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authorChris Zhong <zyw@rock-chips.com>2017-03-22 04:54:48 +0300
committerSean Paul <seanpaul@chromium.org>2017-03-24 21:48:58 +0300
commit25f0b120727e0f191f6a4f6b4476a2191c22497a (patch)
treeb793517e24e4a82bb5b8f2c7017e98d022d02ac7 /drivers/gpu/drm/rockchip
parent8820b68bd378db1821b23b93dbb5a1a06cbbdfdd (diff)
downloadlinux-25f0b120727e0f191f6a4f6b4476a2191c22497a.tar.xz
drm/rockchip/dsi: check phy_cfg_clk only for RK3399
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1490147691-4489-2-git-send-email-zyw@rock-chips.com
Diffstat (limited to 'drivers/gpu/drm/rockchip')
-rw-r--r--drivers/gpu/drm/rockchip/dw-mipi-dsi.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 9360250777ba..ccfb86a1c501 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -251,6 +251,8 @@
#define THS_PRE_PROGRAM_EN BIT(7)
#define THS_ZERO_PROGRAM_EN BIT(6)
+#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
+
enum {
BANDGAP_97_07,
BANDGAP_98_05,
@@ -279,6 +281,7 @@ struct dw_mipi_dsi_plat_data {
u32 grf_switch_reg;
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
+ unsigned int flags;
unsigned int max_data_lanes;
};
@@ -1136,6 +1139,7 @@ static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
.grf_switch_reg = RK3399_GRF_SOC_CON19,
.grf_dsi0_mode = RK3399_GRF_DSI_MODE,
.grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
+ .flags = DW_MIPI_NEEDS_PHY_CFG_CLK,
.max_data_lanes = 4,
};
@@ -1227,15 +1231,13 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
clk_disable_unprepare(dsi->pclk);
}
- dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
- if (IS_ERR(dsi->phy_cfg_clk)) {
- ret = PTR_ERR(dsi->phy_cfg_clk);
- if (ret != -ENOENT) {
+ if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
+ dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+ if (IS_ERR(dsi->phy_cfg_clk)) {
+ ret = PTR_ERR(dsi->phy_cfg_clk);
dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
return ret;
}
- dsi->phy_cfg_clk = NULL;
- dev_dbg(dev, "have not phy_cfg_clk\n");
}
ret = clk_prepare_enable(dsi->pllref_clk);