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authorJernej Skrabec <jernej.skrabec@siol.net>2018-07-06 19:47:32 +0300
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-07-12 19:48:11 +0300
commitf88c5ee77496886071e76b5b9fdfee7158f6d079 (patch)
treef303cf42567da00f649e3fdf3638622f6ceacef3 /drivers/gpu/drm/sun4i/sun8i_mixer.c
parent42ac03213b7f102682157c2821e3fd9657ce4eb7 (diff)
downloadlinux-f88c5ee77496886071e76b5b9fdfee7158f6d079.tar.xz
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun8i_mixer.c')
-rw-r--r--drivers/gpu/drm/sun4i/sun8i_mixer.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index da34fc394902..f76a5576c0e6 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -261,6 +261,17 @@ const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)
return NULL;
}
+static void sun8i_mixer_atomic_begin(struct sunxi_engine *engine,
+ struct drm_crtc_state *old_state)
+{
+ /*
+ * Disable all pipes at the beginning. They will be enabled
+ * again if needed in plane update callback.
+ */
+ regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_PIPE_CTL,
+ SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
+}
+
static void sun8i_mixer_commit(struct sunxi_engine *engine)
{
DRM_DEBUG_DRIVER("Committing changes\n");
@@ -312,6 +323,7 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
}
static const struct sunxi_engine_ops sun8i_engine_ops = {
+ .atomic_begin = sun8i_mixer_atomic_begin,
.commit = sun8i_mixer_commit,
.layers_init = sun8i_layers_init,
};
@@ -477,9 +489,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
SUN8I_MIXER_BLEND_COLOR_BLACK);
- /* Fixed zpos for now */
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE, 0x43210);
-
plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
for (i = 0; i < plane_cnt; i++)
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(i),