diff options
author | Thierry Reding <treding@nvidia.com> | 2015-07-07 21:52:07 +0300 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 13:18:45 +0300 |
commit | db199502fa8b62afddde5379d94cac0439202111 (patch) | |
tree | 521dc19609846d80d89d81193fb5fc16d5cab368 /drivers/gpu/drm/tegra/dp.c | |
parent | cb072eebfa038361b4f578b65a205ad0abc6fe88 (diff) | |
download | linux-db199502fa8b62afddde5379d94cac0439202111.tar.xz |
drm/tegra: dp: Read TPS3 capability from sink
The TPS3 capability can be exposed by DP 1.2 and later sinks if they
support the alternative training pattern for channel equalization.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dp.c')
-rw-r--r-- | drivers/gpu/drm/tegra/dp.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 97fc0225483f..e22ebab677b9 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -11,6 +11,7 @@ static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) { caps->enhanced_framing = false; + caps->tps3_supported = false; caps->fast_training = false; } @@ -18,6 +19,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, const struct drm_dp_link_caps *src) { dest->enhanced_framing = src->enhanced_framing; + dest->tps3_supported = src->tps3_supported; dest->fast_training = src->fast_training; } @@ -63,6 +65,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->max_lanes = drm_dp_max_lane_count(dpcd); link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); + link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->rate = link->max_rate; |