diff options
author | Mikko Perttunen <mperttunen@nvidia.com> | 2022-09-20 11:12:02 +0300 |
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committer | Thierry Reding <treding@nvidia.com> | 2022-11-25 18:14:58 +0300 |
commit | b7dc179ec83e2579ba2cfc6c6a979d91b2c7ccd1 (patch) | |
tree | 27ed5eda562ac3685e09ef092bd4d20ecb439808 /drivers/gpu/drm/tegra/riscv.h | |
parent | 95ffcb4c2ce62b6d666766f3956826552688687c (diff) | |
download | linux-b7dc179ec83e2579ba2cfc6c6a979d91b2c7ccd1.tar.xz |
drm/tegra: Add code for booting RISC-V based engines
Add helper code for booting RISC-V based engines where firmware is
located in a carveout.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/riscv.h')
-rw-r--r-- | drivers/gpu/drm/tegra/riscv.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/riscv.h b/drivers/gpu/drm/tegra/riscv.h new file mode 100644 index 000000000000..bbeb2db078b6 --- /dev/null +++ b/drivers/gpu/drm/tegra/riscv.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, NVIDIA Corporation. + */ + +#ifndef DRM_TEGRA_RISCV_H +#define DRM_TEGRA_RISCV_H + +struct tegra_drm_riscv_descriptor { + u32 manifest_offset; + u32 code_offset; + u32 code_size; + u32 data_offset; + u32 data_size; +}; + +struct tegra_drm_riscv { + /* User initializes */ + struct device *dev; + void __iomem *regs; + + struct tegra_drm_riscv_descriptor bl_desc; + struct tegra_drm_riscv_descriptor os_desc; +}; + +int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv); +int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, + u32 gscid, const struct tegra_drm_riscv_descriptor *desc); + +#endif |