diff options
| author | Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> | 2023-07-18 13:45:28 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:40:27 +0300 |
| commit | 7407f2e5c356a73ec4a6d7f379e91f205025165c (patch) | |
| tree | 443d130619c1b82a6cf5b49d9b1105c2ca040680 /drivers/gpu/drm/xe/regs/xe_engine_regs.h | |
| parent | 25063811d9c1f32c3223c27cafc0a95e7a86be26 (diff) | |
| download | linux-7407f2e5c356a73ec4a6d7f379e91f205025165c.tar.xz | |
drm/xe/pvc: Force even num engines to use 64B
Wa_16017236439 requires that we update BCS_SWCTRL
(via indirect context batch buffer) to set 64B
transfers when running on an even-numbered BCS
engine and 256B on an odd-numbered BCS engine.
v2: Move WA from engine_was[] to lrc_was[]
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_engine_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_engine_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index 1a366d8070f3..692213d09cea 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -64,6 +64,7 @@ #define RING_BBADDR_UDW(base) XE_REG((base) + 0x168) #define BCS_SWCTRL(base) XE_REG((base) + 0x200, XE_REG_OPTION_MASKED) +#define BCS_SWCTRL_DISABLE_256B REG_BIT(2) /* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */ #define BLIT_CCTL(base) XE_REG((base) + 0x204) |