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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-10-16 19:34:54 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:43:00 +0300 |
| commit | 0134f130e76ad6e323e15ccb00624586c8763075 (patch) | |
| tree | 3b25773b659f84ab336a48d2a0a580bef9a9a9f6 /drivers/gpu/drm/xe/regs | |
| parent | 14a1e6a4a460fceae50fc1cf6b50d36c4ba96a7b (diff) | |
| download | linux-0134f130e76ad6e323e15ccb00624586c8763075.tar.xz | |
drm/xe: Extract MI_* instructions to their own header
Extracting the common MI_* instructions that can be used with any engine
to their own header will make it easier as we add additional engine
instructions in upcoming patches.
Also, since the majority of GPU instructions (both MI and non-MI) have
a "length" field in bits 7:0 of the instruction header, a common define
is added for that. Instruction-specific length fields are still defined
for special case instructions that have larger/smaller length fields.
v2:
- Use "instr" instead of "inst" as the short form of "instruction"
everywhere. (Lucas)
- Include xe_reg_defs.h instead of the i915 compat header. (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231016163449.1300701-12-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h index 8c2e0da694d8..4402f72481dc 100644 --- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h @@ -8,45 +8,6 @@ #include "regs/xe_reg_defs.h" -#define INSTR_CLIENT_SHIFT 29 -#define INSTR_MI_CLIENT 0x0 -#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT) - -#define MI_INSTR(opcode, flags) \ - (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags)) - -#define MI_NOOP MI_INSTR(0, 0) -#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) - -#define MI_ARB_ON_OFF MI_INSTR(0x08, 0) -#define MI_ARB_ENABLE (1<<0) -#define MI_ARB_DISABLE (0<<0) - -#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) -#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0) -#define MI_SDI_GGTT REG_BIT(22) -#define MI_SDI_NUM_DW(x) ((x) + 1) -#define MI_SDI_NUM_QW(x) (REG_BIT(21) | (2 * (x) + 1)) - -#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 0) -#define MI_LRI_LRM_CS_MMIO REG_BIT(19) -#define MI_LRI_MMIO_REMAP_EN REG_BIT(17) -#define MI_LRI_LENGTH GENMASK(5, 0) -#define MI_LRI_NUM_REGS(x) REG_FIELD_PREP(MI_LRI_LENGTH, 2 * (x) - 1) -#define MI_LRI_FORCE_POSTED (1<<12) - -#define MI_FLUSH_DW MI_INSTR(0x26, 0) -#define MI_FLUSH_DW_STORE_INDEX (1<<21) -#define MI_INVALIDATE_TLB (1<<18) -#define MI_FLUSH_DW_CCS (1<<16) -#define MI_FLUSH_DW_OP_STOREDW (1<<14) -#define MI_FLUSH_DW_USE_GTT (1<<2) -#define MI_FLUSH_LENGTH GENMASK(5, 0) -#define MI_FLUSH_IMM_DW REG_FIELD_PREP(MI_FLUSH_LENGTH, 2) -#define MI_FLUSH_IMM_QW REG_FIELD_PREP(MI_FLUSH_LENGTH, 3) - -#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 1) - #define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3) #define SRC_ACCESS_TYPE_SHIFT 21 #define DST_ACCESS_TYPE_SHIFT 20 @@ -106,6 +67,4 @@ #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) -#define MI_ARB_CHECK MI_INSTR(0x05, 0) - #endif |