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| author | Vitaly Lubart <vitaly.lubart@intel.com> | 2023-08-28 13:07:07 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:42:59 +0300 |
| commit | 5120243bfb0dabc9f16924a5fc66e8ef26f0f8d3 (patch) | |
| tree | 0a22d4ac82c5ad980ef41c0bdde704c1e1059f5f /drivers/gpu/drm/xe/regs | |
| parent | cd0adf746527dc2d1410adf5bf09ee6f4cd22a79 (diff) | |
| download | linux-5120243bfb0dabc9f16924a5fc66e8ef26f0f8d3.tar.xz | |
drm/xe/gsc: add HECI2 register offsets
Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 1574d11d4e14..e4408473e802 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -33,6 +33,10 @@ #define XEHPC_BCS6_RING_BASE 0x3ea000 #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 + +#define DG1_GSC_HECI2_BASE 0x00259000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define GSCCS_RING_BASE 0x11a000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) |