diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-12-14 21:47:03 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:46:16 +0300 |
| commit | 68df8642ea34bf313757b671f57a4d123458c3f8 (patch) | |
| tree | 3deb06d0c3d14b4f1fdf34acb752d991ff2c2730 /drivers/gpu/drm/xe/regs | |
| parent | 5ea7fe65fb1cf95d9b48fcc3c7c806ce417357c2 (diff) | |
| download | linux-68df8642ea34bf313757b671f57a4d123458c3f8.tar.xz | |
drm/xe: Fix whitespace in register definitions
Our register headers use tabs to align the definition values. Convert a
few definitions that were using spaces instead.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231214184659.2249559-13-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_engine_regs.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_regs.h | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index e109ef912706..7f82bef3a0db 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -136,8 +136,8 @@ #define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1) #define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0) -#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08) -#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5) +#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08) +#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5) #define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10) #define IECPUNIT_CLKGATE_DIS REG_BIT(22) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 4ac71b605487..4b427ec8cbff 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -34,9 +34,9 @@ #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 -#define DG1_GSC_HECI2_BASE 0x00259000 -#define PVC_GSC_HECI2_BASE 0x00285000 -#define DG2_GSC_HECI2_BASE 0x00374000 +#define DG1_GSC_HECI2_BASE 0x00259000 +#define PVC_GSC_HECI2_BASE 0x00285000 +#define DG2_GSC_HECI2_BASE 0x00374000 #define GSCCS_RING_BASE 0x11a000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) |