diff options
| author | Tejas Upadhyay <tejas.upadhyay@intel.com> | 2023-12-05 08:21:59 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:45:24 +0300 |
| commit | 6a1fd6787d59a1852e89a9e8863673ae4dc9a2ca (patch) | |
| tree | 76a356d6edfe9cd251452a80c42f7e49e9868279 /drivers/gpu/drm/xe/regs | |
| parent | d8b1571312b7f77aeae2b2a7a138bb8edaa4f725 (diff) | |
| download | linux-6a1fd6787d59a1852e89a9e8863673ae4dc9a2ca.tar.xz | |
drm/xe/xe2: Add workaround 14019988906
This workaround applies to Graphics 20.04 as engine
workaround
V2(MattR):
- Reorder bit define
- Apply WA for RCS only
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index d318ec0efd7d..e8dc463a49f6 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -124,6 +124,7 @@ #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) #define XEHP_PSS_CHICKEN XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED) +#define FLSH_IGNORES_PSD REG_BIT(10) #define FD_END_COLLECT REG_BIT(5) #define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) |