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authorTejas Upadhyay <tejas.upadhyay@intel.com>2023-11-23 13:39:00 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-21 19:44:56 +0300
commit8bfbe174d7fabf4c6d26e90a133b3129c4e98cbe (patch)
treecbe202b480039d37f85dfae43c1ecd3797e5691e /drivers/gpu/drm/xe/regs
parentf25d8291aca1ccfb0118ec4c0e98f6301bff15ec (diff)
downloadlinux-8bfbe174d7fabf4c6d26e90a133b3129c4e98cbe.tar.xz
drm/xe/xe2: Add workaround 14019449301
This workaround applies to Xe2_LPM V3(MattR): - Reorder reg and wa placement - Add base parameter to reg macro for better definition V2(MattR): - Change name of register - Loop for all engines - Driver permanent WA, applies to all steps Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs')
-rw-r--r--drivers/gpu/drm/xe/regs/xe_engine_regs.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index b57dec17eb2d..444ff9b83bb1 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -112,6 +112,9 @@
#define RING_EXECLIST_CONTROL(base) XE_REG((base) + 0x550)
#define EL_CTRL_LOAD REG_BIT(0)
+#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)
+#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)
+
#define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10)
#define IECPUNIT_CLKGATE_DIS REG_BIT(22)