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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-10-16 19:34:52 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:43:00 +0300 |
| commit | e12a64881e97a78694012646cabd211399db8753 (patch) | |
| tree | 8d833c37958a332cd33dbd478f2f816106d7f08a /drivers/gpu/drm/xe/regs | |
| parent | de54bb81d9d43d0b66a63d839963e9d359e0467d (diff) | |
| download | linux-e12a64881e97a78694012646cabd211399db8753.tar.xz | |
drm/xe: Separate number of registers from MI_LRI opcode
Keeping the number of registers to be loaded as a separate macro from
the instruction opcode will simplify some upcoming LRC parsing code.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231016163449.1300701-10-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h index 9432a960346b..ad1e5466671b 100644 --- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h @@ -25,9 +25,11 @@ #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) #define MI_STORE_DATA_IMM MI_INSTR(0x20, 0) -#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) +#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 0) #define MI_LRI_LRM_CS_MMIO REG_BIT(19) #define MI_LRI_MMIO_REMAP_EN REG_BIT(17) +#define MI_LRI_LENGTH GENMASK(5, 0) +#define MI_LRI_NUM_REGS(x) REG_FIELD_PREP(MI_LRI_LENGTH, 2 * (x) - 1) #define MI_LRI_FORCE_POSTED (1<<12) #define MI_FLUSH_DW MI_INSTR(0x26, 0) |