diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-13 02:28:41 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:31:43 +0300 |
| commit | 58e19acf0cdf3f18c1c868165f45d3ea626b9c3f (patch) | |
| tree | 2f28cc6fbe20f8092f5edba55798621281fa073e /drivers/gpu/drm/xe/xe_bo.h | |
| parent | 9d3c8fb98ba31873c0ebbc42c5d8133fa59f7ac7 (diff) | |
| download | linux-58e19acf0cdf3f18c1c868165f45d3ea626b9c3f.tar.xz | |
drm/xe: Cleanup page-related defines
Rename the following defines to lose the GEN* prefixes since they don't
make sense for xe:
GEN8_PTE_SHIFT -> XE_PTE_SHIFT
GEN8_PAGE_SIZE -> XE_PAGE_SIZE
GEN8_PTE_MASK -> XE_PTE_MASK
GEN8_PDE_SHIFT -> XE_PDE_SHIFT
GEN8_PDES -> XE_PDES
GEN8_PDE_MASK -> XE_PDE_MASK
GEN8_64K_PTE_SHIFT -> XE_64K_PTE_SHIFT
GEN8_64K_PAGE_SIZE -> XE_64K_PAGE_SIZE
GEN8_64K_PTE_MASK -> XE_64K_PTE_MASK
GEN8_64K_PDE_MASK -> XE_64K_PDE_MASK
GEN8_PDE_PS_2M -> XE_PDE_PS_2M
GEN8_PDPE_PS_1G -> XE_PDPE_PS_1G
GEN8_PDE_IPS_64K -> XE_PDE_IPS_64K
GEN12_GGTT_PTE_LM -> XE_GGTT_PTE_LM
GEN12_USM_PPGTT_PTE_AE -> XE_USM_PPGTT_PTE_AE
GEN12_PPGTT_PTE_LM -> XE_PPGTT_PTE_LM
GEN12_PDE_64K -> XE_PDE_64K
GEN12_PTE_PS64 -> XE_PTE_PS64
GEN8_PAGE_PRESENT -> XE_PAGE_PRESENT
GEN8_PAGE_RW -> XE_PAGE_RW
PTE_READ_ONLY -> XE_PTE_READ_ONLY
Keep an XE_ prefix to make sure we don't mix the defines for the CPU
(e.g. PAGE_SIZE) with the ones fro the GPU).
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_bo.h')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_bo.h | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h index effa9d0cf0f6..8354d05ccdf3 100644 --- a/drivers/gpu/drm/xe/xe_bo.h +++ b/drivers/gpu/drm/xe/xe_bo.h @@ -39,32 +39,32 @@ #define PPAT_CACHED BIT_ULL(7) #define PPAT_DISPLAY_ELLC BIT_ULL(4) -#define GEN8_PTE_SHIFT 12 -#define GEN8_PAGE_SIZE (1 << GEN8_PTE_SHIFT) -#define GEN8_PTE_MASK (GEN8_PAGE_SIZE - 1) -#define GEN8_PDE_SHIFT (GEN8_PTE_SHIFT - 3) -#define GEN8_PDES (1 << GEN8_PDE_SHIFT) -#define GEN8_PDE_MASK (GEN8_PDES - 1) - -#define GEN8_64K_PTE_SHIFT 16 -#define GEN8_64K_PAGE_SIZE (1 << GEN8_64K_PTE_SHIFT) -#define GEN8_64K_PTE_MASK (GEN8_64K_PAGE_SIZE - 1) -#define GEN8_64K_PDE_MASK (GEN8_PDE_MASK >> 4) - -#define GEN8_PDE_PS_2M BIT_ULL(7) -#define GEN8_PDPE_PS_1G BIT_ULL(7) -#define GEN8_PDE_IPS_64K BIT_ULL(11) - -#define GEN12_GGTT_PTE_LM BIT_ULL(1) -#define GEN12_USM_PPGTT_PTE_AE BIT_ULL(10) -#define GEN12_PPGTT_PTE_LM BIT_ULL(11) -#define GEN12_PDE_64K BIT_ULL(6) -#define GEN12_PTE_PS64 BIT_ULL(8) - -#define GEN8_PAGE_PRESENT BIT_ULL(0) -#define GEN8_PAGE_RW BIT_ULL(1) - -#define PTE_READ_ONLY BIT(0) +#define XE_PTE_SHIFT 12 +#define XE_PAGE_SIZE (1 << XE_PTE_SHIFT) +#define XE_PTE_MASK (XE_PAGE_SIZE - 1) +#define XE_PDE_SHIFT (XE_PTE_SHIFT - 3) +#define XE_PDES (1 << XE_PDE_SHIFT) +#define XE_PDE_MASK (XE_PDES - 1) + +#define XE_64K_PTE_SHIFT 16 +#define XE_64K_PAGE_SIZE (1 << XE_64K_PTE_SHIFT) +#define XE_64K_PTE_MASK (XE_64K_PAGE_SIZE - 1) +#define XE_64K_PDE_MASK (XE_PDE_MASK >> 4) + +#define XE_PDE_PS_2M BIT_ULL(7) +#define XE_PDPE_PS_1G BIT_ULL(7) +#define XE_PDE_IPS_64K BIT_ULL(11) + +#define XE_GGTT_PTE_LM BIT_ULL(1) +#define XE_USM_PPGTT_PTE_AE BIT_ULL(10) +#define XE_PPGTT_PTE_LM BIT_ULL(11) +#define XE_PDE_64K BIT_ULL(6) +#define XE_PTE_PS64 BIT_ULL(8) + +#define XE_PAGE_PRESENT BIT_ULL(0) +#define XE_PAGE_RW BIT_ULL(1) + +#define XE_PTE_READ_ONLY BIT(0) #define XE_PL_SYSTEM TTM_PL_SYSTEM #define XE_PL_TT TTM_PL_TT |