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authorMatt Roper <matthew.d.roper@intel.com>2023-06-02 00:52:19 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-20 02:34:11 +0300
commit3b0d4a5579968f1c42044142a4997bab9fe7ffed (patch)
treec8351f2fe7c3e997bc555ce935158b76a4f5a305 /drivers/gpu/drm/xe/xe_device_types.h
parent3643e6371542cc4782d3700f07130c9d250666d8 (diff)
downloadlinux-3b0d4a5579968f1c42044142a4997bab9fe7ffed.tar.xz
drm/xe: Move register MMIO into xe_tile
Each tile has its own register region in the BAR, containing instances of all registers for the platform. In contrast, the multiple GTs within a tile share the same MMIO space; there's just a small subset of registers (the GSI registers) which have multiple copies at different offsets (0x0 for primary GT, 0x380000 for media GT). Move the register MMIO region size/pointers to the tile structure, leaving just the GSI offset information in the GT structure. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20230601215244.678611-7-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_device_types.h')
-rw-r--r--drivers/gpu/drm/xe/xe_device_types.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index b76344a9c33b..107a947a7361 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -75,6 +75,22 @@ struct xe_tile {
struct xe_gt primary_gt;
/* TODO: Add media GT here */
+
+ /**
+ * @mmio: MMIO info for a tile.
+ *
+ * Each tile has its own 16MB space in BAR0, laid out as:
+ * * 0-4MB: registers
+ * * 4MB-8MB: reserved
+ * * 8MB-16MB: global GTT
+ */
+ struct {
+ /** @size: size of tile's MMIO space */
+ size_t size;
+
+ /** @regs: pointer to tile's MMIO space (starting with registers) */
+ void *regs;
+ } mmio;
};
/**