diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-28 01:32:48 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:32:15 +0300 |
| commit | d9b79ad275e7a98c566b3ac4b32950142d6bf9ad (patch) | |
| tree | 787a2885b7b78c60c71bb33345d61f09a7c3926b /drivers/gpu/drm/xe/xe_gt_clock.c | |
| parent | 7b829f6dd638c2cb45c7710bc7cd1d0395ea9bc1 (diff) | |
| download | linux-d9b79ad275e7a98c566b3ac4b32950142d6bf9ad.tar.xz | |
drm/xe: Drop gen afixes from registers
The defines for the registers were brought over from i915 while
bootstrapping the driver. As xe supports TGL and later only, it doesn't
make sense to keep the GEN* prefixes and suffixes in the registers: TGL
is graphics version 12, previously called "GEN12". So drop the prefix
everywhere.
v2:
- Also drop _TGL suffix and reword commit message as suggested
by Matt Roper. While at it, rename VSUNIT_CLKGATE_DIS_TGL to
VSUNIT_CLKGATE2_DIS with the additional "2", so it doesn't clash
with the define for the other register
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-3-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_gt_clock.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt_clock.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c index 60a2966bc1fd..1b7d00284535 100644 --- a/drivers/gpu/drm/xe/xe_gt_clock.c +++ b/drivers/gpu/drm/xe/xe_gt_clock.c @@ -14,16 +14,16 @@ static u32 read_reference_ts_freq(struct xe_gt *gt) { - u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg); + u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE.reg); u32 base_freq, frac_freq; - base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; + base_freq = ((ts_override & TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> + TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; base_freq *= 1000000; frac_freq = ((ts_override & - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); + TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> + TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); frac_freq = 1000000 / (frac_freq + 1); return base_freq + frac_freq; @@ -36,17 +36,17 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg) const u32 f25_mhz = 25000000; const u32 f38_4_mhz = 38400000; u32 crystal_clock = - (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> - GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; + (rpm_config_reg & RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> + RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; switch (crystal_clock) { - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: + case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ : return f24_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: + case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ : return f19_2_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: + case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ : return f38_4_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: + case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ : return f25_mhz; default: XE_BUG_ON("NOT_POSSIBLE"); @@ -74,8 +74,8 @@ int xe_gt_clock_init(struct xe_gt *gt) * register increments from this frequency (it might * increment only every few clock cycle). */ - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + freq >>= 3 - ((c0 & RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> + RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); } gt->info.clock_freq = freq; |