diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-07-27 00:03:52 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:39:15 +0300 |
| commit | 063e09af6e1d9a4f26cdd0eb896c19526cb0afd3 (patch) | |
| tree | 45f5d92bd4ef69d512ce6d6fef66f5f608f6015f /drivers/gpu/drm/xe/xe_guc.c | |
| parent | f83a30f466ebbd56355b1f65ec9bcd5087840ffc (diff) | |
| download | linux-063e09af6e1d9a4f26cdd0eb896c19526cb0afd3.tar.xz | |
drm/xe: Invert mask and val in xe_mmio_wait32.
The order: 'offset, mask, val'; is more common in other
drivers and in special in i915, where any dev could copy
a sequence and end up with unexpected behavior.
Done with coccinelle:
@rule1@
expression gt, reg, val, mask, timeout, out, atomic;
@@
- xe_mmio_wait32(gt, reg, val, mask, timeout, out, atomic)
+ xe_mmio_wait32(gt, reg, mask, val, timeout, out, atomic)
spatch -sp_file mmio.cocci *.c *.h compat-i915-headers/intel_uncore.h \
--in-place
v2: Rebased after changes on xe_guc_mcr usage of xe_mmio_wait32.
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc.c | 25 |
1 files changed, 10 insertions, 15 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index 8ae026838702..2530b6243661 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -290,8 +290,7 @@ int xe_guc_reset(struct xe_guc *guc) xe_mmio_write32(gt, GDRST, GRDOM_GUC); - ret = xe_mmio_wait32(gt, GDRST, 0, GRDOM_GUC, 5000, - &gdrst, false); + ret = xe_mmio_wait32(gt, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); if (ret) { drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n", gdrst); @@ -386,10 +385,9 @@ static int guc_wait_ucode(struct xe_guc *guc) * 200ms. Even at slowest clock, this should be sufficient. And * in the working case, a larger timeout makes no difference. */ - ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS, - FIELD_PREP(GS_UKERNEL_MASK, - XE_GUC_LOAD_STATUS_READY), - GS_UKERNEL_MASK, 200000, &status, false); + ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS, GS_UKERNEL_MASK, + FIELD_PREP(GS_UKERNEL_MASK, XE_GUC_LOAD_STATUS_READY), + 200000, &status, false); if (ret) { struct drm_device *drm = &xe->drm; @@ -639,10 +637,9 @@ retry: xe_guc_notify(guc); - ret = xe_mmio_wait32(gt, reply_reg, - FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, - GUC_HXG_ORIGIN_GUC), - GUC_HXG_MSG_0_ORIGIN, 50000, &reply, false); + ret = xe_mmio_wait32(gt, reply_reg, GUC_HXG_MSG_0_ORIGIN, + FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), + 50000, &reply, false); if (ret) { timeout: drm_err(&xe->drm, "mmio request %#x: no reply %#x\n", @@ -654,11 +651,9 @@ timeout: if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) { - ret = xe_mmio_wait32(gt, reply_reg, - FIELD_PREP(GUC_HXG_MSG_0_TYPE, - GUC_HXG_TYPE_RESPONSE_SUCCESS), - GUC_HXG_MSG_0_TYPE, 1000000, &header, - false); + ret = xe_mmio_wait32(gt, reply_reg, GUC_HXG_MSG_0_TYPE, + FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_SUCCESS), + 1000000, &header, false); if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC)) |