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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-08-11 19:06:15 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:40:26 +0300 |
| commit | 0993b22f93f867b4ed1c1fc3f077fa7e736353d6 (patch) | |
| tree | 5ac5a1ff300519f4806bd9113c52d1c6a254fb11 /drivers/gpu/drm/xe/xe_guc.c | |
| parent | e4751ab5d2fef45d666e64a8766e08e9d60eccfd (diff) | |
| download | linux-0993b22f93f867b4ed1c1fc3f077fa7e736353d6.tar.xz | |
drm/xe/xe2: Program GuC's MOCS on Xe2 and beyond
As with PVC, Xe2 platforms require that the index of an uncached MOCS
entry be programmed into the GUC_SHIM_CONTROL register. This will
likely be needed on future platforms as well.
Xe2 also extends the size of the MOCS index register field from two bits
to four bits. Since these extra bits were unused on PVC, it should be
safe to just increase the size of the mask.
Bspec: 60592
Cc: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index 2493c5859948..e102637c0695 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -326,7 +326,7 @@ static void guc_prepare_xfer(struct xe_guc *guc) shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | GUC_ENABLE_MIA_CACHING; - if (xe->info.platform == XE_PVC) + if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); /* Must program this register before loading the ucode with DMA */ |