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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-28 01:32:48 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:32:15 +0300 |
| commit | d9b79ad275e7a98c566b3ac4b32950142d6bf9ad (patch) | |
| tree | 787a2885b7b78c60c71bb33345d61f09a7c3926b /drivers/gpu/drm/xe/xe_guc.c | |
| parent | 7b829f6dd638c2cb45c7710bc7cd1d0395ea9bc1 (diff) | |
| download | linux-d9b79ad275e7a98c566b3ac4b32950142d6bf9ad.tar.xz | |
drm/xe: Drop gen afixes from registers
The defines for the registers were brought over from i915 while
bootstrapping the driver. As xe supports TGL and later only, it doesn't
make sense to keep the GEN* prefixes and suffixes in the registers: TGL
is graphics version 12, previously called "GEN12". So drop the prefix
everywhere.
v2:
- Also drop _TGL suffix and reword commit message as suggested
by Matt Roper. While at it, rename VSUNIT_CLKGATE_DIS_TGL to
VSUNIT_CLKGATE2_DIS with the additional "2", so it doesn't clash
with the define for the other register
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-3-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index d18f2e25ce56..4e9e9b1aad02 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -278,7 +278,7 @@ int xe_guc_init(struct xe_guc *guc) if (xe_gt_is_media_type(gt)) guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT.reg; else - guc->notify_reg = GEN11_GUC_HOST_INTERRUPT.reg; + guc->notify_reg = GUC_HOST_INTERRUPT.reg; xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); @@ -317,9 +317,9 @@ int xe_guc_reset(struct xe_guc *guc) xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); - xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC); + xe_mmio_write32(gt, GDRST.reg, GRDOM_GUC); - ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5000, + ret = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_GUC, 5000, &gdrst, false); if (ret) { drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n", @@ -362,7 +362,7 @@ static void guc_prepare_xfer(struct xe_guc *guc) /* Must program this register before loading the ucode with DMA */ xe_mmio_write32(gt, GUC_SHIM_CONTROL.reg, shim_flags); - xe_mmio_write32(gt, GEN9_GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE); + xe_mmio_write32(gt, GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE); } /* @@ -575,7 +575,7 @@ int xe_guc_enable_communication(struct xe_guc *guc) guc_enable_irq(guc); - xe_mmio_rmw32(guc_to_gt(guc), GEN6_PMINTRMSK.reg, + xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK.reg, ARAT_EXPIRED_INTRMSK, 0); err = xe_guc_ct_enable(&guc->ct); |