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authorLucas De Marchi <lucas.demarchi@intel.com>2023-02-25 03:15:40 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-20 02:29:21 +0300
commit226bfec858c93797dbd3d47d1418ed68684fa752 (patch)
treecad0ad65d418ebee5abeb546560394ddc810faf7 /drivers/gpu/drm/xe/xe_guc_pc.c
parentb79e8fd954c48fba74b2c3807f6093ce40e9ab7f (diff)
downloadlinux-226bfec858c93797dbd3d47d1418ed68684fa752.tar.xz
drm/xe: Remove dependency on intel_gt_regs.h
Create regs/xe_gt_regs.h file with all the registers and bit definitions used by the xe driver. Eventually the registers may be defined in a different way and since xe doesn't supported below gen12, the number of registers touched is much smaller, so create a new header. The definitions themselves are direct copy from the gt/intel_gt_regs.h file, just sorting the registers by address. Cleaning those up and adhering to a common coding style is left for later. v2: Make the change to MCR_REG location in a separate patch to go through the i915 branch (Matt Roper / Rodrigo) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_pc.c')
-rw-r--r--drivers/gpu/drm/xe/xe_guc_pc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 28b86e8f3f6e..f983f47cefb6 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -9,6 +9,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
@@ -31,7 +32,6 @@
#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
#define RPE_MASK REG_GENMASK(15, 8)
-#include "gt/intel_gt_regs.h"
/* For GEN6_RPNSWREQ.reg to be merged when the definition moves to Xe */
#define REQ_RATIO_MASK REG_GENMASK(31, 23)