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| author | Badal Nilawar <badal.nilawar@intel.com> | 2023-06-09 05:49:54 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:34:14 +0300 |
| commit | 2846d10339a2cc304a1ae55ce75e61eb7f55eb0b (patch) | |
| tree | 6d022019b83c97e2aab6c856237b49f00f1d8e51 /drivers/gpu/drm/xe/xe_guc_pc.c | |
| parent | 6dc3a12fb8185f98b525dbdb02fa5b810c4ff0bc (diff) | |
| download | linux-2846d10339a2cc304a1ae55ce75e61eb7f55eb0b.tar.xz | |
drm/xe: Donot apply forcewake while reading actual frequency
RPSTAT1 is an sgunit register and thus doesn't need forcewake.
MTL_MIRROR_TARGET_WP1 is within an "always on" power domain and thus
doesn't require any forcewake to ensure the register is powered
up and usable. When GT is RC6 the actual frequency reported will be 0.
v2:
- Add bspec index (Anshuman)
- %s/GEN12_RPSTAT1/GT_PERF_STATUS as per bspec
v3: Update Fixes tag
Bspec: 51837, 67651
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230609024954.987039-1-badal.nilawar@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_pc.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc_pc.c | 14 |
1 files changed, 3 insertions, 11 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index 67faa9ee0006..5d5cf4b0d508 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -31,7 +31,7 @@ #define GEN10_FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0) #define RPE_MASK REG_GENMASK(15, 8) -#define GEN12_RPSTAT1 XE_REG(0x1381b4) +#define GT_PERF_STATUS XE_REG(0x1381b4) #define GEN12_CAGF_MASK REG_GENMASK(19, 11) #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) @@ -371,26 +371,18 @@ static ssize_t freq_act_show(struct device *dev, ssize_t ret; xe_device_mem_access_get(gt_to_xe(gt)); - /* - * When in RC6, actual frequency is 0. Let's block RC6 so we are able - * to verify that our freq requests are really happening. - */ - ret = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); - if (ret) - goto out; + /* When in RC6, actual frequency reported will be 0. */ if (xe->info.platform == XE_METEORLAKE) { freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1); freq = REG_FIELD_GET(MTL_CAGF_MASK, freq); } else { - freq = xe_mmio_read32(gt, GEN12_RPSTAT1); + freq = xe_mmio_read32(gt, GT_PERF_STATUS); freq = REG_FIELD_GET(GEN12_CAGF_MASK, freq); } ret = sysfs_emit(buf, "%d\n", decode_freq(freq)); - XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); -out: xe_device_mem_access_put(gt_to_xe(gt)); return ret; } |