diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-28 01:32:53 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:32:21 +0300 |
| commit | 3512a78a3cefcd9ec0177771f637de0fe4a64ea2 (patch) | |
| tree | 274f4114180aff907326184909eca50803f48563 /drivers/gpu/drm/xe/xe_guc_pc.c | |
| parent | 36e22be498fb8361ef411ac7d8cf9404338f6fc2 (diff) | |
| download | linux-3512a78a3cefcd9ec0177771f637de0fe4a64ea2.tar.xz | |
drm/xe: Use XE_REG/XE_REG_MCR
These should replace the _MMIO() and MCR_REG() from i915, with the goal
of being more extensible, allowing to pass the additional fields for
struct xe_reg and struct xe_reg_mcr. Replace all uses of _MMIO() and
MCR_REG() in xe.
Since the RTP, reg-save-restore and WA infra are not ready to use the
new type, just undef the macro like was done for the i915 types
previously. That conversion will come later.
v2: Remove MEDIA_SOFT_SCRATCH_COUNT/MEDIA_SOFT_SCRATCH re-added by
mistake (Matt Roper)
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-8-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_pc.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc_pc.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index 6d59e36b6e5c..72d460d5323b 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -23,18 +23,18 @@ #define MCHBAR_MIRROR_BASE_SNB 0x140000 -#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) -#define RP0_MASK REG_GENMASK(7, 0) -#define RP1_MASK REG_GENMASK(15, 8) -#define RPN_MASK REG_GENMASK(23, 16) +#define GEN6_RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998) +#define RP0_MASK REG_GENMASK(7, 0) +#define RP1_MASK REG_GENMASK(15, 8) +#define RPN_MASK REG_GENMASK(23, 16) -#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0) +#define GEN10_FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0) #define RPE_MASK REG_GENMASK(15, 8) -#define GEN12_RPSTAT1 _MMIO(0x1381b4) +#define GEN12_RPSTAT1 XE_REG(0x1381b4) #define GEN12_CAGF_MASK REG_GENMASK(19, 11) -#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) +#define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) #define MTL_CAGF_MASK REG_GENMASK(8, 0) #define GT_FREQUENCY_MULTIPLIER 50 |