diff options
| author | Vinay Belgaumkar <vinay.belgaumkar@intel.com> | 2023-11-13 22:44:02 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:43:39 +0300 |
| commit | 43efd3ba9f44c46fdb31c8b0f257cf9a2d1b58ae (patch) | |
| tree | f8d66d1c39475569f51c67546a2a180d2d4ff88a /drivers/gpu/drm/xe/xe_guc_pc.c | |
| parent | 08987a8b68207e782decb0f4037964ef036a9de4 (diff) | |
| download | linux-43efd3ba9f44c46fdb31c8b0f257cf9a2d1b58ae.tar.xz | |
drm/xe: Raise GT frequency before GuC/HuC load
Starting GT freq is usually RPn. Raising freq to RP0 will
help speed up GuC load times. As an example, this data was
collected on DG2-
GuC Load time @RPn ~ 41 ms
GuC Load time @RP0 ~ 11 ms
v2: Raise GT freq before hwconfig init. This will speed up
both HuC and GuC loads. Address review comments (Rodrigo).
Also add a small usleep after requesting frequency which gives
pcode some time to react.
v3: Address checkpatch issue
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_pc.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc_pc.c | 49 |
1 files changed, 47 insertions, 2 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index 020c6597cd78..f4ac76d6b2dd 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -247,6 +247,12 @@ static u32 decode_freq(u32 raw) GEN9_FREQ_SCALER); } +static u32 encode_freq(u32 freq) +{ + return DIV_ROUND_CLOSEST(freq * GEN9_FREQ_SCALER, + GT_FREQUENCY_MULTIPLIER); +} + static u32 pc_get_min_freq(struct xe_guc_pc *pc) { u32 freq; @@ -257,6 +263,32 @@ static u32 pc_get_min_freq(struct xe_guc_pc *pc) return decode_freq(freq); } +static void pc_set_manual_rp_ctrl(struct xe_guc_pc *pc, bool enable) +{ + struct xe_gt *gt = pc_to_gt(pc); + u32 state = enable ? RPSWCTL_ENABLE : RPSWCTL_DISABLE; + + /* Allow/Disallow punit to process software freq requests */ + xe_mmio_write32(gt, RP_CONTROL, state); +} + +static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq) +{ + struct xe_gt *gt = pc_to_gt(pc); + u32 rpnswreq; + + pc_set_manual_rp_ctrl(pc, true); + + /* Req freq is in units of 16.66 Mhz */ + rpnswreq = REG_FIELD_PREP(REQ_RATIO_MASK, encode_freq(freq)); + xe_mmio_write32(gt, RPNSWREQ, rpnswreq); + + /* Sleep for a small time to allow pcode to respond */ + usleep_range(100, 300); + + pc_set_manual_rp_ctrl(pc, false); +} + static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq) { /* @@ -685,6 +717,21 @@ static void pc_init_fused_rp_values(struct xe_guc_pc *pc) else tgl_init_fused_rp_values(pc); } + +/** + * xe_guc_pc_init_early - Initialize RPx values and request a higher GT + * frequency to allow faster GuC load times + * @pc: Xe_GuC_PC instance + */ +void xe_guc_pc_init_early(struct xe_guc_pc *pc) +{ + struct xe_gt *gt = pc_to_gt(pc); + + xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); + pc_init_fused_rp_values(pc); + pc_set_cur_freq(pc, pc->rp0_freq); +} + static int pc_adjust_freq_bounds(struct xe_guc_pc *pc) { int ret; @@ -918,8 +965,6 @@ int xe_guc_pc_init(struct xe_guc_pc *pc) pc->bo = bo; - pc_init_fused_rp_values(pc); - err = sysfs_create_files(gt->sysfs, pc_attrs); if (err) return err; |