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| author | Badal Nilawar <badal.nilawar@intel.com> | 2023-06-23 08:24:31 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:35:02 +0300 |
| commit | 7b076d14f21a48de572e5191614b3e6b2d6ab823 (patch) | |
| tree | d811a9a226e59dbe836517565948d172a7914628 /drivers/gpu/drm/xe/xe_guc_pc.c | |
| parent | 1c2097bbde107effe2183891f92c060aa64bfa8b (diff) | |
| download | linux-7b076d14f21a48de572e5191614b3e6b2d6ab823.tar.xz | |
drm/xe/mtl: Add support to get C6 residency/status of MTL
Add the registers to get C6 residency of MTL SAMedia and
C6 status of MTL gts
v2:
- move register definitions to regs header (Anshuman)
- correct reg definition for mtl rc status
- make idle_status function common (Badal)
v3:
- remove extra line in commit message
- use only media type check in initialization
- use graphics ver check (Anshuman)
v4:
- remove extra lines (Anshuman)
Bspec: 66300
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_pc.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc_pc.c | 41 |
1 files changed, 31 insertions, 10 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index f02bf1641380..3093cfeff0c2 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -34,9 +34,6 @@ #define GT_PERF_STATUS XE_REG(0x1381b4) #define GEN12_CAGF_MASK REG_GENMASK(19, 11) -#define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) -#define MTL_CAGF_MASK REG_GENMASK(8, 0) - #define GT_FREQUENCY_MULTIPLIER 50 #define GEN9_FREQ_SCALER 3 @@ -568,22 +565,30 @@ out: static DEVICE_ATTR_RW(freq_max); /** - * xe_guc_pc_rc_status - get the current Render C state + * xe_guc_pc_c_status - get the current GT C state * @pc: XE_GuC_PC instance */ -enum xe_gt_idle_state xe_guc_pc_rc_status(struct xe_guc_pc *pc) +enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc) { struct xe_gt *gt = pc_to_gt(pc); - u32 reg; + u32 reg, gt_c_state; xe_device_mem_access_get(gt_to_xe(gt)); - reg = xe_mmio_read32(gt, GT_CORE_STATUS); + + if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) { + reg = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1); + gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg); + } else { + reg = xe_mmio_read32(gt, GT_CORE_STATUS); + gt_c_state = REG_FIELD_GET(RCN_MASK, reg); + } + xe_device_mem_access_put(gt_to_xe(gt)); - switch (REG_FIELD_GET(RCN_MASK, reg)) { - case GT_RC6: + switch (gt_c_state) { + case GT_C6: return GT_IDLE_C6; - case GT_RC0: + case GT_C0: return GT_IDLE_C0; default: return GT_IDLE_UNKNOWN; @@ -606,6 +611,22 @@ u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc) return reg; } +/** + * xe_guc_pc_mc6_residency - mc6 residency counter + * @pc: Xe_GuC_PC instance + */ +u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc) +{ + struct xe_gt *gt = pc_to_gt(pc); + u64 reg; + + xe_device_mem_access_get(gt_to_xe(gt)); + reg = xe_mmio_read32(gt, MTL_MEDIA_MC6); + xe_device_mem_access_put(gt_to_xe(gt)); + + return reg; +} + static const struct attribute *pc_attrs[] = { &dev_attr_freq_act.attr, &dev_attr_freq_cur.attr, |