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authorMatt Roper <matthew.d.roper@intel.com>2023-04-01 03:20:59 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-20 02:31:30 +0300
commit06d06064f725c207a4d14b7410f5498d68c1fb86 (patch)
treee51e82d076d5c1d908625546a8f2ebfcda7bf774 /drivers/gpu/drm/xe/xe_irq.c
parent1a545ed74b33eaf6dee6d4159be07819ad89a569 (diff)
downloadlinux-06d06064f725c207a4d14b7410f5498d68c1fb86.tar.xz
drm/xe/irq: Drop gen3_ prefixes
"Gen" terminology should be avoided in the Xe driver and "gen3" refers to platforms that are 9 (!!) graphics generations earlier than the oldest supported by the Xe driver, so this prefix really doesn't make sense. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20230401002106.588656-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_irq.c')
-rw-r--r--drivers/gpu/drm/xe/xe_irq.c42
1 files changed, 20 insertions, 22 deletions
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 9527e7fb9b6e..afaebc0c589e 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -18,7 +18,7 @@
#include "xe_hw_engine.h"
#include "xe_mmio.h"
-static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
+static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
{
u32 val = xe_mmio_read32(gt, reg.reg);
@@ -34,24 +34,24 @@ static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
xe_mmio_read32(gt, reg.reg);
}
-static void gen3_irq_init(struct xe_gt *gt,
- i915_reg_t imr, u32 imr_val,
- i915_reg_t ier, u32 ier_val,
- i915_reg_t iir)
+static void irq_init(struct xe_gt *gt,
+ i915_reg_t imr, u32 imr_val,
+ i915_reg_t ier, u32 ier_val,
+ i915_reg_t iir)
{
- gen3_assert_iir_is_zero(gt, iir);
+ assert_iir_is_zero(gt, iir);
xe_mmio_write32(gt, ier.reg, ier_val);
xe_mmio_write32(gt, imr.reg, imr_val);
xe_mmio_read32(gt, imr.reg);
}
-#define GEN3_IRQ_INIT(gt, type, imr_val, ier_val) \
- gen3_irq_init((gt), \
- type##IMR, imr_val, \
- type##IER, ier_val, \
- type##IIR)
+#define IRQ_INIT(gt, type, imr_val, ier_val) \
+ irq_init((gt), \
+ type##IMR, imr_val, \
+ type##IER, ier_val, \
+ type##IIR)
-static void gen3_irq_reset(struct xe_gt *gt, i915_reg_t imr, i915_reg_t iir,
+static void irq_reset(struct xe_gt *gt, i915_reg_t imr, i915_reg_t iir,
i915_reg_t ier)
{
xe_mmio_write32(gt, imr.reg, 0xffffffff);
@@ -65,8 +65,8 @@ static void gen3_irq_reset(struct xe_gt *gt, i915_reg_t imr, i915_reg_t iir,
xe_mmio_write32(gt, iir.reg, 0xffffffff);
xe_mmio_read32(gt, iir.reg);
}
-#define GEN3_IRQ_RESET(gt, type) \
- gen3_irq_reset((gt), type##IMR, type##IIR, type##IER)
+#define IRQ_RESET(gt, type) \
+ irq_reset((gt), type##IMR, type##IIR, type##IER)
static u32 gen11_intr_disable(struct xe_gt *gt)
{
@@ -172,8 +172,7 @@ static void gen11_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
gen11_gt_irq_postinstall(xe, gt);
- GEN3_IRQ_INIT(gt, GEN11_GU_MISC_, ~GEN11_GU_MISC_GSE,
- GEN11_GU_MISC_GSE);
+ IRQ_INIT(gt, GEN11_GU_MISC_, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
gen11_intr_enable(gt, true);
}
@@ -332,8 +331,7 @@ static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
{
gen11_gt_irq_postinstall(xe, gt);
- GEN3_IRQ_INIT(gt, GEN11_GU_MISC_, ~GEN11_GU_MISC_GSE,
- GEN11_GU_MISC_GSE);
+ IRQ_INIT(gt, GEN11_GU_MISC_, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
if (gt->info.id == XE_GT0)
dg1_intr_enable(xe, true);
@@ -434,8 +432,8 @@ static void gen11_irq_reset(struct xe_gt *gt)
gen11_gt_irq_reset(gt);
- GEN3_IRQ_RESET(gt, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(gt, GEN8_PCU_);
+ IRQ_RESET(gt, GEN11_GU_MISC_);
+ IRQ_RESET(gt, GEN8_PCU_);
}
static void dg1_irq_reset(struct xe_gt *gt)
@@ -445,8 +443,8 @@ static void dg1_irq_reset(struct xe_gt *gt)
gen11_gt_irq_reset(gt);
- GEN3_IRQ_RESET(gt, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(gt, GEN8_PCU_);
+ IRQ_RESET(gt, GEN11_GU_MISC_);
+ IRQ_RESET(gt, GEN8_PCU_);
}
static void xe_irq_reset(struct xe_device *xe)