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authorLucas De Marchi <lucas.demarchi@intel.com>2023-04-28 01:32:53 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-20 02:32:21 +0300
commit3512a78a3cefcd9ec0177771f637de0fe4a64ea2 (patch)
tree274f4114180aff907326184909eca50803f48563 /drivers/gpu/drm/xe/xe_irq.c
parent36e22be498fb8361ef411ac7d8cf9404338f6fc2 (diff)
downloadlinux-3512a78a3cefcd9ec0177771f637de0fe4a64ea2.tar.xz
drm/xe: Use XE_REG/XE_REG_MCR
These should replace the _MMIO() and MCR_REG() from i915, with the goal of being more extensible, allowing to pass the additional fields for struct xe_reg and struct xe_reg_mcr. Replace all uses of _MMIO() and MCR_REG() in xe. Since the RTP, reg-save-restore and WA infra are not ready to use the new type, just undef the macro like was done for the i915 types previously. That conversion will come later. v2: Remove MEDIA_SOFT_SCRATCH_COUNT/MEDIA_SOFT_SCRATCH re-added by mistake (Matt Roper) Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20230427223256.1432787-8-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_irq.c')
-rw-r--r--drivers/gpu/drm/xe/xe_irq.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 9dd730d707e5..2fffb2865cab 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -22,9 +22,9 @@
* Interrupt registers for a unit are always consecutive and ordered
* ISR, IMR, IIR, IER.
*/
-#define IMR(offset) _MMIO(offset + 0x4)
-#define IIR(offset) _MMIO(offset + 0x8)
-#define IER(offset) _MMIO(offset + 0xc)
+#define IMR(offset) XE_REG(offset + 0x4)
+#define IIR(offset) XE_REG(offset + 0x8)
+#define IER(offset) XE_REG(offset + 0xc)
static void assert_iir_is_zero(struct xe_gt *gt, struct xe_reg reg)
{