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| author | Jonathan Cavitt <jonathan.cavitt@intel.com> | 2023-11-04 00:03:24 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:43:34 +0300 |
| commit | d7925d04c062b8adcbbff9604422f979e9dbedb7 (patch) | |
| tree | 30ea067aec17598ff3ffbc3b160483d93213fd0f /drivers/gpu/drm/xe/xe_irq.c | |
| parent | 37d1eaab34ab9cdd6022a188ce6b77a88f81c7e2 (diff) | |
| download | linux-d7925d04c062b8adcbbff9604422f979e9dbedb7.tar.xz | |
drm/xe: clear the serviced bits on INTR_IDENTITY_REG
The spec for this register, like many other interrupt related ones,
asks software to write back '1' to clear the serviced bits. Let's
respect the spec.
v2:
- Update commit message
- Add missing CC
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_irq.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_irq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c index 5631e5e1ea20..ef26120e7aa4 100644 --- a/drivers/gpu/drm/xe/xe_irq.c +++ b/drivers/gpu/drm/xe/xe_irq.c @@ -231,7 +231,7 @@ gt_engine_identity(struct xe_device *xe, return 0; } - xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), INTR_DATA_VALID); + xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), ident); return ident; } |