diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-03-25 00:04:13 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:30:25 +0300 |
| commit | 366974e4a69c09a441eca7802028e60b39903386 (patch) | |
| tree | 17dce95192078756f36caffa1ed8cee0e424963b /drivers/gpu/drm/xe/xe_pat.c | |
| parent | 152d7f2db978780f6c7e95711c00dc1e0888535b (diff) | |
| download | linux-366974e4a69c09a441eca7802028e60b39903386.tar.xz | |
drm/xe/pat: Clean up PAT register definitions
Replace the deprecated "GEN" terminology in the PAT definitions.
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-5-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_pat.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pat.c | 73 |
1 files changed, 38 insertions, 35 deletions
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c index 6e3a74aa46e7..d2935ef0e274 100644 --- a/drivers/gpu/drm/xe/xe_pat.c +++ b/drivers/gpu/drm/xe/xe_pat.c @@ -12,49 +12,52 @@ #define _PAT_INDEX(index) (0x4800 + (index) * 4) -#define GEN8_PPAT_WB (3<<0) -#define GEN8_PPAT_WT (2<<0) -#define GEN8_PPAT_WC (1<<0) -#define GEN8_PPAT_UC (0<<0) -#define GEN12_PPAT_CLOS(x) ((x)<<2) +#define MTL_L4_POLICY_MASK REG_GENMASK(3, 2) +#define MTL_PAT_3_UC REG_FIELD_PREP(MTL_L4_POLICY_MASK, 3) +#define MTL_PAT_1_WT REG_FIELD_PREP(MTL_L4_POLICY_MASK, 1) +#define MTL_PAT_0_WB REG_FIELD_PREP(MTL_L4_POLICY_MASK, 0) +#define MTL_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) +#define MTL_3_COH_2W REG_FIELD_PREP(MTL_INDEX_COH_MODE_MASK, 3) +#define MTL_2_COH_1W REG_FIELD_PREP(MTL_INDEX_COH_MODE_MASK, 2) +#define MTL_0_COH_NON REG_FIELD_PREP(MTL_INDEX_COH_MODE_MASK, 0) + +#define PVC_CLOS_LEVEL_MASK REG_GENMASK(3, 2) +#define PVC_PAT_CLOS(x) REG_FIELD_PREP(PVC_CLOS_LEVEL_MASK, x) + +#define TGL_MEM_TYPE_MASK REG_GENMASK(1, 0) +#define TGL_PAT_WB REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 3) +#define TGL_PAT_WT REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 2) +#define TGL_PAT_WC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 1) +#define TGL_PAT_UC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 0) const u32 tgl_pat_table[] = { - [0] = GEN8_PPAT_WB, - [1] = GEN8_PPAT_WC, - [2] = GEN8_PPAT_WT, - [3] = GEN8_PPAT_UC, - [4] = GEN8_PPAT_WB, - [5] = GEN8_PPAT_WB, - [6] = GEN8_PPAT_WB, - [7] = GEN8_PPAT_WB, + [0] = TGL_PAT_WB, + [1] = TGL_PAT_WC, + [2] = TGL_PAT_WT, + [3] = TGL_PAT_UC, + [4] = TGL_PAT_WB, + [5] = TGL_PAT_WB, + [6] = TGL_PAT_WB, + [7] = TGL_PAT_WB, }; const u32 pvc_pat_table[] = { - [0] = GEN8_PPAT_UC, - [1] = GEN8_PPAT_WC, - [2] = GEN8_PPAT_WT, - [3] = GEN8_PPAT_WB, - [4] = GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT, - [5] = GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB, - [6] = GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT, - [7] = GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB, + [0] = TGL_PAT_UC, + [1] = TGL_PAT_WC, + [2] = TGL_PAT_WT, + [3] = TGL_PAT_WB, + [4] = PVC_PAT_CLOS(1) | TGL_PAT_WT, + [5] = PVC_PAT_CLOS(1) | TGL_PAT_WB, + [6] = PVC_PAT_CLOS(2) | TGL_PAT_WT, + [7] = PVC_PAT_CLOS(2) | TGL_PAT_WB, }; -#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2) -#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) -#define MTL_PPAT_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3) -#define MTL_PPAT_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1) -#define MTL_PPAT_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0) -#define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3) -#define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2) -#define MTL_0_COH_NON REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 0) - const u32 mtl_pat_table[] = { - [0] = MTL_PPAT_0_WB, - [1] = MTL_PPAT_1_WT | MTL_2_COH_1W, - [2] = MTL_PPAT_3_UC | MTL_2_COH_1W, - [3] = MTL_PPAT_0_WB | MTL_2_COH_1W, - [4] = MTL_PPAT_0_WB | MTL_3_COH_2W, + [0] = MTL_PAT_0_WB, + [1] = MTL_PAT_1_WT | MTL_2_COH_1W, + [2] = MTL_PAT_3_UC | MTL_2_COH_1W, + [3] = MTL_PAT_0_WB | MTL_2_COH_1W, + [4] = MTL_PAT_0_WB | MTL_3_COH_2W, }; #define PROGRAM_PAT_UNICAST(gt, table) do { \ |