diff options
author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-09-27 22:38:56 +0300 |
---|---|---|
committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:41:20 +0300 |
commit | b445be5710200501bba693fe6f9c614895412b94 (patch) | |
tree | d25e77f20201e49856adefc30c062e8f229cc104 /drivers/gpu/drm/xe/xe_pat.c | |
parent | 23c8495efeed0d83657de89b44a569ac406bdfad (diff) | |
download | linux-b445be5710200501bba693fe6f9c614895412b94.tar.xz |
drm/xe: Use vfunc to initialize PAT
Split the PAT initialization between SW-only and HW. The _early() only
sets up the ops and data structure that are used later to program the
tables. This allows the PAT to be easily extended to other platforms.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230927193902.2849159-6-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_pat.c')
-rw-r--r-- | drivers/gpu/drm/xe/xe_pat.c | 59 |
1 files changed, 45 insertions, 14 deletions
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c index 71e0e047fff3..28f401c500d8 100644 --- a/drivers/gpu/drm/xe/xe_pat.c +++ b/drivers/gpu/drm/xe/xe_pat.c @@ -32,6 +32,11 @@ #define TGL_PAT_WC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 1) #define TGL_PAT_UC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 0) +struct xe_pat_ops { + void (*program_graphics)(struct xe_gt *gt, const u32 table[], int n_entries); + void (*program_media)(struct xe_gt *gt, const u32 table[], int n_entries); +}; + static const u32 tgl_pat_table[] = { [0] = TGL_PAT_WB, [1] = TGL_PAT_WC, @@ -80,24 +85,37 @@ static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries) } } -void xe_pat_init(struct xe_gt *gt) -{ - struct xe_device *xe = gt_to_xe(gt); +static const struct xe_pat_ops tgl_pat_ops = { + .program_graphics = program_pat, +}; + +static const struct xe_pat_ops dg2_pat_ops = { + .program_graphics = program_pat_mcr, +}; + +/* + * SAMedia register offsets are adjusted by the write methods and they target + * registers that are not MCR, while for normal GT they are MCR + */ +static const struct xe_pat_ops mtl_pat_ops = { + .program_graphics = program_pat, + .program_media = program_pat_mcr, +}; +void xe_pat_init_early(struct xe_device *xe) +{ if (xe->info.platform == XE_METEORLAKE) { - /* - * SAMedia register offsets are adjusted by the write methods - * and they target registers that are not MCR, while for normal - * GT they are MCR - */ - if (xe_gt_is_media_type(gt)) - program_pat(gt, mtl_pat_table, ARRAY_SIZE(mtl_pat_table)); - else - program_pat_mcr(gt, mtl_pat_table, ARRAY_SIZE(mtl_pat_table)); + xe->pat.ops = &mtl_pat_ops; + xe->pat.table = mtl_pat_table; + xe->pat.n_entries = ARRAY_SIZE(mtl_pat_table); } else if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2) { - program_pat_mcr(gt, pvc_pat_table, ARRAY_SIZE(pvc_pat_table)); + xe->pat.ops = &dg2_pat_ops; + xe->pat.table = pvc_pat_table; + xe->pat.n_entries = ARRAY_SIZE(pvc_pat_table); } else if (GRAPHICS_VERx100(xe) <= 1210) { - program_pat(gt, tgl_pat_table, ARRAY_SIZE(tgl_pat_table)); + xe->pat.ops = &tgl_pat_ops; + xe->pat.table = tgl_pat_table; + xe->pat.n_entries = ARRAY_SIZE(tgl_pat_table); } else { /* * Going forward we expect to need new PAT settings for most @@ -111,3 +129,16 @@ void xe_pat_init(struct xe_gt *gt) GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100); } } + +void xe_pat_init(struct xe_gt *gt) +{ + struct xe_device *xe = gt_to_xe(gt); + + if (!xe->pat.ops) + return; + + if (xe_gt_is_media_type(gt)) + xe->pat.ops->program_media(gt, xe->pat.table, xe->pat.n_entries); + else + xe->pat.ops->program_graphics(gt, xe->pat.table, xe->pat.n_entries); +} |