diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-03-25 00:04:14 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:30:25 +0300 |
| commit | f16a3f6335e84c07de4b5dd263f0c26e3a3fa5a4 (patch) | |
| tree | ba2617ec554faf01b006ca5585d470691a777450 /drivers/gpu/drm/xe/xe_pat.c | |
| parent | 366974e4a69c09a441eca7802028e60b39903386 (diff) | |
| download | linux-f16a3f6335e84c07de4b5dd263f0c26e3a3fa5a4.tar.xz | |
drm/xe/mtl: Fix PAT table coherency settings
Re-sync our MTL PAT table with the bspec. 1-way coherency should only
be set on table entry 3. We do not want an incorrect setting here to
accidentally paper over other bugs elsewhere in the driver.
Bspec: 45101
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-6-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_pat.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pat.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c index d2935ef0e274..e83f7895b853 100644 --- a/drivers/gpu/drm/xe/xe_pat.c +++ b/drivers/gpu/drm/xe/xe_pat.c @@ -54,8 +54,8 @@ const u32 pvc_pat_table[] = { const u32 mtl_pat_table[] = { [0] = MTL_PAT_0_WB, - [1] = MTL_PAT_1_WT | MTL_2_COH_1W, - [2] = MTL_PAT_3_UC | MTL_2_COH_1W, + [1] = MTL_PAT_1_WT, + [2] = MTL_PAT_3_UC, [3] = MTL_PAT_0_WB | MTL_2_COH_1W, [4] = MTL_PAT_0_WB | MTL_3_COH_2W, }; |