diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-03-14 03:30:01 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:29:47 +0300 |
| commit | d855d2246ea6b04cbda372846b21c040fb068575 (patch) | |
| tree | abc1dc06f85fd8b57d91063bbff62d432290f300 /drivers/gpu/drm/xe/xe_reg_whitelist.c | |
| parent | 5be84050ddce298503e7290d375b6dcf3ce920d2 (diff) | |
| download | linux-d855d2246ea6b04cbda372846b21c040fb068575.tar.xz | |
drm/xe: Print whitelist while applying
Besides printing the various register save-restore, it's also useful to
know the register being allowed/denied access from unprivileged batch
buffers. Print them during device probe.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230314003012.2600353-4-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_reg_whitelist.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_reg_whitelist.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c index 2dd10e62718f..6c8577e8dba6 100644 --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c @@ -67,3 +67,44 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) { xe_rtp_process(register_whitelist, &hwe->reg_whitelist, hwe->gt, hwe); } + +/** + * xe_reg_whitelist_print_entry - print one whitelist entry + * @p: DRM printer + * @indent: indent level + * @reg: register allowed/denied + * @entry: save-restore entry + * + * Print details about the entry added to allow/deny access + */ +void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent, + u32 reg, struct xe_reg_sr_entry *entry) +{ + u32 val = entry->set_bits; + const char *access_str = "(invalid)"; + unsigned range_bit = 2; + u32 range_start, range_end; + bool deny; + + deny = val & RING_FORCE_TO_NONPRIV_DENY; + + switch (val & RING_FORCE_TO_NONPRIV_RANGE_MASK) { + case RING_FORCE_TO_NONPRIV_RANGE_4: range_bit = 4; break; + case RING_FORCE_TO_NONPRIV_RANGE_16: range_bit = 6; break; + case RING_FORCE_TO_NONPRIV_RANGE_64: range_bit = 8; break; + } + + range_start = reg & REG_GENMASK(25, range_bit); + range_end = range_start | REG_GENMASK(range_bit, 0); + + switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) { + case RING_FORCE_TO_NONPRIV_ACCESS_RW: access_str = "rw"; break; + case RING_FORCE_TO_NONPRIV_ACCESS_RD: access_str = "read"; break; + case RING_FORCE_TO_NONPRIV_ACCESS_WR: access_str = "write"; break; + } + + drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n", + range_start, range_end, + deny ? "deny" : "allow", + access_str); +} |