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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-03-14 03:30:04 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:29:49 +0300 |
| commit | a19220fa5f1a740d98654ee1d6cf11a8e0158018 (patch) | |
| tree | 0fb255616f656b2c12a8114377a4e94d1749b0d5 /drivers/gpu/drm/xe/xe_wa.c | |
| parent | 6b5ccd6360e29e67a760f82d0b28cf7c058732f7 (diff) | |
| download | linux-a19220fa5f1a740d98654ee1d6cf11a8e0158018.tar.xz | |
drm/xe: Add PVC gt workarounds
Synchronize with i915 the PVC gt workarounds as of committ
commit 4d14d7717f19 ("drm/i915/selftest: Fix ktime_get() and h/w
access order").
v2: Add masked flag to XEHPC_LNCFMISCCFGREG0 (Matt Roper)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230314003012.2600353-7-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_wa.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 155cabe16e2e..e8d523033b87 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -180,6 +180,25 @@ static const struct xe_rtp_entry gt_was[] = { XE_RTP_RULES(PLATFORM(DG2)), XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE)) }, + + /* PVC */ + + { XE_RTP_NAME("14015795083"), + XE_RTP_RULES(PLATFORM(PVC)), + XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE)) + }, + { XE_RTP_NAME("18018781329"), + XE_RTP_RULES(PLATFORM(PVC)), + XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), + SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), + SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), + SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) + }, + { XE_RTP_NAME("16016694945"), + XE_RTP_RULES(PLATFORM(PVC)), + XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC, + XE_RTP_ACTION_FLAG(MASKED_REG))) + }, {} }; |