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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-05-08 20:55:52 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-06-14 13:53:12 +0300 |
| commit | 585c9772f883da3ac425e2e8277b2aaceb201f38 (patch) | |
| tree | 0949d9faf38d545002c7040edc50e0e77cd6a6d7 /drivers/iio/adc/ad7298.c | |
| parent | 98295a206d04633bae31f279de11ff7d04724bce (diff) | |
| download | linux-585c9772f883da3ac425e2e8277b2aaceb201f38.tar.xz | |
iio: adc: ad7298: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: be7fd3b86ad2 ("iio:adc:ad7298 make the tx and rx buffers __be16")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-13-jic23@kernel.org
Diffstat (limited to 'drivers/iio/adc/ad7298.c')
| -rw-r--r-- | drivers/iio/adc/ad7298.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/adc/ad7298.c b/drivers/iio/adc/ad7298.c index 3f4e73f7d35a..c0430f71f592 100644 --- a/drivers/iio/adc/ad7298.c +++ b/drivers/iio/adc/ad7298.c @@ -49,7 +49,7 @@ struct ad7298_state { * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. */ - __be16 rx_buf[12] ____cacheline_aligned; + __be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN); __be16 tx_buf[2]; }; |