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author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2020-09-23 15:13:47 +0300 |
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committer | Joerg Roedel <jroedel@suse.de> | 2020-09-24 13:46:54 +0300 |
commit | 54ce12e02e44feffa6de4f3a069b7d5c7262a966 (patch) | |
tree | d498b3d5bd3b481d97170f8e8d991f3ba3add60b /drivers/iommu/Kconfig | |
parent | 2818de6e87defc3103fd86bf6357658f7d2a661a (diff) | |
download | linux-54ce12e02e44feffa6de4f3a069b7d5c7262a966.tar.xz |
iommu/amd: Re-purpose Exclusion range registers to support SNP CWWB
When the IOMMU SNP support bit is set in the IOMMU Extended Features
register, hardware re-purposes the following registers:
1. IOMMU Exclusion Base register (MMIO offset 0020h) to
Completion Wait Write-Back (CWWB) Base register
2. IOMMU Exclusion Range Limit (MMIO offset 0028h) to
Completion Wait Write-Back (CWWB) Range Limit register
and requires the IOMMU CWWB semaphore base and range to be programmed
in the register offset 0020h and 0028h accordingly.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Link: https://lore.kernel.org/r/20200923121347.25365-4-suravee.suthikulpanit@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/Kconfig')
0 files changed, 0 insertions, 0 deletions