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authorLinus Torvalds <torvalds@linux-foundation.org>2023-04-28 03:46:52 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2023-04-28 03:46:52 +0300
commit91ec4b0d11fe115581ce2835300558802ce55e6c (patch)
tree0c31e5d1627212dd459901f899c10f036b571d0e /drivers/irqchip
parent513f17f8d6b67563d977c730d50bc0db6ea6e1b0 (diff)
parent46e614cc91f7bd6f7872e434e6bcfda44454aac3 (diff)
downloadlinux-91ec4b0d11fe115581ce2835300558802ce55e6c.tar.xz
Merge tag 'mips_6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: - added support for Huawei B593u-12 - added support for virt board aligned to QEMU MIPS virt board - added support for doing DMA coherence on a per device base - reworked handling of RALINK SoCs - cleanup for Loongon64 barriers - removed deprecated support for MIPS_CMP SMP handling method - removed support Sibyte CARMEL and CHRINE boards - cleanups and fixes * tag 'mips_6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (59 commits) MIPS: uprobes: Restore thread.trap_nr MIPS: Don't clear _PAGE_SPECIAL in _PAGE_CHG_MASK MIPS: Sink body of check_bugs_early() into its only call site MIPS: Mark check_bugs() as __init Revert "MIPS: generic: Enable all CPUs supported by virt board in Kconfig" MIPS: octeon_switch: Remove duplicated labels MIPS: loongson2ef: Add missing break in cs5536_isa MIPS: Remove set_swbp() in uprobes.c MIPS: Use def_bool y for ARCH_SUPPORTS_UPROBES MIPS: fw: Allow firmware to pass a empty env MIPS: Remove deprecated CONFIG_MIPS_CMP MIPS: lantiq: remove unused function declaration MIPS: Drop unused positional parameter in local_irq_{dis,en}able MIPS: mm: Remove local_cache_flush_page MIPS: Remove no longer used ide.h MIPS: mm: Remove unused *cache_page_indexed flush functions MIPS: generic: Enable all CPUs supported by virt board in Kconfig MIPS: Add board config for virt board MIPS: Octeon: Disable CVMSEG by default on other platforms MIPS: Loongson: Don't select platform features with CPU ...
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/irq-mips-gic.c26
1 files changed, 0 insertions, 26 deletions
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 1a6a7a672ad7..046c355e120b 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -54,7 +54,6 @@ static DEFINE_SPINLOCK(gic_lock);
static struct irq_domain *gic_irq_domain;
static int gic_shared_intrs;
static unsigned int gic_cpu_pin;
-static unsigned int timer_cpu_pin;
static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
#ifdef CONFIG_GENERIC_IRQ_IPI
@@ -499,9 +498,6 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
*/
switch (intr) {
case GIC_LOCAL_INT_TIMER:
- /* CONFIG_MIPS_CMP workaround (see __gic_init) */
- map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
- fallthrough;
case GIC_LOCAL_INT_PERFCTR:
case GIC_LOCAL_INT_FDC:
/*
@@ -795,34 +791,12 @@ static int __init gic_of_init(struct device_node *node,
if (cpu_has_veic) {
/* Always use vector 1 in EIC mode */
gic_cpu_pin = 0;
- timer_cpu_pin = gic_cpu_pin;
set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
__gic_irq_dispatch);
} else {
gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
gic_irq_dispatch);
- /*
- * With the CMP implementation of SMP (deprecated), other CPUs
- * are started by the bootloader and put into a timer based
- * waiting poll loop. We must not re-route those CPU's local
- * timer interrupts as the wait instruction will never finish,
- * so just handle whatever CPU interrupt it is routed to by
- * default.
- *
- * This workaround should be removed when CMP support is
- * dropped.
- */
- if (IS_ENABLED(CONFIG_MIPS_CMP) &&
- gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
- timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
- irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
- GIC_CPU_PIN_OFFSET +
- timer_cpu_pin,
- gic_irq_dispatch);
- } else {
- timer_cpu_pin = gic_cpu_pin;
- }
}
gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +