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authorMarc Zyngier <maz@kernel.org>2023-04-21 16:05:17 +0300
committerMarc Zyngier <maz@kernel.org>2023-04-21 16:05:17 +0300
commite7b5771aa08746c13bb03ebe0a5053df1498c328 (patch)
tree04360f32dd2cd16196fc3379ad6bdab1ffbb4dd0 /drivers/irqchip
parentf39157b3c0bb4afdcaea7809b3669de8e0495ed5 (diff)
parentf8415f2def181c63486e93c511b82692e0914d9e (diff)
downloadlinux-e7b5771aa08746c13bb03ebe0a5053df1498c328.tar.xz
Merge branch irq/riscv-ipi into irq/irqchip-next
* irq/riscv-ipi: : . : RISC-V IPI rework from Anup Patel: : : "This series aims to improve IPI support in Linux RISC-V in following ways: : 1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V : specific hooks. This also makes Linux RISC-V IPI support aligned with : other architectures. : 2) Remote TLB flushes and icache flushes should prefer local IPIs instead : of SBI calls whenever we have specialized hardware (such as RISC-V AIA : IMSIC and RISC-V SWI) which allows S-mode software to directly inject : IPIs without any assistance from M-mode runtime firmware." : . irqchip/riscv-intc: Add empty irq_eoi() for chained irq handlers RISC-V: Use IPIs for remote icache flush when possible RISC-V: Use IPIs for remote TLB flush when possible RISC-V: Allow marking IPIs as suitable for remote FENCEs RISC-V: Treat IPIs as normal Linux IRQs irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode RISC-V: Clear SIP bit only when using SBI IPI operations Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/Kconfig1
-rw-r--r--drivers/irqchip/irq-riscv-intc.c71
2 files changed, 45 insertions, 27 deletions
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e7bb3554c544..09e422da482f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -537,6 +537,7 @@ config TI_PRUSS_INTC
config RISCV_INTC
bool
depends on RISCV
+ select IRQ_DOMAIN_HIERARCHY
config SIFIVE_PLIC
bool
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 499e5f81b3fe..f229e3e66387 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -26,20 +26,7 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
if (unlikely(cause >= BITS_PER_LONG))
panic("unexpected interrupt cause");
- switch (cause) {
-#ifdef CONFIG_SMP
- case RV_IRQ_SOFT:
- /*
- * We only use software interrupts to pass IPIs, so if a
- * non-SMP system gets one, then we don't know what to do.
- */
- handle_IPI(regs);
- break;
-#endif
- default:
- generic_handle_domain_irq(intc_domain, cause);
- break;
- }
+ generic_handle_domain_irq(intc_domain, cause);
}
/*
@@ -59,22 +46,27 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
csr_set(CSR_IE, BIT(d->hwirq));
}
-static int riscv_intc_cpu_starting(unsigned int cpu)
-{
- csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
- return 0;
-}
-
-static int riscv_intc_cpu_dying(unsigned int cpu)
+static void riscv_intc_irq_eoi(struct irq_data *d)
{
- csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
- return 0;
+ /*
+ * The RISC-V INTC driver uses handle_percpu_devid_irq() flow
+ * for the per-HART local interrupts and child irqchip drivers
+ * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement
+ * chained handlers for the per-HART local interrupts.
+ *
+ * In the absence of irq_eoi(), the chained_irq_enter() and
+ * chained_irq_exit() functions (used by child irqchip drivers)
+ * will do unnecessary mask/unmask of per-HART local interrupts
+ * at the time of handling interrupts. To avoid this, we provide
+ * an empty irq_eoi() callback for RISC-V INTC irqchip.
+ */
}
static struct irq_chip riscv_intc_chip = {
.name = "RISC-V INTC",
.irq_mask = riscv_intc_irq_mask,
.irq_unmask = riscv_intc_irq_unmask,
+ .irq_eoi = riscv_intc_irq_eoi,
};
static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
@@ -87,11 +79,39 @@ static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
return 0;
}
+static int riscv_intc_domain_alloc(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs,
+ void *arg)
+{
+ int i, ret;
+ irq_hw_number_t hwirq;
+ unsigned int type = IRQ_TYPE_NONE;
+ struct irq_fwspec *fwspec = arg;
+
+ ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++) {
+ ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static const struct irq_domain_ops riscv_intc_domain_ops = {
.map = riscv_intc_domain_map,
.xlate = irq_domain_xlate_onecell,
+ .alloc = riscv_intc_domain_alloc
};
+static struct fwnode_handle *riscv_intc_hwnode(void)
+{
+ return intc_domain->fwnode;
+}
+
static int __init riscv_intc_init(struct device_node *node,
struct device_node *parent)
{
@@ -126,10 +146,7 @@ static int __init riscv_intc_init(struct device_node *node,
return rc;
}
- cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
- "irqchip/riscv/intc:starting",
- riscv_intc_cpu_starting,
- riscv_intc_cpu_dying);
+ riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
pr_info("%d local interrupts mapped\n", BITS_PER_LONG);