diff options
author | Maxime Ripard <mripard@kernel.org> | 2023-07-11 10:23:20 +0300 |
---|---|---|
committer | Maxime Ripard <mripard@kernel.org> | 2023-07-11 10:23:20 +0300 |
commit | 2f98e686ef59b5d19af5847d755798e2031bee3a (patch) | |
tree | 7b47919242853d088decf898ca79d6cda0d49381 /drivers/media/platform | |
parent | a2848d08742c8e8494675892c02c0d22acbe3cf8 (diff) | |
parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
download | linux-2f98e686ef59b5d19af5847d755798e2031bee3a.tar.xz |
Merge v6.5-rc1 into drm-misc-fixes
Boris needs 6.5-rc1 in drm-misc-fixes to prevent a conflict.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'drivers/media/platform')
77 files changed, 13037 insertions, 942 deletions
diff --git a/drivers/media/platform/amphion/vdec.c b/drivers/media/platform/amphion/vdec.c index 3fa1a74a2e20..6515f3cdb7a7 100644 --- a/drivers/media/platform/amphion/vdec.c +++ b/drivers/media/platform/amphion/vdec.c @@ -279,6 +279,7 @@ static void vdec_handle_resolution_change(struct vpu_inst *inst) vdec->source_change--; vpu_notify_source_change(inst); + vpu_set_last_buffer_dequeued(inst, false); } static int vdec_update_state(struct vpu_inst *inst, enum vpu_codec_state state, u32 force) @@ -314,7 +315,7 @@ static void vdec_set_last_buffer_dequeued(struct vpu_inst *inst) return; if (vdec->eos_received) { - if (!vpu_set_last_buffer_dequeued(inst)) { + if (!vpu_set_last_buffer_dequeued(inst, true)) { vdec->eos_received--; vdec_update_state(inst, VPU_CODEC_STATE_DRAIN, 0); } @@ -569,7 +570,7 @@ static int vdec_drain(struct vpu_inst *inst) return 0; if (!vdec->params.frame_count) { - vpu_set_last_buffer_dequeued(inst); + vpu_set_last_buffer_dequeued(inst, true); return 0; } @@ -608,7 +609,7 @@ static int vdec_cmd_stop(struct vpu_inst *inst) vpu_trace(inst->dev, "[%d]\n", inst->id); if (inst->state == VPU_CODEC_STATE_DEINIT) { - vpu_set_last_buffer_dequeued(inst); + vpu_set_last_buffer_dequeued(inst, true); } else { vdec->drain = 1; vdec_drain(inst); diff --git a/drivers/media/platform/amphion/venc.c b/drivers/media/platform/amphion/venc.c index e6e8fe45fc7c..58480e2755ec 100644 --- a/drivers/media/platform/amphion/venc.c +++ b/drivers/media/platform/amphion/venc.c @@ -458,7 +458,7 @@ static int venc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd vpu_inst_lock(inst); if (cmd->cmd == V4L2_ENC_CMD_STOP) { if (inst->state == VPU_CODEC_STATE_DEINIT) - vpu_set_last_buffer_dequeued(inst); + vpu_set_last_buffer_dequeued(inst, true); else venc_request_eos(inst); } @@ -878,7 +878,7 @@ static void venc_set_last_buffer_dequeued(struct vpu_inst *inst) struct venc_t *venc = inst->priv; if (venc->stopped && list_empty(&venc->frames)) - vpu_set_last_buffer_dequeued(inst); + vpu_set_last_buffer_dequeued(inst, true); } static void venc_stop_done(struct vpu_inst *inst) diff --git a/drivers/media/platform/amphion/vpu_core.c b/drivers/media/platform/amphion/vpu_core.c index de23627a119a..43d85a54268b 100644 --- a/drivers/media/platform/amphion/vpu_core.c +++ b/drivers/media/platform/amphion/vpu_core.c @@ -254,7 +254,7 @@ static int vpu_core_register(struct device *dev, struct vpu_core *core) if (vpu_core_is_exist(vpu, core)) return 0; - core->workqueue = alloc_workqueue("vpu", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + core->workqueue = alloc_ordered_workqueue("vpu", WQ_MEM_RECLAIM); if (!core->workqueue) { dev_err(core->dev, "fail to alloc workqueue\n"); return -ENOMEM; diff --git a/drivers/media/platform/amphion/vpu_malone.c b/drivers/media/platform/amphion/vpu_malone.c index ef44bff9fbaf..c1d6606ad7e5 100644 --- a/drivers/media/platform/amphion/vpu_malone.c +++ b/drivers/media/platform/amphion/vpu_malone.c @@ -1313,6 +1313,15 @@ static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_i return sizeof(hdr); } +static int vpu_malone_insert_scode_vc1_g_seq(struct malone_scode_t *scode) +{ + if (!scode->inst->total_input_count) + return 0; + if (vpu_vb_is_codecconfig(to_vb2_v4l2_buffer(scode->vb))) + scode->need_data = 0; + return 0; +} + static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode) { struct vb2_v4l2_buffer *vbuf; @@ -1344,6 +1353,8 @@ static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode) int size = 0; u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN]; + if (vpu_vb_is_codecconfig(to_vb2_v4l2_buffer(scode->vb))) + scode->need_data = 0; if (scode->inst->total_input_count) return 0; scode->need_data = 0; @@ -1458,6 +1469,7 @@ static const struct malone_scode_handler scode_handlers[] = { }, { .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G, + .insert_scode_seq = vpu_malone_insert_scode_vc1_g_seq, .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic, }, { diff --git a/drivers/media/platform/amphion/vpu_v4l2.c b/drivers/media/platform/amphion/vpu_v4l2.c index 6773b885597c..021235e1c144 100644 --- a/drivers/media/platform/amphion/vpu_v4l2.c +++ b/drivers/media/platform/amphion/vpu_v4l2.c @@ -100,7 +100,7 @@ int vpu_notify_source_change(struct vpu_inst *inst) return 0; } -int vpu_set_last_buffer_dequeued(struct vpu_inst *inst) +int vpu_set_last_buffer_dequeued(struct vpu_inst *inst, bool eos) { struct vb2_queue *q; @@ -116,7 +116,8 @@ int vpu_set_last_buffer_dequeued(struct vpu_inst *inst) vpu_trace(inst->dev, "last buffer dequeued\n"); q->last_buffer_dequeued = true; wake_up(&q->done_wq); - vpu_notify_eos(inst); + if (eos) + vpu_notify_eos(inst); return 0; } @@ -740,7 +741,7 @@ int vpu_v4l2_open(struct file *file, struct vpu_inst *inst) inst->fh.ctrl_handler = &inst->ctrl_handler; file->private_data = &inst->fh; inst->state = VPU_CODEC_STATE_DEINIT; - inst->workqueue = alloc_workqueue("vpu_inst", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + inst->workqueue = alloc_ordered_workqueue("vpu_inst", WQ_MEM_RECLAIM); if (inst->workqueue) { INIT_WORK(&inst->msg_work, vpu_inst_run_work); ret = kfifo_init(&inst->msg_fifo, diff --git a/drivers/media/platform/amphion/vpu_v4l2.h b/drivers/media/platform/amphion/vpu_v4l2.h index ef5de6b66e47..60f43056a7a2 100644 --- a/drivers/media/platform/amphion/vpu_v4l2.h +++ b/drivers/media/platform/amphion/vpu_v4l2.h @@ -27,7 +27,7 @@ struct vb2_v4l2_buffer *vpu_find_buf_by_idx(struct vpu_inst *inst, u32 type, u32 void vpu_v4l2_set_error(struct vpu_inst *inst); int vpu_notify_eos(struct vpu_inst *inst); int vpu_notify_source_change(struct vpu_inst *inst); -int vpu_set_last_buffer_dequeued(struct vpu_inst *inst); +int vpu_set_last_buffer_dequeued(struct vpu_inst *inst, bool eos); void vpu_vb2_buffers_return(struct vpu_inst *inst, unsigned int type, enum vb2_buffer_state state); int vpu_get_num_buffers(struct vpu_inst *inst, u32 type); bool vpu_is_source_empty(struct vpu_inst *inst); diff --git a/drivers/media/platform/chips-media/coda-common.c b/drivers/media/platform/chips-media/coda-common.c index d013ea5d9d3d..ac9a642ae76f 100644 --- a/drivers/media/platform/chips-media/coda-common.c +++ b/drivers/media/platform/chips-media/coda-common.c @@ -3268,7 +3268,7 @@ static int coda_probe(struct platform_device *pdev) &dev->iram.blob); } - dev->workqueue = alloc_workqueue("coda", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + dev->workqueue = alloc_ordered_workqueue("coda", WQ_MEM_RECLAIM); if (!dev->workqueue) { dev_err(&pdev->dev, "unable to alloc workqueue\n"); ret = -ENOMEM; diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index 0051f372a66c..4768156181c9 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -28,6 +28,7 @@ #include "mtk_jpeg_core.h" #include "mtk_jpeg_dec_parse.h" +#if defined(CONFIG_OF) static struct mtk_jpeg_fmt mtk_jpeg_enc_formats[] = { { .fourcc = V4L2_PIX_FMT_JPEG, @@ -101,6 +102,7 @@ static struct mtk_jpeg_fmt mtk_jpeg_dec_formats[] = { .flags = MTK_JPEG_FMT_FLAG_CAPTURE, }, }; +#endif #define MTK_JPEG_ENC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_enc_formats) #define MTK_JPEG_DEC_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_dec_formats) @@ -936,148 +938,6 @@ static int mtk_jpeg_set_dec_dst(struct mtk_jpeg_ctx *ctx, return 0; } -static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx) -{ - struct mtk_jpegenc_comp_dev *comp_jpeg; - struct mtk_jpeg_dev *jpeg = ctx->jpeg; - unsigned long flags; - int hw_id = -1; - int i; - - spin_lock_irqsave(&jpeg->hw_lock, flags); - for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) { - comp_jpeg = jpeg->enc_hw_dev[i]; - if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) { - hw_id = i; - comp_jpeg->hw_state = MTK_JPEG_HW_BUSY; - break; - } - } - spin_unlock_irqrestore(&jpeg->hw_lock, flags); - - return hw_id; -} - -static int mtk_jpegenc_set_hw_param(struct mtk_jpeg_ctx *ctx, - int hw_id, - struct vb2_v4l2_buffer *src_buf, - struct vb2_v4l2_buffer *dst_buf) -{ - struct mtk_jpegenc_comp_dev *jpeg = ctx->jpeg->enc_hw_dev[hw_id]; - - jpeg->hw_param.curr_ctx = ctx; - jpeg->hw_param.src_buffer = src_buf; - jpeg->hw_param.dst_buffer = dst_buf; - - return 0; -} - -static int mtk_jpegenc_put_hw(struct mtk_jpeg_dev *jpeg, int hw_id) -{ - unsigned long flags; - - spin_lock_irqsave(&jpeg->hw_lock, flags); - jpeg->enc_hw_dev[hw_id]->hw_state = MTK_JPEG_HW_IDLE; - spin_unlock_irqrestore(&jpeg->hw_lock, flags); - - return 0; -} - -static void mtk_jpegenc_worker(struct work_struct *work) -{ - struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX]; - enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; - struct mtk_jpeg_src_buf *jpeg_dst_buf; - struct vb2_v4l2_buffer *src_buf, *dst_buf; - int ret, i, hw_id = 0; - unsigned long flags; - - struct mtk_jpeg_ctx *ctx = container_of(work, - struct mtk_jpeg_ctx, - jpeg_work); - struct mtk_jpeg_dev *jpeg = ctx->jpeg; - - for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) - comp_jpeg[i] = jpeg->enc_hw_dev[i]; - i = 0; - -retry_select: - hw_id = mtk_jpegenc_get_hw(ctx); - if (hw_id < 0) { - ret = wait_event_interruptible(jpeg->hw_wq, - atomic_read(&jpeg->hw_rdy) > 0); - if (ret != 0 || (i++ > MTK_JPEG_MAX_RETRY_TIME)) { - dev_err(jpeg->dev, "%s : %d, all HW are busy\n", - __func__, __LINE__); - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); - return; - } - - goto retry_select; - } - - atomic_dec(&jpeg->hw_rdy); - src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); - if (!src_buf) - goto getbuf_fail; - - dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); - if (!dst_buf) - goto getbuf_fail; - - v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); - - mtk_jpegenc_set_hw_param(ctx, hw_id, src_buf, dst_buf); - ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev); - if (ret < 0) { - dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n", - __func__, __LINE__); - goto enc_end; - } - - ret = clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk); - if (ret) { - dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n", - __func__, __LINE__); - goto enc_end; - } - - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - - schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, - msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC)); - - spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags); - jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf); - jpeg_dst_buf->curr_ctx = ctx; - jpeg_dst_buf->frame_num = ctx->total_frame_num; - ctx->total_frame_num++; - mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base); - mtk_jpeg_set_enc_dst(ctx, - comp_jpeg[hw_id]->reg_base, - &dst_buf->vb2_buf); - mtk_jpeg_set_enc_src(ctx, - comp_jpeg[hw_id]->reg_base, - &src_buf->vb2_buf); - mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base); - mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base); - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); - spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags); - - return; - -enc_end: - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_buf_done(src_buf, buf_state); - v4l2_m2m_buf_done(dst_buf, buf_state); -getbuf_fail: - atomic_inc(&jpeg->hw_rdy); - mtk_jpegenc_put_hw(jpeg, hw_id); - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); -} - static void mtk_jpeg_enc_device_run(void *priv) { struct mtk_jpeg_ctx *ctx = priv; @@ -1128,173 +988,6 @@ static void mtk_jpeg_multicore_enc_device_run(void *priv) queue_work(jpeg->workqueue, &ctx->jpeg_work); } -static int mtk_jpegdec_get_hw(struct mtk_jpeg_ctx *ctx) -{ - struct mtk_jpegdec_comp_dev *comp_jpeg; - struct mtk_jpeg_dev *jpeg = ctx->jpeg; - unsigned long flags; - int hw_id = -1; - int i; - - spin_lock_irqsave(&jpeg->hw_lock, flags); - for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) { - comp_jpeg = jpeg->dec_hw_dev[i]; - if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) { - hw_id = i; - comp_jpeg->hw_state = MTK_JPEG_HW_BUSY; - break; - } - } - spin_unlock_irqrestore(&jpeg->hw_lock, flags); - - return hw_id; -} - -static int mtk_jpegdec_put_hw(struct mtk_jpeg_dev *jpeg, int hw_id) -{ - unsigned long flags; - - spin_lock_irqsave(&jpeg->hw_lock, flags); - jpeg->dec_hw_dev[hw_id]->hw_state = - MTK_JPEG_HW_IDLE; - spin_unlock_irqrestore(&jpeg->hw_lock, flags); - - return 0; -} - -static int mtk_jpegdec_set_hw_param(struct mtk_jpeg_ctx *ctx, - int hw_id, - struct vb2_v4l2_buffer *src_buf, - struct vb2_v4l2_buffer *dst_buf) -{ - struct mtk_jpegdec_comp_dev *jpeg = - ctx->jpeg->dec_hw_dev[hw_id]; - - jpeg->hw_param.curr_ctx = ctx; - jpeg->hw_param.src_buffer = src_buf; - jpeg->hw_param.dst_buffer = dst_buf; - - return 0; -} - -static void mtk_jpegdec_worker(struct work_struct *work) -{ - struct mtk_jpeg_ctx *ctx = container_of(work, struct mtk_jpeg_ctx, - jpeg_work); - struct mtk_jpegdec_comp_dev *comp_jpeg[MTK_JPEGDEC_HW_MAX]; - enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; - struct mtk_jpeg_src_buf *jpeg_src_buf, *jpeg_dst_buf; - struct vb2_v4l2_buffer *src_buf, *dst_buf; - struct mtk_jpeg_dev *jpeg = ctx->jpeg; - int ret, i, hw_id = 0; - struct mtk_jpeg_bs bs; - struct mtk_jpeg_fb fb; - unsigned long flags; - - for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) - comp_jpeg[i] = jpeg->dec_hw_dev[i]; - i = 0; - -retry_select: - hw_id = mtk_jpegdec_get_hw(ctx); - if (hw_id < 0) { - ret = wait_event_interruptible_timeout(jpeg->hw_wq, - atomic_read(&jpeg->hw_rdy) > 0, - MTK_JPEG_HW_TIMEOUT_MSEC); - if (ret != 0 || (i++ > MTK_JPEG_MAX_RETRY_TIME)) { - dev_err(jpeg->dev, "%s : %d, all HW are busy\n", - __func__, __LINE__); - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); - return; - } - - goto retry_select; - } - - atomic_dec(&jpeg->hw_rdy); - src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); - if (!src_buf) - goto getbuf_fail; - - dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); - if (!dst_buf) - goto getbuf_fail; - - v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); - jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf); - jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf); - - if (mtk_jpeg_check_resolution_change(ctx, - &jpeg_src_buf->dec_param)) { - mtk_jpeg_queue_src_chg_event(ctx); - ctx->state = MTK_JPEG_SOURCE_CHANGE; - goto getbuf_fail; - } - - jpeg_src_buf->curr_ctx = ctx; - jpeg_src_buf->frame_num = ctx->total_frame_num; - jpeg_dst_buf->curr_ctx = ctx; - jpeg_dst_buf->frame_num = ctx->total_frame_num; - - mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf); - ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev); - if (ret < 0) { - dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n", - __func__, __LINE__); - goto dec_end; - } - - ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk); - if (ret) { - dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n", - __func__, __LINE__); - goto clk_end; - } - - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - - schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, - msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC)); - - mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs); - if (mtk_jpeg_set_dec_dst(ctx, - &jpeg_src_buf->dec_param, - &dst_buf->vb2_buf, &fb)) { - dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n", - __func__, __LINE__); - goto setdst_end; - } - - spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags); - ctx->total_frame_num++; - mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base); - mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base, - &jpeg_src_buf->dec_param, - jpeg_src_buf->bs_size, - &bs, - &fb); - mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base); - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); - spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags); - - return; - -setdst_end: - clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk); -clk_end: - pm_runtime_put(comp_jpeg[hw_id]->dev); -dec_end: - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_buf_done(src_buf, buf_state); - v4l2_m2m_buf_done(dst_buf, buf_state); -getbuf_fail: - atomic_inc(&jpeg->hw_rdy); - mtk_jpegdec_put_hw(jpeg, hw_id); - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); -} - static void mtk_jpeg_multicore_dec_device_run(void *priv) { struct mtk_jpeg_ctx *ctx = priv; @@ -1430,101 +1123,6 @@ static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg) jpeg->variant->clks); } -static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg) -{ - struct mtk_jpeg_ctx *ctx; - struct vb2_v4l2_buffer *src_buf, *dst_buf; - enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; - u32 result_size; - - ctx = v4l2_m2m_get_curr_priv(jpeg->m2m_dev); - if (!ctx) { - v4l2_err(&jpeg->v4l2_dev, "Context is NULL\n"); - return IRQ_HANDLED; - } - - src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - - result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base); - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size); - - buf_state = VB2_BUF_STATE_DONE; - - v4l2_m2m_buf_done(src_buf, buf_state); - v4l2_m2m_buf_done(dst_buf, buf_state); - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); - pm_runtime_put(ctx->jpeg->dev); - return IRQ_HANDLED; -} - -static irqreturn_t mtk_jpeg_enc_irq(int irq, void *priv) -{ - struct mtk_jpeg_dev *jpeg = priv; - u32 irq_status; - irqreturn_t ret = IRQ_NONE; - - cancel_delayed_work(&jpeg->job_timeout_work); - - irq_status = readl(jpeg->reg_base + JPEG_ENC_INT_STS) & - JPEG_ENC_INT_STATUS_MASK_ALLIRQ; - if (irq_status) - writel(0, jpeg->reg_base + JPEG_ENC_INT_STS); - - if (!(irq_status & JPEG_ENC_INT_STATUS_DONE)) - return ret; - - ret = mtk_jpeg_enc_done(jpeg); - return ret; -} - -static irqreturn_t mtk_jpeg_dec_irq(int irq, void *priv) -{ - struct mtk_jpeg_dev *jpeg = priv; - struct mtk_jpeg_ctx *ctx; - struct vb2_v4l2_buffer *src_buf, *dst_buf; - struct mtk_jpeg_src_buf *jpeg_src_buf; - enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; - u32 dec_irq_ret; - u32 dec_ret; - int i; - - cancel_delayed_work(&jpeg->job_timeout_work); - - dec_ret = mtk_jpeg_dec_get_int_status(jpeg->reg_base); - dec_irq_ret = mtk_jpeg_dec_enum_result(dec_ret); - ctx = v4l2_m2m_get_curr_priv(jpeg->m2m_dev); - if (!ctx) { - v4l2_err(&jpeg->v4l2_dev, "Context is NULL\n"); - return IRQ_HANDLED; - } - - src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf); - - if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW) - mtk_jpeg_dec_reset(jpeg->reg_base); - - if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE) { - dev_err(jpeg->dev, "decode failed\n"); - goto dec_end; - } - - for (i = 0; i < dst_buf->vb2_buf.num_planes; i++) - vb2_set_plane_payload(&dst_buf->vb2_buf, i, - jpeg_src_buf->dec_param.comp_size[i]); - - buf_state = VB2_BUF_STATE_DONE; - -dec_end: - v4l2_m2m_buf_done(src_buf, buf_state); - v4l2_m2m_buf_done(dst_buf, buf_state); - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); - pm_runtime_put(ctx->jpeg->dev); - return IRQ_HANDLED; -} - static void mtk_jpeg_set_default_params(struct mtk_jpeg_ctx *ctx) { struct mtk_jpeg_q_data *q = &ctx->out_q; @@ -1637,15 +1235,6 @@ static const struct v4l2_file_operations mtk_jpeg_fops = { .mmap = v4l2_m2m_fop_mmap, }; -static struct clk_bulk_data mt8173_jpeg_dec_clocks[] = { - { .id = "jpgdec-smi" }, - { .id = "jpgdec" }, -}; - -static struct clk_bulk_data mtk_jpeg_clocks[] = { - { .id = "jpgenc" }, -}; - static void mtk_jpeg_job_timeout_work(struct work_struct *work) { struct mtk_jpeg_dev *jpeg = container_of(work, struct mtk_jpeg_dev, @@ -1867,6 +1456,419 @@ static const struct dev_pm_ops mtk_jpeg_pm_ops = { }; #if defined(CONFIG_OF) +static int mtk_jpegenc_get_hw(struct mtk_jpeg_ctx *ctx) +{ + struct mtk_jpegenc_comp_dev *comp_jpeg; + struct mtk_jpeg_dev *jpeg = ctx->jpeg; + unsigned long flags; + int hw_id = -1; + int i; + + spin_lock_irqsave(&jpeg->hw_lock, flags); + for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) { + comp_jpeg = jpeg->enc_hw_dev[i]; + if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) { + hw_id = i; + comp_jpeg->hw_state = MTK_JPEG_HW_BUSY; + break; + } + } + spin_unlock_irqrestore(&jpeg->hw_lock, flags); + + return hw_id; +} + +static int mtk_jpegenc_set_hw_param(struct mtk_jpeg_ctx *ctx, + int hw_id, + struct vb2_v4l2_buffer *src_buf, + struct vb2_v4l2_buffer *dst_buf) +{ + struct mtk_jpegenc_comp_dev *jpeg = ctx->jpeg->enc_hw_dev[hw_id]; + + jpeg->hw_param.curr_ctx = ctx; + jpeg->hw_param.src_buffer = src_buf; + jpeg->hw_param.dst_buffer = dst_buf; + + return 0; +} + +static int mtk_jpegenc_put_hw(struct mtk_jpeg_dev *jpeg, int hw_id) +{ + unsigned long flags; + + spin_lock_irqsave(&jpeg->hw_lock, flags); + jpeg->enc_hw_dev[hw_id]->hw_state = MTK_JPEG_HW_IDLE; + spin_unlock_irqrestore(&jpeg->hw_lock, flags); + + return 0; +} + +static int mtk_jpegdec_get_hw(struct mtk_jpeg_ctx *ctx) +{ + struct mtk_jpegdec_comp_dev *comp_jpeg; + struct mtk_jpeg_dev *jpeg = ctx->jpeg; + unsigned long flags; + int hw_id = -1; + int i; + + spin_lock_irqsave(&jpeg->hw_lock, flags); + for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) { + comp_jpeg = jpeg->dec_hw_dev[i]; + if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) { + hw_id = i; + comp_jpeg->hw_state = MTK_JPEG_HW_BUSY; + break; + } + } + spin_unlock_irqrestore(&jpeg->hw_lock, flags); + + return hw_id; +} + +static int mtk_jpegdec_put_hw(struct mtk_jpeg_dev *jpeg, int hw_id) +{ + unsigned long flags; + + spin_lock_irqsave(&jpeg->hw_lock, flags); + jpeg->dec_hw_dev[hw_id]->hw_state = + MTK_JPEG_HW_IDLE; + spin_unlock_irqrestore(&jpeg->hw_lock, flags); + + return 0; +} + +static int mtk_jpegdec_set_hw_param(struct mtk_jpeg_ctx *ctx, + int hw_id, + struct vb2_v4l2_buffer *src_buf, + struct vb2_v4l2_buffer *dst_buf) +{ + struct mtk_jpegdec_comp_dev *jpeg = + ctx->jpeg->dec_hw_dev[hw_id]; + + jpeg->hw_param.curr_ctx = ctx; + jpeg->hw_param.src_buffer = src_buf; + jpeg->hw_param.dst_buffer = dst_buf; + + return 0; +} + +static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg) +{ + struct mtk_jpeg_ctx *ctx; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; + u32 result_size; + + ctx = v4l2_m2m_get_curr_priv(jpeg->m2m_dev); + if (!ctx) { + v4l2_err(&jpeg->v4l2_dev, "Context is NULL\n"); + return IRQ_HANDLED; + } + + src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + + result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base); + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size); + + buf_state = VB2_BUF_STATE_DONE; + + v4l2_m2m_buf_done(src_buf, buf_state); + v4l2_m2m_buf_done(dst_buf, buf_state); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + pm_runtime_put(ctx->jpeg->dev); + return IRQ_HANDLED; +} + +static void mtk_jpegenc_worker(struct work_struct *work) +{ + struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX]; + enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; + struct mtk_jpeg_src_buf *jpeg_dst_buf; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + int ret, i, hw_id = 0; + unsigned long flags; + + struct mtk_jpeg_ctx *ctx = container_of(work, + struct mtk_jpeg_ctx, + jpeg_work); + struct mtk_jpeg_dev *jpeg = ctx->jpeg; + + for (i = 0; i < MTK_JPEGENC_HW_MAX; i++) + comp_jpeg[i] = jpeg->enc_hw_dev[i]; + i = 0; + +retry_select: + hw_id = mtk_jpegenc_get_hw(ctx); + if (hw_id < 0) { + ret = wait_event_interruptible(jpeg->hw_wq, + atomic_read(&jpeg->hw_rdy) > 0); + if (ret != 0 || (i++ > MTK_JPEG_MAX_RETRY_TIME)) { + dev_err(jpeg->dev, "%s : %d, all HW are busy\n", + __func__, __LINE__); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + return; + } + + goto retry_select; + } + + atomic_dec(&jpeg->hw_rdy); + src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + if (!src_buf) + goto getbuf_fail; + + dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + if (!dst_buf) + goto getbuf_fail; + + v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); + + mtk_jpegenc_set_hw_param(ctx, hw_id, src_buf, dst_buf); + ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev); + if (ret < 0) { + dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n", + __func__, __LINE__); + goto enc_end; + } + + ret = clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk); + if (ret) { + dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n", + __func__, __LINE__); + goto enc_end; + } + + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + + schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, + msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC)); + + spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags); + jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf); + jpeg_dst_buf->curr_ctx = ctx; + jpeg_dst_buf->frame_num = ctx->total_frame_num; + ctx->total_frame_num++; + mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base); + mtk_jpeg_set_enc_dst(ctx, + comp_jpeg[hw_id]->reg_base, + &dst_buf->vb2_buf); + mtk_jpeg_set_enc_src(ctx, + comp_jpeg[hw_id]->reg_base, + &src_buf->vb2_buf); + mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base); + mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags); + + return; + +enc_end: + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_buf_done(src_buf, buf_state); + v4l2_m2m_buf_done(dst_buf, buf_state); +getbuf_fail: + atomic_inc(&jpeg->hw_rdy); + mtk_jpegenc_put_hw(jpeg, hw_id); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); +} + +static void mtk_jpegdec_worker(struct work_struct *work) +{ + struct mtk_jpeg_ctx *ctx = container_of(work, struct mtk_jpeg_ctx, + jpeg_work); + struct mtk_jpegdec_comp_dev *comp_jpeg[MTK_JPEGDEC_HW_MAX]; + enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; + struct mtk_jpeg_src_buf *jpeg_src_buf, *jpeg_dst_buf; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + struct mtk_jpeg_dev *jpeg = ctx->jpeg; + int ret, i, hw_id = 0; + struct mtk_jpeg_bs bs; + struct mtk_jpeg_fb fb; + unsigned long flags; + + for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) + comp_jpeg[i] = jpeg->dec_hw_dev[i]; + i = 0; + +retry_select: + hw_id = mtk_jpegdec_get_hw(ctx); + if (hw_id < 0) { + ret = wait_event_interruptible_timeout(jpeg->hw_wq, + atomic_read(&jpeg->hw_rdy) > 0, + MTK_JPEG_HW_TIMEOUT_MSEC); + if (ret != 0 || (i++ > MTK_JPEG_MAX_RETRY_TIME)) { + dev_err(jpeg->dev, "%s : %d, all HW are busy\n", + __func__, __LINE__); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + return; + } + + goto retry_select; + } + + atomic_dec(&jpeg->hw_rdy); + src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + if (!src_buf) + goto getbuf_fail; + + dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + if (!dst_buf) + goto getbuf_fail; + + v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); + jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf); + jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf); + + if (mtk_jpeg_check_resolution_change(ctx, + &jpeg_src_buf->dec_param)) { + mtk_jpeg_queue_src_chg_event(ctx); + ctx->state = MTK_JPEG_SOURCE_CHANGE; + goto getbuf_fail; + } + + jpeg_src_buf->curr_ctx = ctx; + jpeg_src_buf->frame_num = ctx->total_frame_num; + jpeg_dst_buf->curr_ctx = ctx; + jpeg_dst_buf->frame_num = ctx->total_frame_num; + + mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf); + ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev); + if (ret < 0) { + dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n", + __func__, __LINE__); + goto dec_end; + } + + ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk); + if (ret) { + dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n", + __func__, __LINE__); + goto clk_end; + } + + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + + schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, + msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC)); + + mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs); + if (mtk_jpeg_set_dec_dst(ctx, + &jpeg_src_buf->dec_param, + &dst_buf->vb2_buf, &fb)) { + dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n", + __func__, __LINE__); + goto setdst_end; + } + + spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags); + ctx->total_frame_num++; + mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base); + mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base, + &jpeg_src_buf->dec_param, + jpeg_src_buf->bs_size, + &bs, + &fb); + mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags); + + return; + +setdst_end: + clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk); +clk_end: + pm_runtime_put(comp_jpeg[hw_id]->dev); +dec_end: + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_buf_done(src_buf, buf_state); + v4l2_m2m_buf_done(dst_buf, buf_state); +getbuf_fail: + atomic_inc(&jpeg->hw_rdy); + mtk_jpegdec_put_hw(jpeg, hw_id); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); +} + +static irqreturn_t mtk_jpeg_enc_irq(int irq, void *priv) +{ + struct mtk_jpeg_dev *jpeg = priv; + u32 irq_status; + irqreturn_t ret = IRQ_NONE; + + cancel_delayed_work(&jpeg->job_timeout_work); + + irq_status = readl(jpeg->reg_base + JPEG_ENC_INT_STS) & + JPEG_ENC_INT_STATUS_MASK_ALLIRQ; + if (irq_status) + writel(0, jpeg->reg_base + JPEG_ENC_INT_STS); + + if (!(irq_status & JPEG_ENC_INT_STATUS_DONE)) + return ret; + + ret = mtk_jpeg_enc_done(jpeg); + return ret; +} + +static irqreturn_t mtk_jpeg_dec_irq(int irq, void *priv) +{ + struct mtk_jpeg_dev *jpeg = priv; + struct mtk_jpeg_ctx *ctx; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + struct mtk_jpeg_src_buf *jpeg_src_buf; + enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; + u32 dec_irq_ret; + u32 dec_ret; + int i; + + cancel_delayed_work(&jpeg->job_timeout_work); + + dec_ret = mtk_jpeg_dec_get_int_status(jpeg->reg_base); + dec_irq_ret = mtk_jpeg_dec_enum_result(dec_ret); + ctx = v4l2_m2m_get_curr_priv(jpeg->m2m_dev); + if (!ctx) { + v4l2_err(&jpeg->v4l2_dev, "Context is NULL\n"); + return IRQ_HANDLED; + } + + src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf); + + if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW) + mtk_jpeg_dec_reset(jpeg->reg_base); + + if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE) { + dev_err(jpeg->dev, "decode failed\n"); + goto dec_end; + } + + for (i = 0; i < dst_buf->vb2_buf.num_planes; i++) + vb2_set_plane_payload(&dst_buf->vb2_buf, i, + jpeg_src_buf->dec_param.comp_size[i]); + + buf_state = VB2_BUF_STATE_DONE; + +dec_end: + v4l2_m2m_buf_done(src_buf, buf_state); + v4l2_m2m_buf_done(dst_buf, buf_state); + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); + pm_runtime_put(ctx->jpeg->dev); + return IRQ_HANDLED; +} + +static struct clk_bulk_data mtk_jpeg_clocks[] = { + { .id = "jpgenc" }, +}; + +static struct clk_bulk_data mt8173_jpeg_dec_clocks[] = { + { .id = "jpgdec-smi" }, + { .id = "jpgdec" }, +}; + static const struct mtk_jpeg_variant mt8173_jpeg_drvdata = { .clks = mt8173_jpeg_dec_clocks, .num_clks = ARRAY_SIZE(mt8173_jpeg_dec_clocks), diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_parse.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_parse.c index b95c45791c29..bb9cdc9e0e90 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_parse.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_parse.c @@ -7,15 +7,10 @@ #include <linux/kernel.h> #include <linux/videodev2.h> +#include <media/jpeg.h> #include "mtk_jpeg_dec_parse.h" -#define TEM 0x01 -#define SOF0 0xc0 -#define RST 0xd0 -#define SOI 0xd8 -#define EOI 0xd9 - struct mtk_jpeg_stream { u8 *addr; u32 size; @@ -83,7 +78,7 @@ static bool mtk_jpeg_do_parse(struct mtk_jpeg_dec_param *param, u8 *src_addr_va, length = 0; switch (byte) { - case SOF0: + case JPEG_MARKER_SOF0: /* length */ if (read_word_be(&stream, &word)) break; @@ -123,10 +118,10 @@ static bool mtk_jpeg_do_parse(struct mtk_jpeg_dec_param *param, u8 *src_addr_va, notfound = !(i == param->comp_num); break; - case RST ... RST + 7: - case SOI: - case EOI: - case TEM: + case JPEG_MARKER_RST ... JPEG_MARKER_RST + 7: + case JPEG_MARKER_SOI: + case JPEG_MARKER_EOI: + case JPEG_MARKER_TEM: break; default: if (read_word_be(&stream, &word)) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 19a4a085f73a..a605e80c7dc3 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -1035,6 +1035,7 @@ static int mdp_comp_sub_create(struct mdp_dev *mdp) { struct device *dev = &mdp->pdev->dev; struct device_node *node, *parent; + int ret = 0; parent = dev->of_node->parent; @@ -1060,16 +1061,22 @@ static int mdp_comp_sub_create(struct mdp_dev *mdp) dev_err(dev, "Fail to get sub comp. id: type %d alias %d\n", type, alias_id); - return -EINVAL; + ret = -EINVAL; + goto err_free_node; } mdp_comp_alias_id[type]++; comp = mdp_comp_create(mdp, node, id); - if (IS_ERR(comp)) - return PTR_ERR(comp); + if (IS_ERR(comp)) { + ret = PTR_ERR(comp); + goto err_free_node; + } } + return ret; - return 0; +err_free_node: + of_node_put(node); + return ret; } void mdp_comp_destroy(struct mdp_dev *mdp) diff --git a/drivers/media/platform/mediatek/vcodec/Makefile b/drivers/media/platform/mediatek/vcodec/Makefile index 93e7a343b5b0..5f4c30fec85a 100644 --- a/drivers/media/platform/mediatek/vcodec/Makefile +++ b/drivers/media/platform/mediatek/vcodec/Makefile @@ -10,9 +10,11 @@ mtk-vcodec-dec-y := vdec/vdec_h264_if.o \ vdec/vdec_vp8_req_if.o \ vdec/vdec_vp9_if.o \ vdec/vdec_vp9_req_lat_if.o \ + vdec/vdec_av1_req_lat_if.o \ vdec/vdec_h264_req_if.o \ vdec/vdec_h264_req_common.o \ vdec/vdec_h264_req_multi_if.o \ + vdec/vdec_hevc_req_multi_if.o \ mtk_vcodec_dec_drv.o \ vdec_drv_if.o \ vdec_vpu_if.o \ @@ -44,3 +46,9 @@ endif ifneq ($(CONFIG_VIDEO_MEDIATEK_VCODEC_SCP),) mtk-vcodec-common-y += mtk_vcodec_fw_scp.o endif + +ifneq ($(CONFIG_DEBUG_FS),) +obj-$(CONFIG_VIDEO_MEDIATEK_VCODEC) += mtk-vcodec-dbgfs.o + +mtk-vcodec-dbgfs-y := mtk_vcodec_dbgfs.o +endif
\ No newline at end of file diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dbgfs.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dbgfs.c new file mode 100644 index 000000000000..b5cdbbfcc388 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dbgfs.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Yunfei Dong <yunfei.dong@mediatek.com> + */ + +#include <linux/debugfs.h> + +#include "mtk_vcodec_dbgfs.h" +#include "mtk_vcodec_drv.h" +#include "mtk_vcodec_util.h" + +static void mtk_vdec_dbgfs_get_format_type(struct mtk_vcodec_ctx *ctx, char *buf, + int *used, int total) +{ + int curr_len; + + switch (ctx->current_codec) { + case V4L2_PIX_FMT_H264_SLICE: + curr_len = snprintf(buf + *used, total - *used, + "\toutput format: h264 slice\n"); + break; + case V4L2_PIX_FMT_VP8_FRAME: + curr_len = snprintf(buf + *used, total - *used, + "\toutput format: vp8 slice\n"); + break; + case V4L2_PIX_FMT_VP9_FRAME: + curr_len = snprintf(buf + *used, total - *used, + "\toutput format: vp9 slice\n"); + break; + default: + curr_len = snprintf(buf + *used, total - *used, + "\tunsupported output format: 0x%x\n", + ctx->current_codec); + } + *used += curr_len; + + switch (ctx->capture_fourcc) { + case V4L2_PIX_FMT_MM21: + curr_len = snprintf(buf + *used, total - *used, + "\tcapture format: MM21\n"); + break; + case V4L2_PIX_FMT_MT21C: + curr_len = snprintf(buf + *used, total - *used, + "\tcapture format: MT21C\n"); + break; + default: + curr_len = snprintf(buf + *used, total - *used, + "\tunsupported capture format: 0x%x\n", + ctx->capture_fourcc); + } + *used += curr_len; +} + +static void mtk_vdec_dbgfs_get_help(char *buf, int *used, int total) +{ + int curr_len; + + curr_len = snprintf(buf + *used, total - *used, + "help: (1: echo -'info' > vdec 2: cat vdec)\n"); + *used += curr_len; + + curr_len = snprintf(buf + *used, total - *used, + "\t-picinfo: get resolution\n"); + *used += curr_len; + + curr_len = snprintf(buf + *used, total - *used, + "\t-format: get output & capture queue format\n"); + *used += curr_len; +} + +static ssize_t mtk_vdec_dbgfs_write(struct file *filp, const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct mtk_vcodec_dev *vcodec_dev = filp->private_data; + struct mtk_vcodec_dbgfs *dbgfs = &vcodec_dev->dbgfs; + + mutex_lock(&dbgfs->dbgfs_lock); + dbgfs->buf_size = simple_write_to_buffer(dbgfs->dbgfs_buf, sizeof(dbgfs->dbgfs_buf), + ppos, ubuf, count); + mutex_unlock(&dbgfs->dbgfs_lock); + if (dbgfs->buf_size > 0) + return count; + + return dbgfs->buf_size; +} + +static ssize_t mtk_vdec_dbgfs_read(struct file *filp, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct mtk_vcodec_dev *vcodec_dev = filp->private_data; + struct mtk_vcodec_dbgfs *dbgfs = &vcodec_dev->dbgfs; + struct mtk_vcodec_dbgfs_inst *dbgfs_inst; + struct mtk_vcodec_ctx *ctx; + int total_len = 200 * (dbgfs->inst_count == 0 ? 1 : dbgfs->inst_count); + int used_len = 0, curr_len, ret; + bool dbgfs_index[MTK_VDEC_DBGFS_MAX] = {0}; + char *buf = kmalloc(total_len, GFP_KERNEL); + + if (!buf) + return -ENOMEM; + + if (strstr(dbgfs->dbgfs_buf, "-help") || dbgfs->buf_size == 1) { + mtk_vdec_dbgfs_get_help(buf, &used_len, total_len); + goto read_buffer; + } + + if (strstr(dbgfs->dbgfs_buf, "-picinfo")) + dbgfs_index[MTK_VDEC_DBGFS_PICINFO] = true; + + if (strstr(dbgfs->dbgfs_buf, "-format")) + dbgfs_index[MTK_VDEC_DBGFS_FORMAT] = true; + + mutex_lock(&dbgfs->dbgfs_lock); + list_for_each_entry(dbgfs_inst, &dbgfs->dbgfs_head, node) { + ctx = dbgfs_inst->vcodec_ctx; + + curr_len = snprintf(buf + used_len, total_len - used_len, + "inst[%d]:\n ", ctx->id); + used_len += curr_len; + + if (dbgfs_index[MTK_VDEC_DBGFS_PICINFO]) { + curr_len = snprintf(buf + used_len, total_len - used_len, + "\treal(%dx%d)=>align(%dx%d)\n", + ctx->picinfo.pic_w, ctx->picinfo.pic_h, + ctx->picinfo.buf_w, ctx->picinfo.buf_h); + used_len += curr_len; + } + + if (dbgfs_index[MTK_VDEC_DBGFS_FORMAT]) + mtk_vdec_dbgfs_get_format_type(ctx, buf, &used_len, total_len); + } + mutex_unlock(&dbgfs->dbgfs_lock); +read_buffer: + ret = simple_read_from_buffer(ubuf, count, ppos, buf, used_len); + kfree(buf); + return ret; +} + +static const struct file_operations vdec_fops = { + .open = simple_open, + .write = mtk_vdec_dbgfs_write, + .read = mtk_vdec_dbgfs_read, +}; + +void mtk_vcodec_dbgfs_create(struct mtk_vcodec_ctx *ctx) +{ + struct mtk_vcodec_dbgfs_inst *dbgfs_inst; + struct mtk_vcodec_dev *vcodec_dev = ctx->dev; + + dbgfs_inst = kzalloc(sizeof(*dbgfs_inst), GFP_KERNEL); + if (!dbgfs_inst) + return; + + list_add_tail(&dbgfs_inst->node, &vcodec_dev->dbgfs.dbgfs_head); + + vcodec_dev->dbgfs.inst_count++; + + dbgfs_inst->inst_id = ctx->id; + dbgfs_inst->vcodec_ctx = ctx; +} +EXPORT_SYMBOL_GPL(mtk_vcodec_dbgfs_create); + +void mtk_vcodec_dbgfs_remove(struct mtk_vcodec_dev *vcodec_dev, int ctx_id) +{ + struct mtk_vcodec_dbgfs_inst *dbgfs_inst; + + list_for_each_entry(dbgfs_inst, &vcodec_dev->dbgfs.dbgfs_head, node) { + if (dbgfs_inst->inst_id == ctx_id) { + vcodec_dev->dbgfs.inst_count--; + break; + } + } + + if (dbgfs_inst) { + list_del(&dbgfs_inst->node); + kfree(dbgfs_inst); + } +} +EXPORT_SYMBOL_GPL(mtk_vcodec_dbgfs_remove); + +void mtk_vcodec_dbgfs_init(struct mtk_vcodec_dev *vcodec_dev, bool is_encode) +{ + struct dentry *vcodec_root; + + if (is_encode) + vcodec_dev->dbgfs.vcodec_root = debugfs_create_dir("vcodec-enc", NULL); + else + vcodec_dev->dbgfs.vcodec_root = debugfs_create_dir("vcodec-dec", NULL); + if (IS_ERR(vcodec_dev->dbgfs.vcodec_root)) + dev_err(&vcodec_dev->plat_dev->dev, "create vcodec dir err:%d\n", + IS_ERR(vcodec_dev->dbgfs.vcodec_root)); + + vcodec_root = vcodec_dev->dbgfs.vcodec_root; + debugfs_create_x32("mtk_v4l2_dbg_level", 0644, vcodec_root, &mtk_v4l2_dbg_level); + debugfs_create_x32("mtk_vcodec_dbg", 0644, vcodec_root, &mtk_vcodec_dbg); + + vcodec_dev->dbgfs.inst_count = 0; + if (is_encode) + return; + + INIT_LIST_HEAD(&vcodec_dev->dbgfs.dbgfs_head); + debugfs_create_file("vdec", 0200, vcodec_root, vcodec_dev, &vdec_fops); + mutex_init(&vcodec_dev->dbgfs.dbgfs_lock); +} +EXPORT_SYMBOL_GPL(mtk_vcodec_dbgfs_init); + +void mtk_vcodec_dbgfs_deinit(struct mtk_vcodec_dev *vcodec_dev) +{ + debugfs_remove_recursive(vcodec_dev->dbgfs.vcodec_root); +} +EXPORT_SYMBOL_GPL(mtk_vcodec_dbgfs_deinit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Mediatek video codec driver"); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dbgfs.h b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dbgfs.h new file mode 100644 index 000000000000..241ff8197e73 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dbgfs.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Yunfei Dong <yunfei.dong@mediatek.com> + */ + +#ifndef __MTK_VCODEC_DBGFS_H__ +#define __MTK_VCODEC_DBGFS_H__ + +struct mtk_vcodec_dev; +struct mtk_vcodec_ctx; + +/* + * enum mtk_vdec_dbgfs_log_index - used to get different debug information + */ +enum mtk_vdec_dbgfs_log_index { + MTK_VDEC_DBGFS_PICINFO, + MTK_VDEC_DBGFS_FORMAT, + MTK_VDEC_DBGFS_MAX, +}; + +/** + * struct mtk_vcodec_dbgfs_inst - debugfs information for each inst + * @node: list node for each inst + * @vcodec_ctx: struct mtk_vcodec_ctx + * @inst_id: index of the context that the same with ctx->id + */ +struct mtk_vcodec_dbgfs_inst { + struct list_head node; + struct mtk_vcodec_ctx *vcodec_ctx; + int inst_id; +}; + +/** + * struct mtk_vcodec_dbgfs - dbgfs information + * @dbgfs_head: list head used to link each instance + * @vcodec_root: vcodec dbgfs entry + * @dbgfs_lock: dbgfs lock used to protect dbgfs_buf + * @dbgfs_buf: dbgfs buf used to store dbgfs cmd + * @buf_size: buffer size of dbgfs + * @inst_count: the count of total instance + */ +struct mtk_vcodec_dbgfs { + struct list_head dbgfs_head; + struct dentry *vcodec_root; + struct mutex dbgfs_lock; + char dbgfs_buf[1024]; + int buf_size; + int inst_count; +}; + +#if defined(CONFIG_DEBUG_FS) +void mtk_vcodec_dbgfs_create(struct mtk_vcodec_ctx *ctx); +void mtk_vcodec_dbgfs_remove(struct mtk_vcodec_dev *vcodec_dev, int ctx_id); +void mtk_vcodec_dbgfs_init(struct mtk_vcodec_dev *vcodec_dev, bool is_encode); +void mtk_vcodec_dbgfs_deinit(struct mtk_vcodec_dev *vcodec_dev); +#else +static inline void mtk_vcodec_dbgfs_create(struct mtk_vcodec_ctx *ctx) +{ +} + +static inline void mtk_vcodec_dbgfs_remove(struct mtk_vcodec_dev *vcodec_dev, int ctx_id) +{ +} + +static inline void mtk_vcodec_dbgfs_init(struct mtk_vcodec_dev *vcodec_dev, bool is_encode) +{ +} + +static inline void mtk_vcodec_dbgfs_deinit(struct mtk_vcodec_dev *vcodec_dev) +{ +} +#endif +#endif diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c index 9c652beb3f19..d41f2121b94f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c @@ -215,6 +215,7 @@ static int fops_vcodec_open(struct file *file) ctx->dev->vdec_pdata->init_vdec_params(ctx); list_add(&ctx->list, &dev->ctx_list); + mtk_vcodec_dbgfs_create(ctx); mutex_unlock(&dev->dev_mutex); mtk_v4l2_debug(0, "%s decoder [%d]", dev_name(&dev->plat_dev->dev), @@ -256,6 +257,7 @@ static int fops_vcodec_release(struct file *file) v4l2_fh_exit(&ctx->fh); v4l2_ctrl_handler_free(&ctx->ctrl_hdl); + mtk_vcodec_dbgfs_remove(dev, ctx->id); list_del_init(&ctx->list); kfree(ctx); mutex_unlock(&dev->dev_mutex); @@ -310,7 +312,6 @@ static int mtk_vcodec_probe(struct platform_device *pdev) } if (IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch)) { - vdec_msg_queue_init_ctx(&dev->msg_queue_core_ctx, MTK_VDEC_CORE); dev->core_workqueue = alloc_ordered_workqueue("core-decoder", WQ_MEM_RECLAIM | WQ_FREEZABLE); @@ -423,6 +424,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev) mtk_v4l2_debug(0, "media registered as /dev/media%d", vfd_dec->minor); } + mtk_vcodec_dbgfs_init(dev, false); mtk_v4l2_debug(0, "decoder registered as /dev/video%d", vfd_dec->minor); return 0; @@ -498,6 +500,7 @@ static void mtk_vcodec_dec_remove(struct platform_device *pdev) if (dev->vfd_dec) video_unregister_device(dev->vfd_dec); + mtk_vcodec_dbgfs_deinit(dev); v4l2_device_unregister(&dev->v4l2_dev); if (!dev->vdec_pdata->is_subdev_supported) pm_runtime_disable(dev->pm.dev); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c index b753bf54ebd9..e1cb2f8dca33 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c @@ -148,20 +148,21 @@ static int mtk_vdec_hw_probe(struct platform_device *pdev) ret = mtk_vcodec_init_dec_clk(pdev, &subdev_dev->pm); if (ret) return ret; - pm_runtime_enable(&pdev->dev); + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; of_id = of_match_device(mtk_vdec_hw_match, dev); if (!of_id) { dev_err(dev, "Can't get vdec subdev id.\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } hw_idx = (enum mtk_vdec_hw_id)(uintptr_t)of_id->data; if (hw_idx >= MTK_VDEC_HW_MAX) { dev_err(dev, "Hardware index %d not correct.\n", hw_idx); - ret = -EINVAL; - goto err; + return -EINVAL; } main_dev->subdev_dev[hw_idx] = subdev_dev; @@ -173,14 +174,14 @@ static int mtk_vdec_hw_probe(struct platform_device *pdev) if (IS_SUPPORT_VDEC_HW_IRQ(hw_idx)) { ret = mtk_vdec_hw_init_irq(subdev_dev); if (ret) - goto err; + return ret; } subdev_dev->reg_base[VDEC_HW_MISC] = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR((__force void *)subdev_dev->reg_base[VDEC_HW_MISC])) { ret = PTR_ERR((__force void *)subdev_dev->reg_base[VDEC_HW_MISC]); - goto err; + return ret; } if (!main_dev->subdev_prob_done) @@ -188,21 +189,10 @@ static int mtk_vdec_hw_probe(struct platform_device *pdev) platform_set_drvdata(pdev, subdev_dev); return 0; -err: - pm_runtime_disable(subdev_dev->pm.dev); - return ret; -} - -static int mtk_vdec_hw_remove(struct platform_device *pdev) -{ - pm_runtime_disable(&pdev->dev); - - return 0; } static struct platform_driver mtk_vdec_driver = { .probe = mtk_vdec_hw_probe, - .remove = mtk_vdec_hw_remove, .driver = { .name = "mtk-vdec-comp", .of_match_table = mtk_vdec_hw_match, diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index 3000db975e5f..db1e14a1bd6c 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -107,11 +107,103 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { }, .codec_type = V4L2_PIX_FMT_VP9_FRAME, }, + { + .cfg = { + .id = V4L2_CID_STATELESS_HEVC_SPS, + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { + .cfg = { + .id = V4L2_CID_STATELESS_HEVC_PPS, + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { + .cfg = { + .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { + .cfg = { + .id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { + .cfg = { + .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + .menu_skip_mask = + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { + .cfg = { + .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, + .min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + .def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + .max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { + .cfg = { + .id = V4L2_CID_STATELESS_HEVC_START_CODE, + .min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + .def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + .max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { + .cfg = { + .id = V4L2_CID_STATELESS_AV1_SEQUENCE, + + }, + .codec_type = V4L2_PIX_FMT_AV1_FRAME, + }, + { + .cfg = { + .id = V4L2_CID_STATELESS_AV1_FRAME, + + }, + .codec_type = V4L2_PIX_FMT_AV1_FRAME, + }, + { + .cfg = { + .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY, + .dims = { V4L2_AV1_MAX_TILE_COUNT }, + + }, + .codec_type = V4L2_PIX_FMT_AV1_FRAME, + }, + { + .cfg = { + .id = V4L2_CID_MPEG_VIDEO_AV1_PROFILE, + .min = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + .def = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + .max = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + }, + .codec_type = V4L2_PIX_FMT_AV1_FRAME, + }, + { + .cfg = { + .id = V4L2_CID_MPEG_VIDEO_AV1_LEVEL, + .min = V4L2_MPEG_VIDEO_AV1_LEVEL_2_0, + .def = V4L2_MPEG_VIDEO_AV1_LEVEL_4_0, + .max = V4L2_MPEG_VIDEO_AV1_LEVEL_5_1, + }, + .codec_type = V4L2_PIX_FMT_AV1_FRAME, + }, }; #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) -static struct mtk_video_fmt mtk_video_formats[5]; +static struct mtk_video_fmt mtk_video_formats[7]; static struct mtk_video_fmt default_out_format; static struct mtk_video_fmt default_cap_format; @@ -240,7 +332,7 @@ static void mtk_vdec_worker(struct work_struct *work) mtk_v4l2_err("vb2 buffer media request is NULL"); ret = vdec_if_decode(ctx, bs_src, NULL, &res_chg); - if (ret) { + if (ret && ret != -EAGAIN) { mtk_v4l2_err(" <===[%d], src_buf[%d] sz=0x%zx pts=%llu vdec_if_decode() ret=%d res_chg=%d===>", ctx->id, vb2_src->index, bs_src->size, vb2_src->timestamp, ret, res_chg); @@ -356,6 +448,8 @@ static void mtk_vcodec_add_formats(unsigned int fourcc, case V4L2_PIX_FMT_H264_SLICE: case V4L2_PIX_FMT_VP8_FRAME: case V4L2_PIX_FMT_VP9_FRAME: + case V4L2_PIX_FMT_HEVC_SLICE: + case V4L2_PIX_FMT_AV1_FRAME: mtk_video_formats[count_formats].fourcc = fourcc; mtk_video_formats[count_formats].type = MTK_FMT_DEC; mtk_video_formats[count_formats].num_planes = 1; @@ -412,6 +506,14 @@ static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_ctx *ctx) mtk_vcodec_add_formats(V4L2_PIX_FMT_VP9_FRAME, ctx); out_format_count++; } + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_HEVC_FRAME) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_HEVC_SLICE, ctx); + out_format_count++; + } + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_AV1_FRAME) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_AV1_FRAME, ctx); + out_format_count++; + } if (cap_format_count) default_cap_format = mtk_video_formats[cap_format_count - 1]; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index 9acab54fd650..f17d67e781c9 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -16,6 +16,7 @@ #include <media/v4l2-mem2mem.h> #include <media/videobuf2-core.h> +#include "mtk_vcodec_dbgfs.h" #include "mtk_vcodec_util.h" #include "vdec_msg_queue.h" @@ -347,6 +348,8 @@ enum mtk_vdec_format_types { MTK_VDEC_FORMAT_H264_SLICE = 0x100, MTK_VDEC_FORMAT_VP8_FRAME = 0x200, MTK_VDEC_FORMAT_VP9_FRAME = 0x400, + MTK_VDEC_FORMAT_AV1_FRAME = 0x800, + MTK_VDEC_FORMAT_HEVC_FRAME = 0x1000, MTK_VCODEC_INNER_RACING = 0x20000, }; @@ -461,7 +464,6 @@ struct mtk_vcodec_enc_pdata { * @enc_capability: used to identify encode capability * * @core_workqueue: queue used for core hardware decode - * @msg_queue_core_ctx: msg queue context used for core workqueue * * @subdev_dev: subdev hardware device * @subdev_prob_done: check whether all used hw device is prob done @@ -470,6 +472,7 @@ struct mtk_vcodec_enc_pdata { * @dec_active_cnt: used to mark whether need to record register value * @vdec_racing_info: record register value * @dec_racing_info_mutex: mutex lock used for inner racing mode + * @dbgfs: debug log related information */ struct mtk_vcodec_dev { struct v4l2_device v4l2_dev; @@ -510,7 +513,6 @@ struct mtk_vcodec_dev { unsigned int enc_capability; struct workqueue_struct *core_workqueue; - struct vdec_msg_queue_ctx msg_queue_core_ctx; void *subdev_dev[MTK_VDEC_HW_MAX]; int (*subdev_prob_done)(struct mtk_vcodec_dev *vdec_dev); @@ -520,6 +522,8 @@ struct mtk_vcodec_dev { u32 vdec_racing_info[132]; /* Protects access to vdec_racing_info data */ struct mutex dec_racing_info_mutex; + + struct mtk_vcodec_dbgfs dbgfs; }; static inline struct mtk_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c index db65e77bd373..9ff439a50f53 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc.c @@ -505,13 +505,13 @@ static int vidioc_venc_s_fmt_out(struct file *file, void *priv, f->fmt.pix.pixelformat = fmt->fourcc; } - q_data->visible_width = f->fmt.pix_mp.width; - q_data->visible_height = f->fmt.pix_mp.height; - q_data->fmt = fmt; - ret = vidioc_try_fmt_out(ctx, f, q_data->fmt); + ret = vidioc_try_fmt_out(ctx, f, fmt); if (ret) return ret; + q_data->fmt = fmt; + q_data->visible_width = f->fmt.pix_mp.width; + q_data->visible_height = f->fmt.pix_mp.height; q_data->coded_width = f->fmt.pix_mp.width; q_data->coded_height = f->fmt.pix_mp.height; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c index 168004a08888..5df0a22ff3b5 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c @@ -358,6 +358,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev) goto err_enc_reg; } + mtk_vcodec_dbgfs_init(dev, true); mtk_v4l2_debug(0, "encoder %d registered as /dev/video%d", dev->venc_pdata->core_id, vfd_enc->num); @@ -468,6 +469,7 @@ static void mtk_vcodec_enc_remove(struct platform_device *pdev) if (dev->vfd_enc) video_unregister_device(dev->vfd_enc); + mtk_vcodec_dbgfs_deinit(dev); v4l2_device_unregister(&dev->v4l2_dev); pm_runtime_disable(dev->pm.dev); mtk_vcodec_fw_release(dev->fw_handler); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c index ace78c4b5b9e..f214e6f67005 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c @@ -13,6 +13,14 @@ #include "mtk_vcodec_drv.h" #include "mtk_vcodec_util.h" +#if defined(CONFIG_DEBUG_FS) +int mtk_vcodec_dbg; +EXPORT_SYMBOL(mtk_vcodec_dbg); + +int mtk_v4l2_dbg_level; +EXPORT_SYMBOL(mtk_v4l2_dbg_level); +#endif + void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_ctx *data, unsigned int reg_idx) { diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h index 71956627a0e2..88d389b65f13 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h @@ -35,15 +35,35 @@ struct mtk_vcodec_dev; pr_err("[MTK_VCODEC][ERROR][%d]: " fmt "\n", \ ((struct mtk_vcodec_ctx *)(h)->ctx)->id, ##args) +#if defined(CONFIG_DEBUG_FS) +extern int mtk_v4l2_dbg_level; +extern int mtk_vcodec_dbg; -#define mtk_v4l2_debug(level, fmt, args...) pr_debug(fmt, ##args) +#define mtk_v4l2_debug(level, fmt, args...) \ + do { \ + if (mtk_v4l2_dbg_level >= (level)) \ + pr_debug("[MTK_V4L2] %s, %d: " fmt "\n", \ + __func__, __LINE__, ##args); \ + } while (0) -#define mtk_v4l2_debug_enter() mtk_v4l2_debug(3, "+") -#define mtk_v4l2_debug_leave() mtk_v4l2_debug(3, "-") +#define mtk_vcodec_debug(h, fmt, args...) \ + do { \ + if (mtk_vcodec_dbg) \ + dev_dbg(&(((struct mtk_vcodec_ctx *)(h)->ctx)->dev->plat_dev->dev), \ + "[MTK_VCODEC][%d]: %s, %d " fmt "\n", \ + ((struct mtk_vcodec_ctx *)(h)->ctx)->id, \ + __func__, __LINE__, ##args); \ + } while (0) +#else +#define mtk_v4l2_debug(level, fmt, args...) pr_debug(fmt, ##args) #define mtk_vcodec_debug(h, fmt, args...) \ pr_debug("[MTK_VCODEC][%d]: " fmt "\n", \ ((struct mtk_vcodec_ctx *)(h)->ctx)->id, ##args) +#endif + +#define mtk_v4l2_debug_enter() mtk_v4l2_debug(3, "+") +#define mtk_v4l2_debug_leave() mtk_v4l2_debug(3, "-") #define mtk_vcodec_debug_enter(h) mtk_vcodec_debug(h, "+") #define mtk_vcodec_debug_leave(h) mtk_vcodec_debug(h, "-") diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c new file mode 100644 index 000000000000..404a1a23fd40 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c @@ -0,0 +1,2207 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Xiaoyong Lu <xiaoyong.lu@mediatek.com> + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <media/videobuf2-dma-contig.h> + +#include "../mtk_vcodec_util.h" +#include "../mtk_vcodec_dec.h" +#include "../mtk_vcodec_intr.h" +#include "../vdec_drv_base.h" +#include "../vdec_drv_if.h" +#include "../vdec_vpu_if.h" + +#define AV1_MAX_FRAME_BUF_COUNT (V4L2_AV1_TOTAL_REFS_PER_FRAME + 1) +#define AV1_TILE_BUF_SIZE 64 +#define AV1_SCALE_SUBPEL_BITS 10 +#define AV1_REF_SCALE_SHIFT 14 +#define AV1_REF_NO_SCALE BIT(AV1_REF_SCALE_SHIFT) +#define AV1_REF_INVALID_SCALE -1 +#define AV1_CDF_TABLE_BUFFER_SIZE 16384 +#define AV1_PRIMARY_REF_NONE 7 + +#define AV1_INVALID_IDX -1 + +#define AV1_DIV_ROUND_UP_POW2(value, n) \ +({ \ + typeof(n) _n = n; \ + typeof(value) _value = value; \ + (_value + (BIT(_n) >> 1)) >> _n; \ +}) + +#define AV1_DIV_ROUND_UP_POW2_SIGNED(value, n) \ +({ \ + typeof(n) _n_ = n; \ + typeof(value) _value_ = value; \ + (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \ + : AV1_DIV_ROUND_UP_POW2((_value_), (_n_))); \ +}) + +#define BIT_FLAG(x, bit) (!!((x)->flags & (bit))) +#define SEGMENTATION_FLAG(x, name) (!!((x)->flags & V4L2_AV1_SEGMENTATION_FLAG_##name)) +#define QUANT_FLAG(x, name) (!!((x)->flags & V4L2_AV1_QUANTIZATION_FLAG_##name)) +#define SEQUENCE_FLAG(x, name) (!!((x)->flags & V4L2_AV1_SEQUENCE_FLAG_##name)) +#define FH_FLAG(x, name) (!!((x)->flags & V4L2_AV1_FRAME_FLAG_##name)) + +#define MINQ 0 +#define MAXQ 255 + +#define DIV_LUT_PREC_BITS 14 +#define DIV_LUT_BITS 8 +#define DIV_LUT_NUM BIT(DIV_LUT_BITS) +#define WARP_PARAM_REDUCE_BITS 6 +#define WARPEDMODEL_PREC_BITS 16 + +#define SEG_LVL_ALT_Q 0 +#define SECONDARY_FILTER_STRENGTH_NUM_BITS 2 + +static const short div_lut[DIV_LUT_NUM + 1] = { + 16384, 16320, 16257, 16194, 16132, 16070, 16009, 15948, 15888, 15828, 15768, + 15709, 15650, 15592, 15534, 15477, 15420, 15364, 15308, 15252, 15197, 15142, + 15087, 15033, 14980, 14926, 14873, 14821, 14769, 14717, 14665, 14614, 14564, + 14513, 14463, 14413, 14364, 14315, 14266, 14218, 14170, 14122, 14075, 14028, + 13981, 13935, 13888, 13843, 13797, 13752, 13707, 13662, 13618, 13574, 13530, + 13487, 13443, 13400, 13358, 13315, 13273, 13231, 13190, 13148, 13107, 13066, + 13026, 12985, 12945, 12906, 12866, 12827, 12788, 12749, 12710, 12672, 12633, + 12596, 12558, 12520, 12483, 12446, 12409, 12373, 12336, 12300, 12264, 12228, + 12193, 12157, 12122, 12087, 12053, 12018, 11984, 11950, 11916, 11882, 11848, + 11815, 11782, 11749, 11716, 11683, 11651, 11619, 11586, 11555, 11523, 11491, + 11460, 11429, 11398, 11367, 11336, 11305, 11275, 11245, 11215, 11185, 11155, + 11125, 11096, 11067, 11038, 11009, 10980, 10951, 10923, 10894, 10866, 10838, + 10810, 10782, 10755, 10727, 10700, 10673, 10645, 10618, 10592, 10565, 10538, + 10512, 10486, 10460, 10434, 10408, 10382, 10356, 10331, 10305, 10280, 10255, + 10230, 10205, 10180, 10156, 10131, 10107, 10082, 10058, 10034, 10010, 9986, + 9963, 9939, 9916, 9892, 9869, 9846, 9823, 9800, 9777, 9754, 9732, + 9709, 9687, 9664, 9642, 9620, 9598, 9576, 9554, 9533, 9511, 9489, + 9468, 9447, 9425, 9404, 9383, 9362, 9341, 9321, 9300, 9279, 9259, + 9239, 9218, 9198, 9178, 9158, 9138, 9118, 9098, 9079, 9059, 9039, + 9020, 9001, 8981, 8962, 8943, 8924, 8905, 8886, 8867, 8849, 8830, + 8812, 8793, 8775, 8756, 8738, 8720, 8702, 8684, 8666, 8648, 8630, + 8613, 8595, 8577, 8560, 8542, 8525, 8508, 8490, 8473, 8456, 8439, + 8422, 8405, 8389, 8372, 8355, 8339, 8322, 8306, 8289, 8273, 8257, + 8240, 8224, 8208, 8192, +}; + +/** + * struct vdec_av1_slice_init_vsi - VSI used to initialize instance + * @architecture: architecture type + * @reserved: reserved + * @core_vsi: for core vsi + * @cdf_table_addr: cdf table addr + * @cdf_table_size: cdf table size + * @iq_table_addr: iq table addr + * @iq_table_size: iq table size + * @vsi_size: share vsi structure size + */ +struct vdec_av1_slice_init_vsi { + u32 architecture; + u32 reserved; + u64 core_vsi; + u64 cdf_table_addr; + u32 cdf_table_size; + u64 iq_table_addr; + u32 iq_table_size; + u32 vsi_size; +}; + +/** + * struct vdec_av1_slice_mem - memory address and size + * @buf: dma_addr padding + * @dma_addr: buffer address + * @size: buffer size + * @dma_addr_end: buffer end address + * @padding: for padding + */ +struct vdec_av1_slice_mem { + union { + u64 buf; + dma_addr_t dma_addr; + }; + union { + size_t size; + dma_addr_t dma_addr_end; + u64 padding; + }; +}; + +/** + * struct vdec_av1_slice_state - decoding state + * @err : err type for decode + * @full : transcoded buffer is full or not + * @timeout : decode timeout or not + * @perf : performance enable + * @crc : hw checksum + * @out_size : hw output size + */ +struct vdec_av1_slice_state { + int err; + u32 full; + u32 timeout; + u32 perf; + u32 crc[16]; + u32 out_size; +}; + +/* + * enum vdec_av1_slice_resolution_level - resolution level + */ +enum vdec_av1_slice_resolution_level { + AV1_RES_NONE, + AV1_RES_FHD, + AV1_RES_4K, + AV1_RES_8K, +}; + +/* + * enum vdec_av1_slice_frame_type - av1 frame type + */ +enum vdec_av1_slice_frame_type { + AV1_KEY_FRAME = 0, + AV1_INTER_FRAME, + AV1_INTRA_ONLY_FRAME, + AV1_SWITCH_FRAME, + AV1_FRAME_TYPES, +}; + +/* + * enum vdec_av1_slice_reference_mode - reference mode type + */ +enum vdec_av1_slice_reference_mode { + AV1_SINGLE_REFERENCE = 0, + AV1_COMPOUND_REFERENCE, + AV1_REFERENCE_MODE_SELECT, + AV1_REFERENCE_MODES, +}; + +/** + * struct vdec_av1_slice_tile_group - info for each tile + * @num_tiles: tile number + * @tile_size: input size for each tile + * @tile_start_offset: tile offset to input buffer + */ +struct vdec_av1_slice_tile_group { + u32 num_tiles; + u32 tile_size[V4L2_AV1_MAX_TILE_COUNT]; + u32 tile_start_offset[V4L2_AV1_MAX_TILE_COUNT]; +}; + +/** + * struct vdec_av1_slice_scale_factors - scale info for each ref frame + * @is_scaled: frame is scaled or not + * @x_scale: frame width scale coefficient + * @y_scale: frame height scale coefficient + * @x_step: width step for x_scale + * @y_step: height step for y_scale + */ +struct vdec_av1_slice_scale_factors { + u8 is_scaled; + int x_scale; + int y_scale; + int x_step; + int y_step; +}; + +/** + * struct vdec_av1_slice_frame_refs - ref frame info + * @ref_fb_idx: ref slot index + * @ref_map_idx: ref frame index + * @scale_factors: scale factors for each ref frame + */ +struct vdec_av1_slice_frame_refs { + int ref_fb_idx; + int ref_map_idx; + struct vdec_av1_slice_scale_factors scale_factors; +}; + +/** + * struct vdec_av1_slice_gm - AV1 Global Motion parameters + * @wmtype: The type of global motion transform used + * @wmmat: gm_params + * @alpha: alpha info + * @beta: beta info + * @gamma: gamma info + * @delta: delta info + * @invalid: is invalid or not + */ +struct vdec_av1_slice_gm { + int wmtype; + int wmmat[8]; + short alpha; + short beta; + short gamma; + short delta; + char invalid; +}; + +/** + * struct vdec_av1_slice_sm - AV1 Skip Mode parameters + * @skip_mode_allowed: Skip Mode is allowed or not + * @skip_mode_present: specified that the skip_mode will be present or not + * @skip_mode_frame: specifies the frames to use for compound prediction + */ +struct vdec_av1_slice_sm { + u8 skip_mode_allowed; + u8 skip_mode_present; + int skip_mode_frame[2]; +}; + +/** + * struct vdec_av1_slice_seg - AV1 Segmentation params + * @segmentation_enabled: this frame makes use of the segmentation tool or not + * @segmentation_update_map: segmentation map are updated during the decoding frame + * @segmentation_temporal_update:segmentation map are coded relative the existing segmentaion map + * @segmentation_update_data: new parameters are about to be specified for each segment + * @feature_data: specifies the feature data for a segment feature + * @feature_enabled_mask: the corresponding feature value is coded or not. + * @segid_preskip: segment id will be read before the skip syntax element. + * @last_active_segid: the highest numbered segment id that has some enabled feature + */ +struct vdec_av1_slice_seg { + u8 segmentation_enabled; + u8 segmentation_update_map; + u8 segmentation_temporal_update; + u8 segmentation_update_data; + int feature_data[V4L2_AV1_MAX_SEGMENTS][V4L2_AV1_SEG_LVL_MAX]; + u16 feature_enabled_mask[V4L2_AV1_MAX_SEGMENTS]; + int segid_preskip; + int last_active_segid; +}; + +/** + * struct vdec_av1_slice_delta_q_lf - AV1 Loop Filter delta parameters + * @delta_q_present: specified whether quantizer index delta values are present + * @delta_q_res: specifies the left shift which should be applied to decoded quantizer index + * @delta_lf_present: specifies whether loop filter delta values are present + * @delta_lf_res: specifies the left shift which should be applied to decoded + * loop filter delta values + * @delta_lf_multi: specifies that separate loop filter deltas are sent for horizontal + * luma edges,vertical luma edges,the u edges, and the v edges. + */ +struct vdec_av1_slice_delta_q_lf { + u8 delta_q_present; + u8 delta_q_res; + u8 delta_lf_present; + u8 delta_lf_res; + u8 delta_lf_multi; +}; + +/** + * struct vdec_av1_slice_quantization - AV1 Quantization params + * @base_q_idx: indicates the base frame qindex. This is used for Y AC + * coefficients and as the base value for the other quantizers. + * @qindex: qindex + * @delta_qydc: indicates the Y DC quantizer relative to base_q_idx + * @delta_qudc: indicates the U DC quantizer relative to base_q_idx. + * @delta_quac: indicates the U AC quantizer relative to base_q_idx + * @delta_qvdc: indicates the V DC quantizer relative to base_q_idx + * @delta_qvac: indicates the V AC quantizer relative to base_q_idx + * @using_qmatrix: specifies that the quantizer matrix will be used to + * compute quantizers + * @qm_y: specifies the level in the quantizer matrix that should + * be used for luma plane decoding + * @qm_u: specifies the level in the quantizer matrix that should + * be used for chroma U plane decoding. + * @qm_v: specifies the level in the quantizer matrix that should be + * used for chroma V plane decoding + */ +struct vdec_av1_slice_quantization { + int base_q_idx; + int qindex[V4L2_AV1_MAX_SEGMENTS]; + int delta_qydc; + int delta_qudc; + int delta_quac; + int delta_qvdc; + int delta_qvac; + u8 using_qmatrix; + u8 qm_y; + u8 qm_u; + u8 qm_v; +}; + +/** + * struct vdec_av1_slice_lr - AV1 Loop Restauration parameters + * @use_lr: whether to use loop restoration + * @use_chroma_lr: whether to use chroma loop restoration + * @frame_restoration_type: specifies the type of restoration used for each plane + * @loop_restoration_size: pecifies the size of loop restoration units in units + * of samples in the current plane + */ +struct vdec_av1_slice_lr { + u8 use_lr; + u8 use_chroma_lr; + u8 frame_restoration_type[V4L2_AV1_NUM_PLANES_MAX]; + u32 loop_restoration_size[V4L2_AV1_NUM_PLANES_MAX]; +}; + +/** + * struct vdec_av1_slice_loop_filter - AV1 Loop filter parameters + * @loop_filter_level: an array containing loop filter strength values. + * @loop_filter_ref_deltas: contains the adjustment needed for the filter + * level based on the chosen reference frame + * @loop_filter_mode_deltas: contains the adjustment needed for the filter + * level based on the chosen mode + * @loop_filter_sharpness: indicates the sharpness level. The loop_filter_level + * and loop_filter_sharpness together determine when + * a block edge is filtered, and by how much the + * filtering can change the sample values + * @loop_filter_delta_enabled: filetr level depends on the mode and reference + * frame used to predict a block + */ +struct vdec_av1_slice_loop_filter { + u8 loop_filter_level[4]; + int loop_filter_ref_deltas[V4L2_AV1_TOTAL_REFS_PER_FRAME]; + int loop_filter_mode_deltas[2]; + u8 loop_filter_sharpness; + u8 loop_filter_delta_enabled; +}; + +/** + * struct vdec_av1_slice_cdef - AV1 CDEF parameters + * @cdef_damping: controls the amount of damping in the deringing filter + * @cdef_y_strength: specifies the strength of the primary filter and secondary filter + * @cdef_uv_strength: specifies the strength of the primary filter and secondary filter + * @cdef_bits: specifies the number of bits needed to specify which + * CDEF filter to apply + */ +struct vdec_av1_slice_cdef { + u8 cdef_damping; + u8 cdef_y_strength[8]; + u8 cdef_uv_strength[8]; + u8 cdef_bits; +}; + +/** + * struct vdec_av1_slice_mfmv - AV1 mfmv parameters + * @mfmv_valid_ref: mfmv_valid_ref + * @mfmv_dir: mfmv_dir + * @mfmv_ref_to_cur: mfmv_ref_to_cur + * @mfmv_ref_frame_idx: mfmv_ref_frame_idx + * @mfmv_count: mfmv_count + */ +struct vdec_av1_slice_mfmv { + u32 mfmv_valid_ref[3]; + u32 mfmv_dir[3]; + int mfmv_ref_to_cur[3]; + int mfmv_ref_frame_idx[3]; + int mfmv_count; +}; + +/** + * struct vdec_av1_slice_tile - AV1 Tile info + * @tile_cols: specifies the number of tiles across the frame + * @tile_rows: pecifies the number of tiles down the frame + * @mi_col_starts: an array specifying the start column + * @mi_row_starts: an array specifying the start row + * @context_update_tile_id: specifies which tile to use for the CDF update + * @uniform_tile_spacing_flag: tiles are uniformly spaced across the frame + * or the tile sizes are coded + */ +struct vdec_av1_slice_tile { + u8 tile_cols; + u8 tile_rows; + int mi_col_starts[V4L2_AV1_MAX_TILE_COLS + 1]; + int mi_row_starts[V4L2_AV1_MAX_TILE_ROWS + 1]; + u8 context_update_tile_id; + u8 uniform_tile_spacing_flag; +}; + +/** + * struct vdec_av1_slice_uncompressed_header - Represents an AV1 Frame Header OBU + * @use_ref_frame_mvs: use_ref_frame_mvs flag + * @order_hint: specifies OrderHintBits least significant bits of the expected + * @gm: global motion param + * @upscaled_width: the upscaled width + * @frame_width: frame's width + * @frame_height: frame's height + * @reduced_tx_set: frame is restricted to a reduced subset of the full + * set of transform types + * @tx_mode: specifies how the transform size is determined + * @uniform_tile_spacing_flag: tiles are uniformly spaced across the frame + * or the tile sizes are coded + * @interpolation_filter: specifies the filter selection used for performing inter prediction + * @allow_warped_motion: motion_mode may be present or not + * @is_motion_mode_switchable : euqlt to 0 specifies that only the SIMPLE motion mode will be used + * @reference_mode : frame reference mode selected + * @allow_high_precision_mv: specifies that motion vectors are specified to + * quarter pel precision or to eighth pel precision + * @allow_intra_bc: ubducates that intra block copy may be used in this frame + * @force_integer_mv: specifies motion vectors will always be integers or + * can contain fractional bits + * @allow_screen_content_tools: intra blocks may use palette encoding + * @error_resilient_mode: error resislent mode is enable/disable + * @frame_type: specifies the AV1 frame type + * @primary_ref_frame: specifies which reference frame contains the CDF values + * and other state that should be loaded at the start of the frame + * slots will be updated with the current frame after it is decoded + * @disable_frame_end_update_cdf:indicates the end of frame CDF update is disable or enable + * @disable_cdf_update: specified whether the CDF update in the symbol + * decoding process should be disables + * @skip_mode: av1 skip mode parameters + * @seg: av1 segmentaon parameters + * @delta_q_lf: av1 delta loop fileter + * @quant: av1 Quantization params + * @lr: av1 Loop Restauration parameters + * @superres_denom: the denominator for the upscaling ratio + * @loop_filter: av1 Loop filter parameters + * @cdef: av1 CDEF parameters + * @mfmv: av1 mfmv parameters + * @tile: av1 Tile info + * @frame_is_intra: intra frame + * @loss_less_array: loss less array + * @coded_loss_less: coded lsss less + * @mi_rows: size of mi unit in rows + * @mi_cols: size of mi unit in cols + */ +struct vdec_av1_slice_uncompressed_header { + u8 use_ref_frame_mvs; + int order_hint; + struct vdec_av1_slice_gm gm[V4L2_AV1_TOTAL_REFS_PER_FRAME]; + u32 upscaled_width; + u32 frame_width; + u32 frame_height; + u8 reduced_tx_set; + u8 tx_mode; + u8 uniform_tile_spacing_flag; + u8 interpolation_filter; + u8 allow_warped_motion; + u8 is_motion_mode_switchable; + u8 reference_mode; + u8 allow_high_precision_mv; + u8 allow_intra_bc; + u8 force_integer_mv; + u8 allow_screen_content_tools; + u8 error_resilient_mode; + u8 frame_type; + u8 primary_ref_frame; + u8 disable_frame_end_update_cdf; + u32 disable_cdf_update; + struct vdec_av1_slice_sm skip_mode; + struct vdec_av1_slice_seg seg; + struct vdec_av1_slice_delta_q_lf delta_q_lf; + struct vdec_av1_slice_quantization quant; + struct vdec_av1_slice_lr lr; + u32 superres_denom; + struct vdec_av1_slice_loop_filter loop_filter; + struct vdec_av1_slice_cdef cdef; + struct vdec_av1_slice_mfmv mfmv; + struct vdec_av1_slice_tile tile; + u8 frame_is_intra; + u8 loss_less_array[V4L2_AV1_MAX_SEGMENTS]; + u8 coded_loss_less; + u32 mi_rows; + u32 mi_cols; +}; + +/** + * struct vdec_av1_slice_seq_header - Represents an AV1 Sequence OBU + * @bitdepth: the bitdepth to use for the sequence + * @enable_superres: specifies whether the use_superres syntax element may be present + * @enable_filter_intra: specifies the use_filter_intra syntax element may be present + * @enable_intra_edge_filter: whether the intra edge filtering process should be enabled + * @enable_interintra_compound: specifies the mode info fo rinter blocks may + * contain the syntax element interintra + * @enable_masked_compound: specifies the mode info fo rinter blocks may + * contain the syntax element compound_type + * @enable_dual_filter: the inter prediction filter type may be specified independently + * @enable_jnt_comp: distance weights process may be used for inter prediction + * @mono_chrome: indicates the video does not contain U and V color planes + * @enable_order_hint: tools based on the values of order hints may be used + * @order_hint_bits: the number of bits used for the order_hint field at each frame + * @use_128x128_superblock: indicates superblocks contain 128*128 luma samples + * @subsampling_x: the chroma subsamling format + * @subsampling_y: the chroma subsamling format + * @max_frame_width: the maximum frame width for the frames represented by sequence + * @max_frame_height: the maximum frame height for the frames represented by sequence + */ +struct vdec_av1_slice_seq_header { + u8 bitdepth; + u8 enable_superres; + u8 enable_filter_intra; + u8 enable_intra_edge_filter; + u8 enable_interintra_compound; + u8 enable_masked_compound; + u8 enable_dual_filter; + u8 enable_jnt_comp; + u8 mono_chrome; + u8 enable_order_hint; + u8 order_hint_bits; + u8 use_128x128_superblock; + u8 subsampling_x; + u8 subsampling_y; + u32 max_frame_width; + u32 max_frame_height; +}; + +/** + * struct vdec_av1_slice_frame - Represents current Frame info + * @uh: uncompressed header info + * @seq: sequence header info + * @large_scale_tile: is large scale mode + * @cur_ts: current frame timestamp + * @prev_fb_idx: prev slot id + * @ref_frame_sign_bias: arrays for ref_frame sign bias + * @order_hints: arrays for ref_frame order hint + * @ref_frame_valid: arrays for valid ref_frame + * @ref_frame_map: map to slot frame info + * @frame_refs: ref_frame info + */ +struct vdec_av1_slice_frame { + struct vdec_av1_slice_uncompressed_header uh; + struct vdec_av1_slice_seq_header seq; + u8 large_scale_tile; + u64 cur_ts; + int prev_fb_idx; + u8 ref_frame_sign_bias[V4L2_AV1_TOTAL_REFS_PER_FRAME]; + u32 order_hints[V4L2_AV1_REFS_PER_FRAME]; + u32 ref_frame_valid[V4L2_AV1_REFS_PER_FRAME]; + int ref_frame_map[V4L2_AV1_TOTAL_REFS_PER_FRAME]; + struct vdec_av1_slice_frame_refs frame_refs[V4L2_AV1_REFS_PER_FRAME]; +}; + +/** + * struct vdec_av1_slice_work_buffer - work buffer for lat + * @mv_addr: mv buffer memory info + * @cdf_addr: cdf buffer memory info + * @segid_addr: segid buffer memory info + */ +struct vdec_av1_slice_work_buffer { + struct vdec_av1_slice_mem mv_addr; + struct vdec_av1_slice_mem cdf_addr; + struct vdec_av1_slice_mem segid_addr; +}; + +/** + * struct vdec_av1_slice_frame_info - frame info for each slot + * @frame_type: frame type + * @frame_is_intra: is intra frame + * @order_hint: order hint + * @order_hints: referece frame order hint + * @upscaled_width: upscale width + * @pic_pitch: buffer pitch + * @frame_width: frane width + * @frame_height: frame height + * @mi_rows: rows in mode info + * @mi_cols: cols in mode info + * @ref_count: mark to reference frame counts + */ +struct vdec_av1_slice_frame_info { + u8 frame_type; + u8 frame_is_intra; + int order_hint; + u32 order_hints[V4L2_AV1_REFS_PER_FRAME]; + u32 upscaled_width; + u32 pic_pitch; + u32 frame_width; + u32 frame_height; + u32 mi_rows; + u32 mi_cols; + int ref_count; +}; + +/** + * struct vdec_av1_slice_slot - slot info that needs to be saved in the global instance + * @frame_info: frame info for each slot + * @timestamp: time stamp info + */ +struct vdec_av1_slice_slot { + struct vdec_av1_slice_frame_info frame_info[AV1_MAX_FRAME_BUF_COUNT]; + u64 timestamp[AV1_MAX_FRAME_BUF_COUNT]; +}; + +/** + * struct vdec_av1_slice_fb - frame buffer for decoding + * @y: current y buffer address info + * @c: current c buffer address info + */ +struct vdec_av1_slice_fb { + struct vdec_av1_slice_mem y; + struct vdec_av1_slice_mem c; +}; + +/** + * struct vdec_av1_slice_vsi - exchange frame information between Main CPU and MicroP + * @bs: input buffer info + * @work_buffer: working buffe for hw + * @cdf_table: cdf_table buffer + * @cdf_tmp: cdf temp buffer + * @rd_mv: mv buffer for lat output , core input + * @ube: ube buffer + * @trans: transcoded buffer + * @err_map: err map buffer + * @row_info: row info buffer + * @fb: current y/c buffer + * @ref: ref y/c buffer + * @iq_table: iq table buffer + * @tile: tile buffer + * @slots: slots info for each frame + * @slot_id: current frame slot id + * @frame: current frame info + * @state: status after decode done + * @cur_lst_tile_id: tile id for large scale + */ +struct vdec_av1_slice_vsi { + /* lat */ + struct vdec_av1_slice_mem bs; + struct vdec_av1_slice_work_buffer work_buffer[AV1_MAX_FRAME_BUF_COUNT]; + struct vdec_av1_slice_mem cdf_table; + struct vdec_av1_slice_mem cdf_tmp; + /* LAT stage's output, Core stage's input */ + struct vdec_av1_slice_mem rd_mv; + struct vdec_av1_slice_mem ube; + struct vdec_av1_slice_mem trans; + struct vdec_av1_slice_mem err_map; + struct vdec_av1_slice_mem row_info; + /* core */ + struct vdec_av1_slice_fb fb; + struct vdec_av1_slice_fb ref[V4L2_AV1_REFS_PER_FRAME]; + struct vdec_av1_slice_mem iq_table; + /* lat and core share*/ + struct vdec_av1_slice_mem tile; + struct vdec_av1_slice_slot slots; + s8 slot_id; + struct vdec_av1_slice_frame frame; + struct vdec_av1_slice_state state; + u32 cur_lst_tile_id; +}; + +/** + * struct vdec_av1_slice_pfc - per-frame context that contains a local vsi. + * pass it from lat to core + * @vsi: local vsi. copy to/from remote vsi before/after decoding + * @ref_idx: reference buffer timestamp + * @seq: picture sequence + */ +struct vdec_av1_slice_pfc { + struct vdec_av1_slice_vsi vsi; + u64 ref_idx[V4L2_AV1_REFS_PER_FRAME]; + int seq; +}; + +/** + * struct vdec_av1_slice_instance - represent one av1 instance + * @ctx: pointer to codec's context + * @vpu: VPU instance + * @iq_table: iq table buffer + * @cdf_table: cdf table buffer + * @mv: mv working buffer + * @cdf: cdf working buffer + * @seg: segmentation working buffer + * @cdf_temp: cdf temp buffer + * @tile: tile buffer + * @slots: slots info + * @tile_group: tile_group entry + * @level: level of current resolution + * @width: width of last picture + * @height: height of last picture + * @frame_type: frame_type of last picture + * @irq_enabled: irq to Main CPU or MicroP + * @inneracing_mode: is inneracing mode + * @init_vsi: vsi used for initialized AV1 instance + * @vsi: vsi used for decoding/flush ... + * @core_vsi: vsi used for Core stage + * @seq: global picture sequence + */ +struct vdec_av1_slice_instance { + struct mtk_vcodec_ctx *ctx; + struct vdec_vpu_inst vpu; + + struct mtk_vcodec_mem iq_table; + struct mtk_vcodec_mem cdf_table; + + struct mtk_vcodec_mem mv[AV1_MAX_FRAME_BUF_COUNT]; + struct mtk_vcodec_mem cdf[AV1_MAX_FRAME_BUF_COUNT]; + struct mtk_vcodec_mem seg[AV1_MAX_FRAME_BUF_COUNT]; + struct mtk_vcodec_mem cdf_temp; + struct mtk_vcodec_mem tile; + struct vdec_av1_slice_slot slots; + struct vdec_av1_slice_tile_group tile_group; + + /* for resolution change and get_pic_info */ + enum vdec_av1_slice_resolution_level level; + u32 width; + u32 height; + + u32 frame_type; + u32 irq_enabled; + u32 inneracing_mode; + + /* MicroP vsi */ + union { + struct vdec_av1_slice_init_vsi *init_vsi; + struct vdec_av1_slice_vsi *vsi; + }; + struct vdec_av1_slice_vsi *core_vsi; + int seq; +}; + +static int vdec_av1_slice_core_decode(struct vdec_lat_buf *lat_buf); + +static inline int vdec_av1_slice_get_msb(u32 n) +{ + if (n == 0) + return 0; + return 31 ^ __builtin_clz(n); +} + +static inline bool vdec_av1_slice_need_scale(u32 ref_width, u32 ref_height, + u32 this_width, u32 this_height) +{ + return ((this_width << 1) >= ref_width) && + ((this_height << 1) >= ref_height) && + (this_width <= (ref_width << 4)) && + (this_height <= (ref_height << 4)); +} + +static void *vdec_av1_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) +{ + struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, id); + + if (!ctrl) + return ERR_PTR(-EINVAL); + + return ctrl->p_cur.p; +} + +static int vdec_av1_slice_init_cdf_table(struct vdec_av1_slice_instance *instance) +{ + u8 *remote_cdf_table; + struct mtk_vcodec_ctx *ctx; + struct vdec_av1_slice_init_vsi *vsi; + int ret; + + ctx = instance->ctx; + vsi = instance->vpu.vsi; + remote_cdf_table = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, + (u32)vsi->cdf_table_addr); + if (IS_ERR(remote_cdf_table)) { + mtk_vcodec_err(instance, "failed to map cdf table\n"); + return PTR_ERR(remote_cdf_table); + } + + mtk_vcodec_debug(instance, "map cdf table to 0x%p\n", + remote_cdf_table); + + if (instance->cdf_table.va) + mtk_vcodec_mem_free(ctx, &instance->cdf_table); + instance->cdf_table.size = vsi->cdf_table_size; + + ret = mtk_vcodec_mem_alloc(ctx, &instance->cdf_table); + if (ret) + return ret; + + memcpy(instance->cdf_table.va, remote_cdf_table, vsi->cdf_table_size); + + return 0; +} + +static int vdec_av1_slice_init_iq_table(struct vdec_av1_slice_instance *instance) +{ + u8 *remote_iq_table; + struct mtk_vcodec_ctx *ctx; + struct vdec_av1_slice_init_vsi *vsi; + int ret; + + ctx = instance->ctx; + vsi = instance->vpu.vsi; + remote_iq_table = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, + (u32)vsi->iq_table_addr); + if (IS_ERR(remote_iq_table)) { + mtk_vcodec_err(instance, "failed to map iq table\n"); + return PTR_ERR(remote_iq_table); + } + + mtk_vcodec_debug(instance, "map iq table to 0x%p\n", remote_iq_table); + + if (instance->iq_table.va) + mtk_vcodec_mem_free(ctx, &instance->iq_table); + instance->iq_table.size = vsi->iq_table_size; + + ret = mtk_vcodec_mem_alloc(ctx, &instance->iq_table); + if (ret) + return ret; + + memcpy(instance->iq_table.va, remote_iq_table, vsi->iq_table_size); + + return 0; +} + +static int vdec_av1_slice_get_new_slot(struct vdec_av1_slice_vsi *vsi) +{ + struct vdec_av1_slice_slot *slots = &vsi->slots; + int new_slot_idx = AV1_INVALID_IDX; + int i; + + for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { + if (slots->frame_info[i].ref_count == 0) { + new_slot_idx = i; + break; + } + } + + if (new_slot_idx != AV1_INVALID_IDX) { + slots->frame_info[new_slot_idx].ref_count++; + slots->timestamp[new_slot_idx] = vsi->frame.cur_ts; + } + + return new_slot_idx; +} + +static inline void vdec_av1_slice_clear_fb(struct vdec_av1_slice_frame_info *frame_info) +{ + memset((void *)frame_info, 0, sizeof(struct vdec_av1_slice_frame_info)); +} + +static void vdec_av1_slice_decrease_ref_count(struct vdec_av1_slice_slot *slots, int fb_idx) +{ + struct vdec_av1_slice_frame_info *frame_info = slots->frame_info; + + frame_info[fb_idx].ref_count--; + if (frame_info[fb_idx].ref_count < 0) { + frame_info[fb_idx].ref_count = 0; + mtk_v4l2_err("av1_error: %s() fb_idx %d decrease ref_count error\n", + __func__, fb_idx); + } + + vdec_av1_slice_clear_fb(&frame_info[fb_idx]); +} + +static void vdec_av1_slice_cleanup_slots(struct vdec_av1_slice_slot *slots, + struct vdec_av1_slice_frame *frame, + struct v4l2_ctrl_av1_frame *ctrl_fh) +{ + int slot_id, ref_id; + + for (ref_id = 0; ref_id < V4L2_AV1_TOTAL_REFS_PER_FRAME; ref_id++) + frame->ref_frame_map[ref_id] = AV1_INVALID_IDX; + + for (slot_id = 0; slot_id < AV1_MAX_FRAME_BUF_COUNT; slot_id++) { + u64 timestamp = slots->timestamp[slot_id]; + bool ref_used = false; + + /* ignored unused slots */ + if (slots->frame_info[slot_id].ref_count == 0) + continue; + + for (ref_id = 0; ref_id < V4L2_AV1_TOTAL_REFS_PER_FRAME; ref_id++) { + if (ctrl_fh->reference_frame_ts[ref_id] == timestamp) { + frame->ref_frame_map[ref_id] = slot_id; + ref_used = true; + } + } + + if (!ref_used) + vdec_av1_slice_decrease_ref_count(slots, slot_id); + } +} + +static void vdec_av1_slice_setup_slot(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_vsi *vsi, + struct v4l2_ctrl_av1_frame *ctrl_fh) +{ + struct vdec_av1_slice_frame_info *cur_frame_info; + struct vdec_av1_slice_uncompressed_header *uh = &vsi->frame.uh; + int ref_id; + + memcpy(&vsi->slots, &instance->slots, sizeof(instance->slots)); + vdec_av1_slice_cleanup_slots(&vsi->slots, &vsi->frame, ctrl_fh); + vsi->slot_id = vdec_av1_slice_get_new_slot(vsi); + + if (vsi->slot_id == AV1_INVALID_IDX) { + mtk_v4l2_err("warning:av1 get invalid index slot\n"); + vsi->slot_id = 0; + } + cur_frame_info = &vsi->slots.frame_info[vsi->slot_id]; + cur_frame_info->frame_type = uh->frame_type; + cur_frame_info->frame_is_intra = ((uh->frame_type == AV1_INTRA_ONLY_FRAME) || + (uh->frame_type == AV1_KEY_FRAME)); + cur_frame_info->order_hint = uh->order_hint; + cur_frame_info->upscaled_width = uh->upscaled_width; + cur_frame_info->pic_pitch = 0; + cur_frame_info->frame_width = uh->frame_width; + cur_frame_info->frame_height = uh->frame_height; + cur_frame_info->mi_cols = ((uh->frame_width + 7) >> 3) << 1; + cur_frame_info->mi_rows = ((uh->frame_height + 7) >> 3) << 1; + + /* ensure current frame is properly mapped if referenced */ + for (ref_id = 0; ref_id < V4L2_AV1_TOTAL_REFS_PER_FRAME; ref_id++) { + u64 timestamp = vsi->slots.timestamp[vsi->slot_id]; + + if (ctrl_fh->reference_frame_ts[ref_id] == timestamp) + vsi->frame.ref_frame_map[ref_id] = vsi->slot_id; + } +} + +static int vdec_av1_slice_alloc_working_buffer(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_vsi *vsi) +{ + struct mtk_vcodec_ctx *ctx = instance->ctx; + enum vdec_av1_slice_resolution_level level; + u32 max_sb_w, max_sb_h, max_w, max_h, w, h; + int i, ret; + + w = vsi->frame.uh.frame_width; + h = vsi->frame.uh.frame_height; + + if (w > VCODEC_DEC_4K_CODED_WIDTH || h > VCODEC_DEC_4K_CODED_HEIGHT) + /* 8K */ + return -EINVAL; + + if (w > MTK_VDEC_MAX_W || h > MTK_VDEC_MAX_H) { + /* 4K */ + level = AV1_RES_4K; + max_w = VCODEC_DEC_4K_CODED_WIDTH; + max_h = VCODEC_DEC_4K_CODED_HEIGHT; + } else { + /* FHD */ + level = AV1_RES_FHD; + max_w = MTK_VDEC_MAX_W; + max_h = MTK_VDEC_MAX_H; + } + + if (level == instance->level) + return 0; + + mtk_vcodec_debug(instance, "resolution level changed from %u to %u, %ux%u", + instance->level, level, w, h); + + max_sb_w = DIV_ROUND_UP(max_w, 128); + max_sb_h = DIV_ROUND_UP(max_h, 128); + + for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { + if (instance->mv[i].va) + mtk_vcodec_mem_free(ctx, &instance->mv[i]); + instance->mv[i].size = max_sb_w * max_sb_h * SZ_1K; + ret = mtk_vcodec_mem_alloc(ctx, &instance->mv[i]); + if (ret) + goto err; + + if (instance->seg[i].va) + mtk_vcodec_mem_free(ctx, &instance->seg[i]); + instance->seg[i].size = max_sb_w * max_sb_h * 512; + ret = mtk_vcodec_mem_alloc(ctx, &instance->seg[i]); + if (ret) + goto err; + + if (instance->cdf[i].va) + mtk_vcodec_mem_free(ctx, &instance->cdf[i]); + instance->cdf[i].size = AV1_CDF_TABLE_BUFFER_SIZE; + ret = mtk_vcodec_mem_alloc(ctx, &instance->cdf[i]); + if (ret) + goto err; + } + + if (!instance->cdf_temp.va) { + instance->cdf_temp.size = (SZ_1K * 16 * 100); + ret = mtk_vcodec_mem_alloc(ctx, &instance->cdf_temp); + if (ret) + goto err; + vsi->cdf_tmp.buf = instance->cdf_temp.dma_addr; + vsi->cdf_tmp.size = instance->cdf_temp.size; + } + + if (instance->tile.va) + mtk_vcodec_mem_free(ctx, &instance->tile); + + instance->tile.size = AV1_TILE_BUF_SIZE * V4L2_AV1_MAX_TILE_COUNT; + ret = mtk_vcodec_mem_alloc(ctx, &instance->tile); + if (ret) + goto err; + + instance->level = level; + return 0; + +err: + instance->level = AV1_RES_NONE; + return ret; +} + +static void vdec_av1_slice_free_working_buffer(struct vdec_av1_slice_instance *instance) +{ + struct mtk_vcodec_ctx *ctx = instance->ctx; + int i; + + for (i = 0; i < ARRAY_SIZE(instance->mv); i++) + mtk_vcodec_mem_free(ctx, &instance->mv[i]); + + for (i = 0; i < ARRAY_SIZE(instance->seg); i++) + mtk_vcodec_mem_free(ctx, &instance->seg[i]); + + for (i = 0; i < ARRAY_SIZE(instance->cdf); i++) + mtk_vcodec_mem_free(ctx, &instance->cdf[i]); + + mtk_vcodec_mem_free(ctx, &instance->tile); + mtk_vcodec_mem_free(ctx, &instance->cdf_temp); + mtk_vcodec_mem_free(ctx, &instance->cdf_table); + mtk_vcodec_mem_free(ctx, &instance->iq_table); + + instance->level = AV1_RES_NONE; +} + +static inline void vdec_av1_slice_vsi_from_remote(struct vdec_av1_slice_vsi *vsi, + struct vdec_av1_slice_vsi *remote_vsi) +{ + memcpy(&vsi->trans, &remote_vsi->trans, sizeof(vsi->trans)); + memcpy(&vsi->state, &remote_vsi->state, sizeof(vsi->state)); +} + +static inline void vdec_av1_slice_vsi_to_remote(struct vdec_av1_slice_vsi *vsi, + struct vdec_av1_slice_vsi *remote_vsi) +{ + memcpy(remote_vsi, vsi, sizeof(*vsi)); +} + +static int vdec_av1_slice_setup_lat_from_src_buf(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_vsi *vsi, + struct vdec_lat_buf *lat_buf) +{ + struct vb2_v4l2_buffer *src; + struct vb2_v4l2_buffer *dst; + + src = v4l2_m2m_next_src_buf(instance->ctx->m2m_ctx); + if (!src) + return -EINVAL; + + lat_buf->src_buf_req = src->vb2_buf.req_obj.req; + dst = &lat_buf->ts_info; + v4l2_m2m_buf_copy_metadata(src, dst, true); + vsi->frame.cur_ts = dst->vb2_buf.timestamp; + + return 0; +} + +static short vdec_av1_slice_resolve_divisor_32(u32 D, short *shift) +{ + int f; + int e; + + *shift = vdec_av1_slice_get_msb(D); + /* e is obtained from D after resetting the most significant 1 bit. */ + e = D - ((u32)1 << *shift); + /* Get the most significant DIV_LUT_BITS (8) bits of e into f */ + if (*shift > DIV_LUT_BITS) + f = AV1_DIV_ROUND_UP_POW2(e, *shift - DIV_LUT_BITS); + else + f = e << (DIV_LUT_BITS - *shift); + if (f > DIV_LUT_NUM) + return -1; + *shift += DIV_LUT_PREC_BITS; + /* Use f as lookup into the precomputed table of multipliers */ + return div_lut[f]; +} + +static void vdec_av1_slice_get_shear_params(struct vdec_av1_slice_gm *gm_params) +{ + const int *mat = gm_params->wmmat; + short shift; + short y; + long long gv, dv; + + if (gm_params->wmmat[2] <= 0) + return; + + gm_params->alpha = clamp_val(mat[2] - (1 << WARPEDMODEL_PREC_BITS), S16_MIN, S16_MAX); + gm_params->beta = clamp_val(mat[3], S16_MIN, S16_MAX); + + y = vdec_av1_slice_resolve_divisor_32(abs(mat[2]), &shift) * (mat[2] < 0 ? -1 : 1); + + gv = ((long long)mat[4] * (1 << WARPEDMODEL_PREC_BITS)) * y; + gm_params->gamma = clamp_val((int)AV1_DIV_ROUND_UP_POW2_SIGNED(gv, shift), + S16_MIN, S16_MAX); + + dv = ((long long)mat[3] * mat[4]) * y; + gm_params->delta = clamp_val(mat[5] - (int)AV1_DIV_ROUND_UP_POW2_SIGNED(dv, shift) - + (1 << WARPEDMODEL_PREC_BITS), S16_MIN, S16_MAX); + + gm_params->alpha = AV1_DIV_ROUND_UP_POW2_SIGNED(gm_params->alpha, WARP_PARAM_REDUCE_BITS) * + (1 << WARP_PARAM_REDUCE_BITS); + gm_params->beta = AV1_DIV_ROUND_UP_POW2_SIGNED(gm_params->beta, WARP_PARAM_REDUCE_BITS) * + (1 << WARP_PARAM_REDUCE_BITS); + gm_params->gamma = AV1_DIV_ROUND_UP_POW2_SIGNED(gm_params->gamma, WARP_PARAM_REDUCE_BITS) * + (1 << WARP_PARAM_REDUCE_BITS); + gm_params->delta = AV1_DIV_ROUND_UP_POW2_SIGNED(gm_params->delta, WARP_PARAM_REDUCE_BITS) * + (1 << WARP_PARAM_REDUCE_BITS); +} + +static void vdec_av1_slice_setup_gm(struct vdec_av1_slice_gm *gm, + struct v4l2_av1_global_motion *ctrl_gm) +{ + u32 i, j; + + for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) { + gm[i].wmtype = ctrl_gm->type[i]; + for (j = 0; j < 6; j++) + gm[i].wmmat[j] = ctrl_gm->params[i][j]; + + gm[i].invalid = !!(ctrl_gm->invalid & BIT(i)); + gm[i].alpha = 0; + gm[i].beta = 0; + gm[i].gamma = 0; + gm[i].delta = 0; + if (gm[i].wmtype <= V4L2_AV1_WARP_MODEL_AFFINE) + vdec_av1_slice_get_shear_params(&gm[i]); + } +} + +static void vdec_av1_slice_setup_seg(struct vdec_av1_slice_seg *seg, + struct v4l2_av1_segmentation *ctrl_seg) +{ + u32 i, j; + + seg->segmentation_enabled = SEGMENTATION_FLAG(ctrl_seg, ENABLED); + seg->segmentation_update_map = SEGMENTATION_FLAG(ctrl_seg, UPDATE_MAP); + seg->segmentation_temporal_update = SEGMENTATION_FLAG(ctrl_seg, TEMPORAL_UPDATE); + seg->segmentation_update_data = SEGMENTATION_FLAG(ctrl_seg, UPDATE_DATA); + seg->segid_preskip = SEGMENTATION_FLAG(ctrl_seg, SEG_ID_PRE_SKIP); + seg->last_active_segid = ctrl_seg->last_active_seg_id; + + for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) { + seg->feature_enabled_mask[i] = ctrl_seg->feature_enabled[i]; + for (j = 0; j < V4L2_AV1_SEG_LVL_MAX; j++) + seg->feature_data[i][j] = ctrl_seg->feature_data[i][j]; + } +} + +static void vdec_av1_slice_setup_quant(struct vdec_av1_slice_quantization *quant, + struct v4l2_av1_quantization *ctrl_quant) +{ + quant->base_q_idx = ctrl_quant->base_q_idx; + quant->delta_qydc = ctrl_quant->delta_q_y_dc; + quant->delta_qudc = ctrl_quant->delta_q_u_dc; + quant->delta_quac = ctrl_quant->delta_q_u_ac; + quant->delta_qvdc = ctrl_quant->delta_q_v_dc; + quant->delta_qvac = ctrl_quant->delta_q_v_ac; + quant->qm_y = ctrl_quant->qm_y; + quant->qm_u = ctrl_quant->qm_u; + quant->qm_v = ctrl_quant->qm_v; + quant->using_qmatrix = QUANT_FLAG(ctrl_quant, USING_QMATRIX); +} + +static int vdec_av1_slice_get_qindex(struct vdec_av1_slice_uncompressed_header *uh, + int segmentation_id) +{ + struct vdec_av1_slice_seg *seg = &uh->seg; + struct vdec_av1_slice_quantization *quant = &uh->quant; + int data = 0, qindex = 0; + + if (seg->segmentation_enabled && + (seg->feature_enabled_mask[segmentation_id] & BIT(SEG_LVL_ALT_Q))) { + data = seg->feature_data[segmentation_id][SEG_LVL_ALT_Q]; + qindex = quant->base_q_idx + data; + return clamp_val(qindex, 0, MAXQ); + } + + return quant->base_q_idx; +} + +static void vdec_av1_slice_setup_lr(struct vdec_av1_slice_lr *lr, + struct v4l2_av1_loop_restoration *ctrl_lr) +{ + int i; + + lr->use_lr = 0; + lr->use_chroma_lr = 0; + for (i = 0; i < V4L2_AV1_NUM_PLANES_MAX; i++) { + lr->frame_restoration_type[i] = ctrl_lr->frame_restoration_type[i]; + lr->loop_restoration_size[i] = ctrl_lr->loop_restoration_size[i]; + if (lr->frame_restoration_type[i]) { + lr->use_lr = 1; + if (i > 0) + lr->use_chroma_lr = 1; + } + } +} + +static void vdec_av1_slice_setup_lf(struct vdec_av1_slice_loop_filter *lf, + struct v4l2_av1_loop_filter *ctrl_lf) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lf->loop_filter_level); i++) + lf->loop_filter_level[i] = ctrl_lf->level[i]; + + for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) + lf->loop_filter_ref_deltas[i] = ctrl_lf->ref_deltas[i]; + + for (i = 0; i < ARRAY_SIZE(lf->loop_filter_mode_deltas); i++) + lf->loop_filter_mode_deltas[i] = ctrl_lf->mode_deltas[i]; + + lf->loop_filter_sharpness = ctrl_lf->sharpness; + lf->loop_filter_delta_enabled = + BIT_FLAG(ctrl_lf, V4L2_AV1_LOOP_FILTER_FLAG_DELTA_ENABLED); +} + +static void vdec_av1_slice_setup_cdef(struct vdec_av1_slice_cdef *cdef, + struct v4l2_av1_cdef *ctrl_cdef) +{ + int i; + + cdef->cdef_damping = ctrl_cdef->damping_minus_3 + 3; + cdef->cdef_bits = ctrl_cdef->bits; + + for (i = 0; i < V4L2_AV1_CDEF_MAX; i++) { + if (ctrl_cdef->y_sec_strength[i] == 4) + ctrl_cdef->y_sec_strength[i] -= 1; + + if (ctrl_cdef->uv_sec_strength[i] == 4) + ctrl_cdef->uv_sec_strength[i] -= 1; + + cdef->cdef_y_strength[i] = + ctrl_cdef->y_pri_strength[i] << SECONDARY_FILTER_STRENGTH_NUM_BITS | + ctrl_cdef->y_sec_strength[i]; + cdef->cdef_uv_strength[i] = + ctrl_cdef->uv_pri_strength[i] << SECONDARY_FILTER_STRENGTH_NUM_BITS | + ctrl_cdef->uv_sec_strength[i]; + } +} + +static void vdec_av1_slice_setup_seq(struct vdec_av1_slice_seq_header *seq, + struct v4l2_ctrl_av1_sequence *ctrl_seq) +{ + seq->bitdepth = ctrl_seq->bit_depth; + seq->max_frame_width = ctrl_seq->max_frame_width_minus_1 + 1; + seq->max_frame_height = ctrl_seq->max_frame_height_minus_1 + 1; + seq->enable_superres = SEQUENCE_FLAG(ctrl_seq, ENABLE_SUPERRES); + seq->enable_filter_intra = SEQUENCE_FLAG(ctrl_seq, ENABLE_FILTER_INTRA); + seq->enable_intra_edge_filter = SEQUENCE_FLAG(ctrl_seq, ENABLE_INTRA_EDGE_FILTER); + seq->enable_interintra_compound = SEQUENCE_FLAG(ctrl_seq, ENABLE_INTERINTRA_COMPOUND); + seq->enable_masked_compound = SEQUENCE_FLAG(ctrl_seq, ENABLE_MASKED_COMPOUND); + seq->enable_dual_filter = SEQUENCE_FLAG(ctrl_seq, ENABLE_DUAL_FILTER); + seq->enable_jnt_comp = SEQUENCE_FLAG(ctrl_seq, ENABLE_JNT_COMP); + seq->mono_chrome = SEQUENCE_FLAG(ctrl_seq, MONO_CHROME); + seq->enable_order_hint = SEQUENCE_FLAG(ctrl_seq, ENABLE_ORDER_HINT); + seq->order_hint_bits = ctrl_seq->order_hint_bits; + seq->use_128x128_superblock = SEQUENCE_FLAG(ctrl_seq, USE_128X128_SUPERBLOCK); + seq->subsampling_x = SEQUENCE_FLAG(ctrl_seq, SUBSAMPLING_X); + seq->subsampling_y = SEQUENCE_FLAG(ctrl_seq, SUBSAMPLING_Y); +} + +static void vdec_av1_slice_setup_tile(struct vdec_av1_slice_frame *frame, + struct v4l2_av1_tile_info *ctrl_tile) +{ + struct vdec_av1_slice_seq_header *seq = &frame->seq; + struct vdec_av1_slice_tile *tile = &frame->uh.tile; + u32 mib_size_log2 = seq->use_128x128_superblock ? 5 : 4; + int i; + + tile->tile_cols = ctrl_tile->tile_cols; + tile->tile_rows = ctrl_tile->tile_rows; + tile->context_update_tile_id = ctrl_tile->context_update_tile_id; + tile->uniform_tile_spacing_flag = + BIT_FLAG(ctrl_tile, V4L2_AV1_TILE_INFO_FLAG_UNIFORM_TILE_SPACING); + + for (i = 0; i < tile->tile_cols + 1; i++) + tile->mi_col_starts[i] = + ALIGN(ctrl_tile->mi_col_starts[i], BIT(mib_size_log2)) >> mib_size_log2; + + for (i = 0; i < tile->tile_rows + 1; i++) + tile->mi_row_starts[i] = + ALIGN(ctrl_tile->mi_row_starts[i], BIT(mib_size_log2)) >> mib_size_log2; +} + +static void vdec_av1_slice_setup_uh(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_frame *frame, + struct v4l2_ctrl_av1_frame *ctrl_fh) +{ + struct vdec_av1_slice_uncompressed_header *uh = &frame->uh; + int i; + + uh->use_ref_frame_mvs = FH_FLAG(ctrl_fh, USE_REF_FRAME_MVS); + uh->order_hint = ctrl_fh->order_hint; + vdec_av1_slice_setup_gm(uh->gm, &ctrl_fh->global_motion); + uh->upscaled_width = ctrl_fh->upscaled_width; + uh->frame_width = ctrl_fh->frame_width_minus_1 + 1; + uh->frame_height = ctrl_fh->frame_height_minus_1 + 1; + uh->mi_cols = ((uh->frame_width + 7) >> 3) << 1; + uh->mi_rows = ((uh->frame_height + 7) >> 3) << 1; + uh->reduced_tx_set = FH_FLAG(ctrl_fh, REDUCED_TX_SET); + uh->tx_mode = ctrl_fh->tx_mode; + uh->uniform_tile_spacing_flag = + BIT_FLAG(&ctrl_fh->tile_info, V4L2_AV1_TILE_INFO_FLAG_UNIFORM_TILE_SPACING); + uh->interpolation_filter = ctrl_fh->interpolation_filter; + uh->allow_warped_motion = FH_FLAG(ctrl_fh, ALLOW_WARPED_MOTION); + uh->is_motion_mode_switchable = FH_FLAG(ctrl_fh, IS_MOTION_MODE_SWITCHABLE); + uh->frame_type = ctrl_fh->frame_type; + uh->frame_is_intra = (uh->frame_type == V4L2_AV1_INTRA_ONLY_FRAME || + uh->frame_type == V4L2_AV1_KEY_FRAME); + + if (!uh->frame_is_intra && FH_FLAG(ctrl_fh, REFERENCE_SELECT)) + uh->reference_mode = AV1_REFERENCE_MODE_SELECT; + else + uh->reference_mode = AV1_SINGLE_REFERENCE; + + uh->allow_high_precision_mv = FH_FLAG(ctrl_fh, ALLOW_HIGH_PRECISION_MV); + uh->allow_intra_bc = FH_FLAG(ctrl_fh, ALLOW_INTRABC); + uh->force_integer_mv = FH_FLAG(ctrl_fh, FORCE_INTEGER_MV); + uh->allow_screen_content_tools = FH_FLAG(ctrl_fh, ALLOW_SCREEN_CONTENT_TOOLS); + uh->error_resilient_mode = FH_FLAG(ctrl_fh, ERROR_RESILIENT_MODE); + uh->primary_ref_frame = ctrl_fh->primary_ref_frame; + uh->disable_frame_end_update_cdf = + FH_FLAG(ctrl_fh, DISABLE_FRAME_END_UPDATE_CDF); + uh->disable_cdf_update = FH_FLAG(ctrl_fh, DISABLE_CDF_UPDATE); + uh->skip_mode.skip_mode_present = FH_FLAG(ctrl_fh, SKIP_MODE_PRESENT); + uh->skip_mode.skip_mode_frame[0] = + ctrl_fh->skip_mode_frame[0] - V4L2_AV1_REF_LAST_FRAME; + uh->skip_mode.skip_mode_frame[1] = + ctrl_fh->skip_mode_frame[1] - V4L2_AV1_REF_LAST_FRAME; + uh->skip_mode.skip_mode_allowed = ctrl_fh->skip_mode_frame[0] ? 1 : 0; + + vdec_av1_slice_setup_seg(&uh->seg, &ctrl_fh->segmentation); + uh->delta_q_lf.delta_q_present = QUANT_FLAG(&ctrl_fh->quantization, DELTA_Q_PRESENT); + uh->delta_q_lf.delta_q_res = 1 << ctrl_fh->quantization.delta_q_res; + uh->delta_q_lf.delta_lf_present = + BIT_FLAG(&ctrl_fh->loop_filter, V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_PRESENT); + uh->delta_q_lf.delta_lf_res = ctrl_fh->loop_filter.delta_lf_res; + uh->delta_q_lf.delta_lf_multi = + BIT_FLAG(&ctrl_fh->loop_filter, V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_MULTI); + vdec_av1_slice_setup_quant(&uh->quant, &ctrl_fh->quantization); + + uh->coded_loss_less = 1; + for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) { + uh->quant.qindex[i] = vdec_av1_slice_get_qindex(uh, i); + uh->loss_less_array[i] = + (uh->quant.qindex[i] == 0 && uh->quant.delta_qydc == 0 && + uh->quant.delta_quac == 0 && uh->quant.delta_qudc == 0 && + uh->quant.delta_qvac == 0 && uh->quant.delta_qvdc == 0); + + if (!uh->loss_less_array[i]) + uh->coded_loss_less = 0; + } + + vdec_av1_slice_setup_lr(&uh->lr, &ctrl_fh->loop_restoration); + uh->superres_denom = ctrl_fh->superres_denom; + vdec_av1_slice_setup_lf(&uh->loop_filter, &ctrl_fh->loop_filter); + vdec_av1_slice_setup_cdef(&uh->cdef, &ctrl_fh->cdef); + vdec_av1_slice_setup_tile(frame, &ctrl_fh->tile_info); +} + +static int vdec_av1_slice_setup_tile_group(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_vsi *vsi) +{ + struct v4l2_ctrl_av1_tile_group_entry *ctrl_tge; + struct vdec_av1_slice_tile_group *tile_group = &instance->tile_group; + struct vdec_av1_slice_uncompressed_header *uh = &vsi->frame.uh; + struct vdec_av1_slice_tile *tile = &uh->tile; + struct v4l2_ctrl *ctrl; + u32 tge_size; + int i; + + ctrl = v4l2_ctrl_find(&instance->ctx->ctrl_hdl, V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY); + if (!ctrl) + return -EINVAL; + + tge_size = ctrl->elems; + ctrl_tge = (struct v4l2_ctrl_av1_tile_group_entry *)ctrl->p_cur.p; + + tile_group->num_tiles = tile->tile_cols * tile->tile_rows; + + if (tile_group->num_tiles != tge_size || + tile_group->num_tiles > V4L2_AV1_MAX_TILE_COUNT) { + mtk_vcodec_err(instance, "invalid tge_size %d, tile_num:%d\n", + tge_size, tile_group->num_tiles); + return -EINVAL; + } + + for (i = 0; i < tge_size; i++) { + if (i != ctrl_tge[i].tile_row * vsi->frame.uh.tile.tile_cols + + ctrl_tge[i].tile_col) { + mtk_vcodec_err(instance, "invalid tge info %d, %d %d %d\n", + i, ctrl_tge[i].tile_row, ctrl_tge[i].tile_col, + vsi->frame.uh.tile.tile_rows); + return -EINVAL; + } + tile_group->tile_size[i] = ctrl_tge[i].tile_size; + tile_group->tile_start_offset[i] = ctrl_tge[i].tile_offset; + } + + return 0; +} + +static inline void vdec_av1_slice_setup_state(struct vdec_av1_slice_vsi *vsi) +{ + memset(&vsi->state, 0, sizeof(vsi->state)); +} + +static void vdec_av1_slice_setup_scale_factors(struct vdec_av1_slice_frame_refs *frame_ref, + struct vdec_av1_slice_frame_info *ref_frame_info, + struct vdec_av1_slice_uncompressed_header *uh) +{ + struct vdec_av1_slice_scale_factors *scale_factors = &frame_ref->scale_factors; + u32 ref_upscaled_width = ref_frame_info->upscaled_width; + u32 ref_frame_height = ref_frame_info->frame_height; + u32 frame_width = uh->frame_width; + u32 frame_height = uh->frame_height; + + if (!vdec_av1_slice_need_scale(ref_upscaled_width, ref_frame_height, + frame_width, frame_height)) { + scale_factors->x_scale = -1; + scale_factors->y_scale = -1; + scale_factors->is_scaled = 0; + return; + } + + scale_factors->x_scale = + ((ref_upscaled_width << AV1_REF_SCALE_SHIFT) + (frame_width >> 1)) / frame_width; + scale_factors->y_scale = + ((ref_frame_height << AV1_REF_SCALE_SHIFT) + (frame_height >> 1)) / frame_height; + scale_factors->is_scaled = + (scale_factors->x_scale != AV1_REF_INVALID_SCALE) && + (scale_factors->y_scale != AV1_REF_INVALID_SCALE) && + (scale_factors->x_scale != AV1_REF_NO_SCALE || + scale_factors->y_scale != AV1_REF_NO_SCALE); + scale_factors->x_step = + AV1_DIV_ROUND_UP_POW2(scale_factors->x_scale, + AV1_REF_SCALE_SHIFT - AV1_SCALE_SUBPEL_BITS); + scale_factors->y_step = + AV1_DIV_ROUND_UP_POW2(scale_factors->y_scale, + AV1_REF_SCALE_SHIFT - AV1_SCALE_SUBPEL_BITS); +} + +static unsigned char vdec_av1_slice_get_sign_bias(int a, + int b, + u8 enable_order_hint, + u8 order_hint_bits) +{ + int diff = 0; + int m = 0; + unsigned char result = 0; + + if (!enable_order_hint) + return 0; + + diff = a - b; + m = 1 << (order_hint_bits - 1); + diff = (diff & (m - 1)) - (diff & m); + + if (diff > 0) + result = 1; + + return result; +} + +static void vdec_av1_slice_setup_ref(struct vdec_av1_slice_pfc *pfc, + struct v4l2_ctrl_av1_frame *ctrl_fh) +{ + struct vdec_av1_slice_vsi *vsi = &pfc->vsi; + struct vdec_av1_slice_frame *frame = &vsi->frame; + struct vdec_av1_slice_slot *slots = &vsi->slots; + struct vdec_av1_slice_uncompressed_header *uh = &frame->uh; + struct vdec_av1_slice_seq_header *seq = &frame->seq; + struct vdec_av1_slice_frame_info *cur_frame_info = + &slots->frame_info[vsi->slot_id]; + struct vdec_av1_slice_frame_info *frame_info; + int i, slot_id; + + if (uh->frame_is_intra) + return; + + for (i = 0; i < V4L2_AV1_REFS_PER_FRAME; i++) { + int ref_idx = ctrl_fh->ref_frame_idx[i]; + + pfc->ref_idx[i] = ctrl_fh->reference_frame_ts[ref_idx]; + slot_id = frame->ref_frame_map[ref_idx]; + frame_info = &slots->frame_info[slot_id]; + if (slot_id == AV1_INVALID_IDX) { + mtk_v4l2_err("cannot match reference[%d] 0x%llx\n", i, + ctrl_fh->reference_frame_ts[ref_idx]); + frame->order_hints[i] = 0; + frame->ref_frame_valid[i] = 0; + continue; + } + + frame->frame_refs[i].ref_fb_idx = slot_id; + vdec_av1_slice_setup_scale_factors(&frame->frame_refs[i], + frame_info, uh); + if (!seq->enable_order_hint) + frame->ref_frame_sign_bias[i + 1] = 0; + else + frame->ref_frame_sign_bias[i + 1] = + vdec_av1_slice_get_sign_bias(frame_info->order_hint, + uh->order_hint, + seq->enable_order_hint, + seq->order_hint_bits); + + frame->order_hints[i] = ctrl_fh->order_hints[i + 1]; + cur_frame_info->order_hints[i] = frame->order_hints[i]; + frame->ref_frame_valid[i] = 1; + } +} + +static void vdec_av1_slice_get_previous(struct vdec_av1_slice_vsi *vsi) +{ + struct vdec_av1_slice_frame *frame = &vsi->frame; + + if (frame->uh.primary_ref_frame == AV1_PRIMARY_REF_NONE) + frame->prev_fb_idx = AV1_INVALID_IDX; + else + frame->prev_fb_idx = frame->frame_refs[frame->uh.primary_ref_frame].ref_fb_idx; +} + +static inline void vdec_av1_slice_setup_operating_mode(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_frame *frame) +{ + frame->large_scale_tile = 0; +} + +static int vdec_av1_slice_setup_pfc(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_pfc *pfc) +{ + struct v4l2_ctrl_av1_frame *ctrl_fh; + struct v4l2_ctrl_av1_sequence *ctrl_seq; + struct vdec_av1_slice_vsi *vsi = &pfc->vsi; + int ret = 0; + + /* frame header */ + ctrl_fh = (struct v4l2_ctrl_av1_frame *) + vdec_av1_get_ctrl_ptr(instance->ctx, + V4L2_CID_STATELESS_AV1_FRAME); + if (IS_ERR(ctrl_fh)) + return PTR_ERR(ctrl_fh); + + ctrl_seq = (struct v4l2_ctrl_av1_sequence *) + vdec_av1_get_ctrl_ptr(instance->ctx, + V4L2_CID_STATELESS_AV1_SEQUENCE); + if (IS_ERR(ctrl_seq)) + return PTR_ERR(ctrl_seq); + + /* setup vsi information */ + vdec_av1_slice_setup_seq(&vsi->frame.seq, ctrl_seq); + vdec_av1_slice_setup_uh(instance, &vsi->frame, ctrl_fh); + vdec_av1_slice_setup_operating_mode(instance, &vsi->frame); + + vdec_av1_slice_setup_state(vsi); + vdec_av1_slice_setup_slot(instance, vsi, ctrl_fh); + vdec_av1_slice_setup_ref(pfc, ctrl_fh); + vdec_av1_slice_get_previous(vsi); + + pfc->seq = instance->seq; + instance->seq++; + + return ret; +} + +static void vdec_av1_slice_setup_lat_buffer(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_vsi *vsi, + struct mtk_vcodec_mem *bs, + struct vdec_lat_buf *lat_buf) +{ + struct vdec_av1_slice_work_buffer *work_buffer; + int i; + + vsi->bs.dma_addr = bs->dma_addr; + vsi->bs.size = bs->size; + + vsi->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + vsi->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size; + vsi->trans.dma_addr = lat_buf->ctx->msg_queue.wdma_wptr_addr; + /* used to store trans end */ + vsi->trans.dma_addr_end = lat_buf->ctx->msg_queue.wdma_rptr_addr; + vsi->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr; + vsi->err_map.size = lat_buf->wdma_err_addr.size; + vsi->rd_mv.dma_addr = lat_buf->rd_mv_addr.dma_addr; + vsi->rd_mv.size = lat_buf->rd_mv_addr.size; + + vsi->row_info.buf = 0; + vsi->row_info.size = 0; + + work_buffer = vsi->work_buffer; + + for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { + work_buffer[i].mv_addr.buf = instance->mv[i].dma_addr; + work_buffer[i].mv_addr.size = instance->mv[i].size; + work_buffer[i].segid_addr.buf = instance->seg[i].dma_addr; + work_buffer[i].segid_addr.size = instance->seg[i].size; + work_buffer[i].cdf_addr.buf = instance->cdf[i].dma_addr; + work_buffer[i].cdf_addr.size = instance->cdf[i].size; + } + + vsi->cdf_tmp.buf = instance->cdf_temp.dma_addr; + vsi->cdf_tmp.size = instance->cdf_temp.size; + + vsi->tile.buf = instance->tile.dma_addr; + vsi->tile.size = instance->tile.size; + memcpy(lat_buf->tile_addr.va, instance->tile.va, 64 * instance->tile_group.num_tiles); + + vsi->cdf_table.buf = instance->cdf_table.dma_addr; + vsi->cdf_table.size = instance->cdf_table.size; + vsi->iq_table.buf = instance->iq_table.dma_addr; + vsi->iq_table.size = instance->iq_table.size; +} + +static void vdec_av1_slice_setup_seg_buffer(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_vsi *vsi) +{ + struct vdec_av1_slice_uncompressed_header *uh = &vsi->frame.uh; + struct mtk_vcodec_mem *buf; + + /* reset segment buffer */ + if (uh->primary_ref_frame == AV1_PRIMARY_REF_NONE || !uh->seg.segmentation_enabled) { + mtk_vcodec_debug(instance, "reset seg %d\n", vsi->slot_id); + if (vsi->slot_id != AV1_INVALID_IDX) { + buf = &instance->seg[vsi->slot_id]; + memset(buf->va, 0, buf->size); + } + } +} + +static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_vsi *vsi, + struct mtk_vcodec_mem *bs) +{ + struct vdec_av1_slice_tile_group *tile_group = &instance->tile_group; + struct vdec_av1_slice_uncompressed_header *uh = &vsi->frame.uh; + struct vdec_av1_slice_tile *tile = &uh->tile; + u32 tile_num, tile_row, tile_col; + u32 allow_update_cdf = 0; + u32 sb_boundary_x_m1 = 0, sb_boundary_y_m1 = 0; + int tile_info_base; + u32 tile_buf_pa; + u32 *tile_info_buf = instance->tile.va; + u32 pa = (u32)bs->dma_addr; + + if (uh->disable_cdf_update == 0) + allow_update_cdf = 1; + + for (tile_num = 0; tile_num < tile_group->num_tiles; tile_num++) { + /* each uint32 takes place of 4 bytes */ + tile_info_base = (AV1_TILE_BUF_SIZE * tile_num) >> 2; + tile_row = tile_num / tile->tile_cols; + tile_col = tile_num % tile->tile_cols; + tile_info_buf[tile_info_base + 0] = (tile_group->tile_size[tile_num] << 3); + tile_buf_pa = pa + tile_group->tile_start_offset[tile_num]; + + tile_info_buf[tile_info_base + 1] = (tile_buf_pa >> 4) << 4; + tile_info_buf[tile_info_base + 2] = (tile_buf_pa % 16) << 3; + + sb_boundary_x_m1 = + (tile->mi_col_starts[tile_col + 1] - tile->mi_col_starts[tile_col] - 1) & + 0x3f; + sb_boundary_y_m1 = + (tile->mi_row_starts[tile_row + 1] - tile->mi_row_starts[tile_row] - 1) & + 0x1ff; + + tile_info_buf[tile_info_base + 3] = (sb_boundary_y_m1 << 7) | sb_boundary_x_m1; + tile_info_buf[tile_info_base + 4] = ((allow_update_cdf << 18) | (1 << 16)); + + if (tile_num == tile->context_update_tile_id && + uh->disable_frame_end_update_cdf == 0) + tile_info_buf[tile_info_base + 4] |= (1 << 17); + + mtk_vcodec_debug(instance, "// tile buf %d pos(%dx%d) offset 0x%x\n", + tile_num, tile_row, tile_col, tile_info_base); + mtk_vcodec_debug(instance, "// %08x %08x %08x %08x\n", + tile_info_buf[tile_info_base + 0], + tile_info_buf[tile_info_base + 1], + tile_info_buf[tile_info_base + 2], + tile_info_buf[tile_info_base + 3]); + mtk_vcodec_debug(instance, "// %08x %08x %08x %08x\n", + tile_info_buf[tile_info_base + 4], + tile_info_buf[tile_info_base + 5], + tile_info_buf[tile_info_base + 6], + tile_info_buf[tile_info_base + 7]); + } +} + +static int vdec_av1_slice_setup_lat(struct vdec_av1_slice_instance *instance, + struct mtk_vcodec_mem *bs, + struct vdec_lat_buf *lat_buf, + struct vdec_av1_slice_pfc *pfc) +{ + struct vdec_av1_slice_vsi *vsi = &pfc->vsi; + int ret; + + ret = vdec_av1_slice_setup_lat_from_src_buf(instance, vsi, lat_buf); + if (ret) + return ret; + + ret = vdec_av1_slice_setup_pfc(instance, pfc); + if (ret) + return ret; + + ret = vdec_av1_slice_setup_tile_group(instance, vsi); + if (ret) + return ret; + + ret = vdec_av1_slice_alloc_working_buffer(instance, vsi); + if (ret) + return ret; + + vdec_av1_slice_setup_seg_buffer(instance, vsi); + vdec_av1_slice_setup_tile_buffer(instance, vsi, bs); + vdec_av1_slice_setup_lat_buffer(instance, vsi, bs, lat_buf); + + return 0; +} + +static int vdec_av1_slice_update_lat(struct vdec_av1_slice_instance *instance, + struct vdec_lat_buf *lat_buf, + struct vdec_av1_slice_pfc *pfc) +{ + struct vdec_av1_slice_vsi *vsi; + + vsi = &pfc->vsi; + mtk_vcodec_debug(instance, "frame %u LAT CRC 0x%08x, output size is %d\n", + pfc->seq, vsi->state.crc[0], vsi->state.out_size); + + /* buffer full, need to re-decode */ + if (vsi->state.full) { + /* buffer not enough */ + if (vsi->trans.dma_addr_end - vsi->trans.dma_addr == vsi->ube.size) + return -ENOMEM; + return -EAGAIN; + } + + instance->width = vsi->frame.uh.upscaled_width; + instance->height = vsi->frame.uh.frame_height; + instance->frame_type = vsi->frame.uh.frame_type; + + return 0; +} + +static int vdec_av1_slice_setup_core_to_dst_buf(struct vdec_av1_slice_instance *instance, + struct vdec_lat_buf *lat_buf) +{ + struct vb2_v4l2_buffer *dst; + + dst = v4l2_m2m_next_dst_buf(instance->ctx->m2m_ctx); + if (!dst) + return -EINVAL; + + v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, dst, true); + + return 0; +} + +static int vdec_av1_slice_setup_core_buffer(struct vdec_av1_slice_instance *instance, + struct vdec_av1_slice_pfc *pfc, + struct vdec_av1_slice_vsi *vsi, + struct vdec_fb *fb, + struct vdec_lat_buf *lat_buf) +{ + struct vb2_buffer *vb; + struct vb2_queue *vq; + int w, h, plane, size; + int i; + + plane = instance->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes; + w = vsi->frame.uh.upscaled_width; + h = vsi->frame.uh.frame_height; + size = ALIGN(w, VCODEC_DEC_ALIGNED_64) * ALIGN(h, VCODEC_DEC_ALIGNED_64); + + /* frame buffer */ + vsi->fb.y.dma_addr = fb->base_y.dma_addr; + if (plane == 1) + vsi->fb.c.dma_addr = fb->base_y.dma_addr + size; + else + vsi->fb.c.dma_addr = fb->base_c.dma_addr; + + /* reference buffers */ + vq = v4l2_m2m_get_vq(instance->ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + if (!vq) + return -EINVAL; + + /* get current output buffer */ + vb = &v4l2_m2m_next_dst_buf(instance->ctx->m2m_ctx)->vb2_buf; + if (!vb) + return -EINVAL; + + /* get buffer address from vb2buf */ + for (i = 0; i < V4L2_AV1_REFS_PER_FRAME; i++) { + struct vdec_av1_slice_fb *vref = &vsi->ref[i]; + + vb = vb2_find_buffer(vq, pfc->ref_idx[i]); + if (!vb) { + memset(vref, 0, sizeof(*vref)); + continue; + } + + vref->y.dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); + if (plane == 1) + vref->c.dma_addr = vref->y.dma_addr + size; + else + vref->c.dma_addr = vb2_dma_contig_plane_dma_addr(vb, 1); + } + vsi->tile.dma_addr = lat_buf->tile_addr.dma_addr; + vsi->tile.size = lat_buf->tile_addr.size; + + return 0; +} + +static int vdec_av1_slice_setup_core(struct vdec_av1_slice_instance *instance, + struct vdec_fb *fb, + struct vdec_lat_buf *lat_buf, + struct vdec_av1_slice_pfc *pfc) +{ + struct vdec_av1_slice_vsi *vsi = &pfc->vsi; + int ret; + + ret = vdec_av1_slice_setup_core_to_dst_buf(instance, lat_buf); + if (ret) + return ret; + + ret = vdec_av1_slice_setup_core_buffer(instance, pfc, vsi, fb, lat_buf); + if (ret) + return ret; + + return 0; +} + +static int vdec_av1_slice_update_core(struct vdec_av1_slice_instance *instance, + struct vdec_lat_buf *lat_buf, + struct vdec_av1_slice_pfc *pfc) +{ + struct vdec_av1_slice_vsi *vsi = instance->core_vsi; + + mtk_vcodec_debug(instance, "frame %u Y_CRC %08x %08x %08x %08x\n", + pfc->seq, vsi->state.crc[0], vsi->state.crc[1], + vsi->state.crc[2], vsi->state.crc[3]); + mtk_vcodec_debug(instance, "frame %u C_CRC %08x %08x %08x %08x\n", + pfc->seq, vsi->state.crc[8], vsi->state.crc[9], + vsi->state.crc[10], vsi->state.crc[11]); + + return 0; +} + +static int vdec_av1_slice_init(struct mtk_vcodec_ctx *ctx) +{ + struct vdec_av1_slice_instance *instance; + struct vdec_av1_slice_init_vsi *vsi; + int ret; + + instance = kzalloc(sizeof(*instance), GFP_KERNEL); + if (!instance) + return -ENOMEM; + + instance->ctx = ctx; + instance->vpu.id = SCP_IPI_VDEC_LAT; + instance->vpu.core_id = SCP_IPI_VDEC_CORE; + instance->vpu.ctx = ctx; + instance->vpu.codec_type = ctx->current_codec; + + ret = vpu_dec_init(&instance->vpu); + if (ret) { + mtk_vcodec_err(instance, "failed to init vpu dec, ret %d\n", ret); + goto error_vpu_init; + } + + /* init vsi and global flags */ + vsi = instance->vpu.vsi; + if (!vsi) { + mtk_vcodec_err(instance, "failed to get AV1 vsi\n"); + ret = -EINVAL; + goto error_vsi; + } + instance->init_vsi = vsi; + instance->core_vsi = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, (u32)vsi->core_vsi); + + if (!instance->core_vsi) { + mtk_vcodec_err(instance, "failed to get AV1 core vsi\n"); + ret = -EINVAL; + goto error_vsi; + } + + if (vsi->vsi_size != sizeof(struct vdec_av1_slice_vsi)) + mtk_vcodec_err(instance, "remote vsi size 0x%x mismatch! expected: 0x%zx\n", + vsi->vsi_size, sizeof(struct vdec_av1_slice_vsi)); + + instance->irq_enabled = 1; + instance->inneracing_mode = IS_VDEC_INNER_RACING(instance->ctx->dev->dec_capability); + + mtk_vcodec_debug(instance, "vsi 0x%p core_vsi 0x%llx 0x%p, inneracing_mode %d\n", + vsi, vsi->core_vsi, instance->core_vsi, instance->inneracing_mode); + + ret = vdec_av1_slice_init_cdf_table(instance); + if (ret) + goto error_vsi; + + ret = vdec_av1_slice_init_iq_table(instance); + if (ret) + goto error_vsi; + + ctx->drv_handle = instance; + + return 0; +error_vsi: + vpu_dec_deinit(&instance->vpu); +error_vpu_init: + kfree(instance); + + return ret; +} + +static void vdec_av1_slice_deinit(void *h_vdec) +{ + struct vdec_av1_slice_instance *instance = h_vdec; + + if (!instance) + return; + mtk_vcodec_debug(instance, "h_vdec 0x%p\n", h_vdec); + vpu_dec_deinit(&instance->vpu); + vdec_av1_slice_free_working_buffer(instance); + vdec_msg_queue_deinit(&instance->ctx->msg_queue, instance->ctx); + kfree(instance); +} + +static int vdec_av1_slice_flush(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_av1_slice_instance *instance = h_vdec; + int i; + + mtk_vcodec_debug(instance, "flush ...\n"); + + vdec_msg_queue_wait_lat_buf_full(&instance->ctx->msg_queue); + + for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) + vdec_av1_slice_clear_fb(&instance->slots.frame_info[i]); + + return vpu_dec_reset(&instance->vpu); +} + +static void vdec_av1_slice_get_pic_info(struct vdec_av1_slice_instance *instance) +{ + struct mtk_vcodec_ctx *ctx = instance->ctx; + u32 data[3]; + + mtk_vcodec_debug(instance, "w %u h %u\n", ctx->picinfo.pic_w, ctx->picinfo.pic_h); + + data[0] = ctx->picinfo.pic_w; + data[1] = ctx->picinfo.pic_h; + data[2] = ctx->capture_fourcc; + vpu_dec_get_param(&instance->vpu, data, 3, GET_PARAM_PIC_INFO); + + ctx->picinfo.buf_w = ALIGN(ctx->picinfo.pic_w, VCODEC_DEC_ALIGNED_64); + ctx->picinfo.buf_h = ALIGN(ctx->picinfo.pic_h, VCODEC_DEC_ALIGNED_64); + ctx->picinfo.fb_sz[0] = instance->vpu.fb_sz[0]; + ctx->picinfo.fb_sz[1] = instance->vpu.fb_sz[1]; +} + +static inline void vdec_av1_slice_get_dpb_size(struct vdec_av1_slice_instance *instance, + u32 *dpb_sz) +{ + /* refer av1 specification */ + *dpb_sz = V4L2_AV1_TOTAL_REFS_PER_FRAME + 1; +} + +static void vdec_av1_slice_get_crop_info(struct vdec_av1_slice_instance *instance, + struct v4l2_rect *cr) +{ + struct mtk_vcodec_ctx *ctx = instance->ctx; + + cr->left = 0; + cr->top = 0; + cr->width = ctx->picinfo.pic_w; + cr->height = ctx->picinfo.pic_h; + + mtk_vcodec_debug(instance, "l=%d, t=%d, w=%d, h=%d\n", + cr->left, cr->top, cr->width, cr->height); +} + +static int vdec_av1_slice_get_param(void *h_vdec, enum vdec_get_param_type type, void *out) +{ + struct vdec_av1_slice_instance *instance = h_vdec; + + switch (type) { + case GET_PARAM_PIC_INFO: + vdec_av1_slice_get_pic_info(instance); + break; + case GET_PARAM_DPB_SIZE: + vdec_av1_slice_get_dpb_size(instance, out); + break; + case GET_PARAM_CROP_INFO: + vdec_av1_slice_get_crop_info(instance, out); + break; + default: + mtk_vcodec_err(instance, "invalid get parameter type=%d\n", type); + return -EINVAL; + } + + return 0; +} + +static int vdec_av1_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_av1_slice_instance *instance = h_vdec; + struct vdec_lat_buf *lat_buf; + struct vdec_av1_slice_pfc *pfc; + struct vdec_av1_slice_vsi *vsi; + struct mtk_vcodec_ctx *ctx; + int ret; + + if (!instance || !instance->ctx) + return -EINVAL; + + ctx = instance->ctx; + /* init msgQ for the first time */ + if (vdec_msg_queue_init(&ctx->msg_queue, ctx, + vdec_av1_slice_core_decode, sizeof(*pfc))) { + mtk_vcodec_err(instance, "failed to init AV1 msg queue\n"); + return -ENOMEM; + } + + /* bs NULL means flush decoder */ + if (!bs) + return vdec_av1_slice_flush(h_vdec, bs, fb, res_chg); + + lat_buf = vdec_msg_queue_dqbuf(&ctx->msg_queue.lat_ctx); + if (!lat_buf) { + mtk_vcodec_err(instance, "failed to get AV1 lat buf\n"); + return -EAGAIN; + } + pfc = (struct vdec_av1_slice_pfc *)lat_buf->private_data; + if (!pfc) { + ret = -EINVAL; + goto err_free_fb_out; + } + vsi = &pfc->vsi; + + ret = vdec_av1_slice_setup_lat(instance, bs, lat_buf, pfc); + if (ret) { + mtk_vcodec_err(instance, "failed to setup AV1 lat ret %d\n", ret); + goto err_free_fb_out; + } + + vdec_av1_slice_vsi_to_remote(vsi, instance->vsi); + ret = vpu_dec_start(&instance->vpu, NULL, 0); + if (ret) { + mtk_vcodec_err(instance, "failed to dec AV1 ret %d\n", ret); + goto err_free_fb_out; + } + if (instance->inneracing_mode) + vdec_msg_queue_qbuf(&ctx->msg_queue.core_ctx, lat_buf); + + if (instance->irq_enabled) { + ret = mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, + MTK_VDEC_LAT0); + /* update remote vsi if decode timeout */ + if (ret) { + mtk_vcodec_err(instance, "AV1 Frame %d decode timeout %d\n", pfc->seq, ret); + WRITE_ONCE(instance->vsi->state.timeout, 1); + } + vpu_dec_end(&instance->vpu); + } + + vdec_av1_slice_vsi_from_remote(vsi, instance->vsi); + ret = vdec_av1_slice_update_lat(instance, lat_buf, pfc); + + /* LAT trans full, re-decode */ + if (ret == -EAGAIN) { + mtk_vcodec_err(instance, "AV1 Frame %d trans full\n", pfc->seq); + if (!instance->inneracing_mode) + vdec_msg_queue_qbuf(&ctx->msg_queue.lat_ctx, lat_buf); + return 0; + } + + /* LAT trans full, no more UBE or decode timeout */ + if (ret == -ENOMEM || vsi->state.timeout) { + mtk_vcodec_err(instance, "AV1 Frame %d insufficient buffer or timeout\n", pfc->seq); + if (!instance->inneracing_mode) + vdec_msg_queue_qbuf(&ctx->msg_queue.lat_ctx, lat_buf); + return -EBUSY; + } + vsi->trans.dma_addr_end += ctx->msg_queue.wdma_addr.dma_addr; + mtk_vcodec_debug(instance, "lat dma 1 0x%pad 0x%pad\n", + &pfc->vsi.trans.dma_addr, &pfc->vsi.trans.dma_addr_end); + + vdec_msg_queue_update_ube_wptr(&ctx->msg_queue, vsi->trans.dma_addr_end); + + if (!instance->inneracing_mode) + vdec_msg_queue_qbuf(&ctx->msg_queue.core_ctx, lat_buf); + memcpy(&instance->slots, &vsi->slots, sizeof(instance->slots)); + + return 0; + +err_free_fb_out: + vdec_msg_queue_qbuf(&ctx->msg_queue.lat_ctx, lat_buf); + + if (pfc) + mtk_vcodec_err(instance, "slice dec number: %d err: %d", pfc->seq, ret); + + return ret; +} + +static int vdec_av1_slice_core_decode(struct vdec_lat_buf *lat_buf) +{ + struct vdec_av1_slice_instance *instance; + struct vdec_av1_slice_pfc *pfc; + struct mtk_vcodec_ctx *ctx = NULL; + struct vdec_fb *fb = NULL; + int ret = -EINVAL; + + if (!lat_buf) + return -EINVAL; + + pfc = lat_buf->private_data; + ctx = lat_buf->ctx; + if (!pfc || !ctx) + return -EINVAL; + + instance = ctx->drv_handle; + if (!instance) + goto err; + + fb = ctx->dev->vdec_pdata->get_cap_buffer(ctx); + if (!fb) { + ret = -EBUSY; + goto err; + } + + ret = vdec_av1_slice_setup_core(instance, fb, lat_buf, pfc); + if (ret) { + mtk_vcodec_err(instance, "vdec_av1_slice_setup_core\n"); + goto err; + } + vdec_av1_slice_vsi_to_remote(&pfc->vsi, instance->core_vsi); + ret = vpu_dec_core(&instance->vpu); + if (ret) { + mtk_vcodec_err(instance, "vpu_dec_core\n"); + goto err; + } + + if (instance->irq_enabled) { + ret = mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, + MTK_VDEC_CORE); + /* update remote vsi if decode timeout */ + if (ret) { + mtk_vcodec_err(instance, "AV1 frame %d core timeout\n", pfc->seq); + WRITE_ONCE(instance->vsi->state.timeout, 1); + } + vpu_dec_core_end(&instance->vpu); + } + + ret = vdec_av1_slice_update_core(instance, lat_buf, pfc); + if (ret) { + mtk_vcodec_err(instance, "vdec_av1_slice_update_core\n"); + goto err; + } + + mtk_vcodec_debug(instance, "core dma_addr_end 0x%pad\n", + &instance->core_vsi->trans.dma_addr_end); + vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, instance->core_vsi->trans.dma_addr_end); + + ctx->dev->vdec_pdata->cap_to_disp(ctx, 0, lat_buf->src_buf_req); + + return 0; + +err: + /* always update read pointer */ + vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, pfc->vsi.trans.dma_addr_end); + + if (fb) + ctx->dev->vdec_pdata->cap_to_disp(ctx, 1, lat_buf->src_buf_req); + + return ret; +} + +const struct vdec_common_if vdec_av1_slice_lat_if = { + .init = vdec_av1_slice_init, + .decode = vdec_av1_slice_lat_decode, + .get_param = vdec_av1_slice_get_param, + .deinit = vdec_av1_slice_deinit, +}; diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c index 999ce7ee5fdc..a7e8e3257b7f 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c @@ -596,7 +596,7 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, lat_buf = vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx); if (!lat_buf) { - mtk_vcodec_err(inst, "failed to get lat buffer"); + mtk_vcodec_debug(inst, "failed to get lat buffer"); return -EAGAIN; } share_info = lat_buf->private_data; @@ -672,7 +672,7 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) { memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params, sizeof(share_info->h264_slice_params)); - vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf); + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf); } /* wait decoder done interrupt */ @@ -698,7 +698,7 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) { memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params, sizeof(share_info->h264_slice_params)); - vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf); + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf); } mtk_vcodec_debug(inst, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->slice_dec_num, inst->vsi->dec.crc[0], inst->vsi->dec.crc[1], inst->vsi->dec.crc[2]); diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_hevc_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_hevc_req_multi_if.c new file mode 100644 index 000000000000..1e6ab138b0bb --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_hevc_req_multi_if.c @@ -0,0 +1,1097 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Yunfei Dong <yunfei.dong@mediatek.com> + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <media/videobuf2-dma-contig.h> + +#include "../mtk_vcodec_util.h" +#include "../mtk_vcodec_dec.h" +#include "../mtk_vcodec_intr.h" +#include "../vdec_drv_base.h" +#include "../vdec_drv_if.h" +#include "../vdec_vpu_if.h" + +/* the size used to store hevc wrap information */ +#define VDEC_HEVC_WRAP_SZ (532 * SZ_1K) + +#define HEVC_MAX_MV_NUM 32 + +/* get used parameters for sps/pps */ +#define GET_HEVC_VDEC_FLAG(cond, flag) \ + { dst_param->cond = ((src_param->flags & (flag)) ? (1) : (0)); } +#define GET_HEVC_VDEC_PARAM(param) \ + { dst_param->param = src_param->param; } + +/** + * enum vdec_hevc_core_dec_err_type - core decode error type + * + * @TRANS_BUFFER_FULL: trans buffer is full + * @SLICE_HEADER_FULL: slice header buffer is full + */ +enum vdec_hevc_core_dec_err_type { + TRANS_BUFFER_FULL = 1, + SLICE_HEADER_FULL, +}; + +/** + * struct mtk_hevc_dpb_info - hevc dpb information + * + * @y_dma_addr: Y plane physical address + * @c_dma_addr: CbCr plane physical address + * @reference_flag: reference picture flag (short/long term reference picture) + * @field: field picture flag + */ +struct mtk_hevc_dpb_info { + dma_addr_t y_dma_addr; + dma_addr_t c_dma_addr; + int reference_flag; + int field; +}; + +/* + * struct mtk_hevc_sps_param - parameters for sps + */ +struct mtk_hevc_sps_param { + unsigned char video_parameter_set_id; + unsigned char seq_parameter_set_id; + unsigned short pic_width_in_luma_samples; + unsigned short pic_height_in_luma_samples; + unsigned char bit_depth_luma_minus8; + unsigned char bit_depth_chroma_minus8; + unsigned char log2_max_pic_order_cnt_lsb_minus4; + unsigned char sps_max_dec_pic_buffering_minus1; + unsigned char sps_max_num_reorder_pics; + unsigned char sps_max_latency_increase_plus1; + unsigned char log2_min_luma_coding_block_size_minus3; + unsigned char log2_diff_max_min_luma_coding_block_size; + unsigned char log2_min_luma_transform_block_size_minus2; + unsigned char log2_diff_max_min_luma_transform_block_size; + unsigned char max_transform_hierarchy_depth_inter; + unsigned char max_transform_hierarchy_depth_intra; + unsigned char pcm_sample_bit_depth_luma_minus1; + unsigned char pcm_sample_bit_depth_chroma_minus1; + unsigned char log2_min_pcm_luma_coding_block_size_minus3; + unsigned char log2_diff_max_min_pcm_luma_coding_block_size; + unsigned char num_short_term_ref_pic_sets; + unsigned char num_long_term_ref_pics_sps; + unsigned char chroma_format_idc; + unsigned char sps_max_sub_layers_minus1; + unsigned char separate_colour_plane; + unsigned char scaling_list_enabled; + unsigned char amp_enabled; + unsigned char sample_adaptive_offset; + unsigned char pcm_enabled; + unsigned char pcm_loop_filter_disabled; + unsigned char long_term_ref_pics_enabled; + unsigned char sps_temporal_mvp_enabled; + unsigned char strong_intra_smoothing_enabled; + unsigned char reserved[5]; +}; + +/* + * struct mtk_hevc_pps_param - parameters for pps + */ +struct mtk_hevc_pps_param { + unsigned char pic_parameter_set_id; + unsigned char num_extra_slice_header_bits; + unsigned char num_ref_idx_l0_default_active_minus1; + unsigned char num_ref_idx_l1_default_active_minus1; + char init_qp_minus26; + unsigned char diff_cu_qp_delta_depth; + char pps_cb_qp_offset; + char pps_cr_qp_offset; + unsigned char num_tile_columns_minus1; + unsigned char num_tile_rows_minus1; + unsigned char column_width_minus1[20]; + unsigned char row_height_minus1[22]; + char pps_beta_offset_div2; + char pps_tc_offset_div2; + unsigned char log2_parallel_merge_level_minus2; + char dependent_slice_segment_enabled; + char output_flag_present; + char sign_data_hiding_enabled; + char cabac_init_present; + char constrained_intra_pred; + char transform_skip_enabled; + char cu_qp_delta_enabled; + char pps_slice_chroma_qp_offsets_present; + char weighted_pred; + char weighted_bipred; + char transquant_bypass_enabled; + char pps_flag_tiles_enabled; + char entropy_coding_sync_enabled; + char loop_filter_across_tiles_enabled; + char pps_loop_filter_across_slices_enabled; + char deblocking_filter_override_enabled; + char pps_disable_deflocking_filter; + char lists_modification_present; + char slice_segment_header_extersion_present; + char deblocking_filter_control_present; + char uniform_spacing; + char reserved[6]; +}; + +/* + * struct mtk_hevc_slice_header_param - parameters for slice header + */ +struct mtk_hevc_slice_header_param { + unsigned int slice_type; + unsigned int num_active_ref_layer_pics; + int slice_qp; + int slice_qp_delta_cb; + int slice_qp_delta_cr; + int num_ref_idx[3]; + unsigned int col_ref_idx; + unsigned int five_minus_max_num_merge_cand; + int slice_deblocking_filter_beta_offset_div2; + int slice_deblocking_filter_tc_offset_div2; + unsigned char sao_enable_flag; + unsigned char sao_enable_flag_chroma; + unsigned char cabac_init_flag; + unsigned char slice_tmvp_flags_present; + unsigned char col_from_l0_flag; + unsigned char mvd_l1_zero_flag; + unsigned char slice_loop_filter_across_slices_enabled_flag; + unsigned char deblocking_filter_disable_flag; + unsigned int slice_reg0; + unsigned int slice_reg1; + unsigned int slice_reg2; + unsigned int num_rps_curr_temp_list; + unsigned int ref_list_mode; + int str_num_delta_pocs; + int str_num_negtive_pos_pics; + int num_long_term; + int num_long_term_sps; + unsigned int max_cu_width; + unsigned int max_cu_height; + unsigned int num_entry_point_offsets; + unsigned int last_lcu_x_in_tile[17]; + unsigned int last_lcu_y_in_tile[17]; + unsigned char nal_unit_type; +}; + +/* + * struct slice_api_hevc_scaling_matrix - parameters for scaling list + */ +struct slice_api_hevc_scaling_matrix { + unsigned char scaling_list_4x4[6][16]; + unsigned char scaling_list_8x8[6][64]; + unsigned char scaling_list_16x16[6][64]; + unsigned char scaling_list_32x32[2][64]; + unsigned char scaling_list_dc_coef_16x16[6]; + unsigned char scaling_list_dc_coef_32x32[2]; +}; + +/* + * struct slice_hevc_dpb_entry - each dpb information + */ +struct slice_hevc_dpb_entry { + u64 timestamp; + unsigned char flags; + unsigned char field_pic; + int pic_order_cnt_val; +}; + +/* + * struct slice_api_hevc_decode_param - parameters for decode. + */ +struct slice_api_hevc_decode_param { + struct slice_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + int pic_order_cnt_val; + unsigned short short_term_ref_pic_set_size; + unsigned short long_term_ref_pic_set_size; + unsigned char num_active_dpb_entries; + unsigned char num_poc_st_curr_before; + unsigned char num_poc_st_curr_after; + unsigned char num_poc_lt_curr; + unsigned char poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + unsigned char poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + unsigned char poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + unsigned char num_delta_pocs_of_ref_rps_idx; + int flags; +}; + +/** + * struct hevc_fb - hevc decode frame buffer information + * + * @vdec_fb_va: virtual address of struct vdec_fb + * @y_fb_dma: dma address of Y frame buffer (luma) + * @c_fb_dma: dma address of C frame buffer (chroma) + * @poc: picture order count of frame buffer + * @reserved: for 8 bytes alignment + */ +struct hevc_fb { + u64 vdec_fb_va; + u64 y_fb_dma; + u64 c_fb_dma; + s32 poc; + u32 reserved; +}; + +/** + * struct vdec_hevc_slice_lat_dec_param - parameters for decode current frame + * + * @sps: hevc sps syntax parameters + * @pps: hevc pps syntax parameters + * @slice_header: hevc slice header syntax parameters + * @scaling_matrix: hevc scaling list parameters + * @decode_params: decoder parameters of each frame used for hardware decode + * @hevc_dpb_info: dpb reference list + */ +struct vdec_hevc_slice_lat_dec_param { + struct mtk_hevc_sps_param sps; + struct mtk_hevc_pps_param pps; + struct mtk_hevc_slice_header_param slice_header; + struct slice_api_hevc_scaling_matrix scaling_matrix; + struct slice_api_hevc_decode_param decode_params; + struct mtk_hevc_dpb_info hevc_dpb_info[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; +}; + +/** + * struct vdec_hevc_slice_info - decode information + * + * @wdma_end_addr_offset: wdma end address offset + * @timeout: Decode timeout: 1 timeout, 0 no timeount + * @vdec_fb_va: VDEC frame buffer struct virtual address + * @crc: Used to check whether hardware's status is right + */ +struct vdec_hevc_slice_info { + u64 wdma_end_addr_offset; + u64 timeout; + u64 vdec_fb_va; + u32 crc[8]; +}; + +/* + * struct vdec_hevc_slice_mem - memory address and size + */ +struct vdec_hevc_slice_mem { + union { + u64 buf; + dma_addr_t dma_addr; + }; + union { + size_t size; + dma_addr_t dma_addr_end; + u64 padding; + }; +}; + +/** + * struct vdec_hevc_slice_fb - frame buffer for decoding + * @y: current y buffer address info + * @c: current c buffer address info + */ +struct vdec_hevc_slice_fb { + struct vdec_hevc_slice_mem y; + struct vdec_hevc_slice_mem c; +}; + +/** + * struct vdec_hevc_slice_vsi - shared memory for decode information exchange + * between SCP and Host. + * + * @bs: input buffer info + * + * @ube: ube buffer + * @trans: transcoded buffer + * @err_map: err map buffer + * @slice_bc: slice bc buffer + * @wrap: temp buffer + * + * @fb: current y/c buffer + * @mv_buf_dma: HW working motion vector buffer + * @dec: decode information (AP-R, VPU-W) + * @hevc_slice_params: decode parameters for hw used + */ +struct vdec_hevc_slice_vsi { + /* used in LAT stage */ + struct vdec_hevc_slice_mem bs; + + struct vdec_hevc_slice_mem ube; + struct vdec_hevc_slice_mem trans; + struct vdec_hevc_slice_mem err_map; + struct vdec_hevc_slice_mem slice_bc; + struct vdec_hevc_slice_mem wrap; + + struct vdec_hevc_slice_fb fb; + struct vdec_hevc_slice_mem mv_buf_dma[HEVC_MAX_MV_NUM]; + struct vdec_hevc_slice_info dec; + struct vdec_hevc_slice_lat_dec_param hevc_slice_params; +}; + +/** + * struct vdec_hevc_slice_share_info - shared information used to exchange + * message between lat and core + * + * @sps: sequence header information from user space + * @dec_params: decoder params from user space + * @hevc_slice_params: decoder params used for hardware + * @trans: trans buffer dma address + */ +struct vdec_hevc_slice_share_info { + struct v4l2_ctrl_hevc_sps sps; + struct v4l2_ctrl_hevc_decode_params dec_params; + struct vdec_hevc_slice_lat_dec_param hevc_slice_params; + struct vdec_hevc_slice_mem trans; +}; + +/** + * struct vdec_hevc_slice_inst - hevc decoder instance + * + * @slice_dec_num: how many picture be decoded + * @ctx: point to mtk_vcodec_ctx + * @mv_buf: HW working motion vector buffer + * @vpu: VPU instance + * @vsi: vsi used for lat + * @vsi_core: vsi used for core + * @wrap_addr: wrap address used for hevc + * + * @hevc_slice_param: the parameters that hardware use to decode + * + * @resolution_changed: resolution changed + * @realloc_mv_buf: reallocate mv buffer + * @cap_num_planes: number of capture queue plane + */ +struct vdec_hevc_slice_inst { + unsigned int slice_dec_num; + struct mtk_vcodec_ctx *ctx; + struct mtk_vcodec_mem mv_buf[HEVC_MAX_MV_NUM]; + struct vdec_vpu_inst vpu; + struct vdec_hevc_slice_vsi *vsi; + struct vdec_hevc_slice_vsi *vsi_core; + struct mtk_vcodec_mem wrap_addr; + + struct vdec_hevc_slice_lat_dec_param hevc_slice_param; + + unsigned int resolution_changed; + unsigned int realloc_mv_buf; + unsigned int cap_num_planes; +}; + +static unsigned int vdec_hevc_get_mv_buf_size(unsigned int width, unsigned int height) +{ + const unsigned int unit_size = (width / 16) * (height / 16) + 8; + + return 64 * unit_size; +} + +static void *vdec_hevc_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) +{ + struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, id); + + if (!ctrl) + return ERR_PTR(-EINVAL); + + return ctrl->p_cur.p; +} + +static void vdec_hevc_fill_dpb_info(struct mtk_vcodec_ctx *ctx, + struct slice_api_hevc_decode_param *decode_params, + struct mtk_hevc_dpb_info *hevc_dpb_info) +{ + const struct slice_hevc_dpb_entry *dpb; + struct vb2_queue *vq; + struct vb2_buffer *vb; + int index; + + vq = v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + for (index = 0; index < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; index++) { + dpb = &decode_params->dpb[index]; + if (index >= decode_params->num_active_dpb_entries) + continue; + + vb = vb2_find_buffer(vq, dpb->timestamp); + if (!vb) { + dev_err(&ctx->dev->plat_dev->dev, + "Reference invalid: dpb_index(%d) timestamp(%lld)", + index, dpb->timestamp); + continue; + } + + hevc_dpb_info[index].field = dpb->field_pic; + + hevc_dpb_info[index].y_dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) + hevc_dpb_info[index].c_dma_addr = vb2_dma_contig_plane_dma_addr(vb, 1); + else + hevc_dpb_info[index].c_dma_addr = + hevc_dpb_info[index].y_dma_addr + ctx->picinfo.fb_sz[0]; + } +} + +static void vdec_hevc_copy_sps_params(struct mtk_hevc_sps_param *dst_param, + const struct v4l2_ctrl_hevc_sps *src_param) +{ + GET_HEVC_VDEC_PARAM(video_parameter_set_id); + GET_HEVC_VDEC_PARAM(seq_parameter_set_id); + GET_HEVC_VDEC_PARAM(pic_width_in_luma_samples); + GET_HEVC_VDEC_PARAM(pic_height_in_luma_samples); + GET_HEVC_VDEC_PARAM(bit_depth_luma_minus8); + GET_HEVC_VDEC_PARAM(bit_depth_chroma_minus8); + GET_HEVC_VDEC_PARAM(log2_max_pic_order_cnt_lsb_minus4); + GET_HEVC_VDEC_PARAM(sps_max_dec_pic_buffering_minus1); + GET_HEVC_VDEC_PARAM(sps_max_num_reorder_pics); + GET_HEVC_VDEC_PARAM(sps_max_latency_increase_plus1); + GET_HEVC_VDEC_PARAM(log2_min_luma_coding_block_size_minus3); + GET_HEVC_VDEC_PARAM(log2_diff_max_min_luma_coding_block_size); + GET_HEVC_VDEC_PARAM(log2_min_luma_transform_block_size_minus2); + GET_HEVC_VDEC_PARAM(log2_diff_max_min_luma_transform_block_size); + GET_HEVC_VDEC_PARAM(max_transform_hierarchy_depth_inter); + GET_HEVC_VDEC_PARAM(max_transform_hierarchy_depth_intra); + GET_HEVC_VDEC_PARAM(pcm_sample_bit_depth_luma_minus1); + GET_HEVC_VDEC_PARAM(pcm_sample_bit_depth_chroma_minus1); + GET_HEVC_VDEC_PARAM(log2_min_pcm_luma_coding_block_size_minus3); + GET_HEVC_VDEC_PARAM(log2_diff_max_min_pcm_luma_coding_block_size); + GET_HEVC_VDEC_PARAM(num_short_term_ref_pic_sets); + GET_HEVC_VDEC_PARAM(num_long_term_ref_pics_sps); + GET_HEVC_VDEC_PARAM(chroma_format_idc); + GET_HEVC_VDEC_PARAM(sps_max_sub_layers_minus1); + + GET_HEVC_VDEC_FLAG(separate_colour_plane, + V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE); + GET_HEVC_VDEC_FLAG(scaling_list_enabled, + V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED); + GET_HEVC_VDEC_FLAG(amp_enabled, + V4L2_HEVC_SPS_FLAG_AMP_ENABLED); + GET_HEVC_VDEC_FLAG(sample_adaptive_offset, + V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET); + GET_HEVC_VDEC_FLAG(pcm_enabled, + V4L2_HEVC_SPS_FLAG_PCM_ENABLED); + GET_HEVC_VDEC_FLAG(pcm_loop_filter_disabled, + V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED); + GET_HEVC_VDEC_FLAG(long_term_ref_pics_enabled, + V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT); + GET_HEVC_VDEC_FLAG(sps_temporal_mvp_enabled, + V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED); + GET_HEVC_VDEC_FLAG(strong_intra_smoothing_enabled, + V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED); +} + +static void vdec_hevc_copy_pps_params(struct mtk_hevc_pps_param *dst_param, + const struct v4l2_ctrl_hevc_pps *src_param) +{ + int i; + + GET_HEVC_VDEC_PARAM(pic_parameter_set_id); + GET_HEVC_VDEC_PARAM(num_extra_slice_header_bits); + GET_HEVC_VDEC_PARAM(num_ref_idx_l0_default_active_minus1); + GET_HEVC_VDEC_PARAM(num_ref_idx_l1_default_active_minus1); + GET_HEVC_VDEC_PARAM(init_qp_minus26); + GET_HEVC_VDEC_PARAM(diff_cu_qp_delta_depth); + GET_HEVC_VDEC_PARAM(pps_cb_qp_offset); + GET_HEVC_VDEC_PARAM(pps_cr_qp_offset); + GET_HEVC_VDEC_PARAM(num_tile_columns_minus1); + GET_HEVC_VDEC_PARAM(num_tile_rows_minus1); + GET_HEVC_VDEC_PARAM(init_qp_minus26); + GET_HEVC_VDEC_PARAM(diff_cu_qp_delta_depth); + GET_HEVC_VDEC_PARAM(pic_parameter_set_id); + GET_HEVC_VDEC_PARAM(num_extra_slice_header_bits); + GET_HEVC_VDEC_PARAM(num_ref_idx_l0_default_active_minus1); + GET_HEVC_VDEC_PARAM(num_ref_idx_l1_default_active_minus1); + GET_HEVC_VDEC_PARAM(pps_beta_offset_div2); + GET_HEVC_VDEC_PARAM(pps_tc_offset_div2); + GET_HEVC_VDEC_PARAM(log2_parallel_merge_level_minus2); + + for (i = 0; i < ARRAY_SIZE(src_param->column_width_minus1); i++) + GET_HEVC_VDEC_PARAM(column_width_minus1[i]); + for (i = 0; i < ARRAY_SIZE(src_param->row_height_minus1); i++) + GET_HEVC_VDEC_PARAM(row_height_minus1[i]); + + GET_HEVC_VDEC_FLAG(dependent_slice_segment_enabled, + V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); + GET_HEVC_VDEC_FLAG(output_flag_present, + V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); + GET_HEVC_VDEC_FLAG(sign_data_hiding_enabled, + V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED); + GET_HEVC_VDEC_FLAG(cabac_init_present, + V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT); + GET_HEVC_VDEC_FLAG(constrained_intra_pred, + V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED); + GET_HEVC_VDEC_FLAG(transform_skip_enabled, + V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED); + GET_HEVC_VDEC_FLAG(cu_qp_delta_enabled, + V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED); + GET_HEVC_VDEC_FLAG(pps_slice_chroma_qp_offsets_present, + V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT); + GET_HEVC_VDEC_FLAG(weighted_pred, + V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED); + GET_HEVC_VDEC_FLAG(weighted_bipred, + V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED); + GET_HEVC_VDEC_FLAG(transquant_bypass_enabled, + V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED); + GET_HEVC_VDEC_FLAG(pps_flag_tiles_enabled, + V4L2_HEVC_PPS_FLAG_TILES_ENABLED); + GET_HEVC_VDEC_FLAG(entropy_coding_sync_enabled, + V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED); + GET_HEVC_VDEC_FLAG(loop_filter_across_tiles_enabled, + V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED); + GET_HEVC_VDEC_FLAG(pps_loop_filter_across_slices_enabled, + V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED); + GET_HEVC_VDEC_FLAG(deblocking_filter_override_enabled, + V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED); + GET_HEVC_VDEC_FLAG(pps_disable_deflocking_filter, + V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER); + GET_HEVC_VDEC_FLAG(lists_modification_present, + V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT); + GET_HEVC_VDEC_FLAG(slice_segment_header_extersion_present, + V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT); + GET_HEVC_VDEC_FLAG(deblocking_filter_control_present, + V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); + GET_HEVC_VDEC_FLAG(uniform_spacing, + V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING); +} + +static void vdec_hevc_copy_scaling_matrix(struct slice_api_hevc_scaling_matrix *dst_matrix, + const struct v4l2_ctrl_hevc_scaling_matrix *src_matrix) +{ + memcpy(dst_matrix, src_matrix, sizeof(*src_matrix)); +} + +static void +vdec_hevc_copy_decode_params(struct slice_api_hevc_decode_param *dst_param, + const struct v4l2_ctrl_hevc_decode_params *src_param, + const struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]) +{ + struct slice_hevc_dpb_entry *dst_entry; + const struct v4l2_hevc_dpb_entry *src_entry; + int i; + + for (i = 0; i < ARRAY_SIZE(dst_param->dpb); i++) { + dst_entry = &dst_param->dpb[i]; + src_entry = &dpb[i]; + + dst_entry->timestamp = src_entry->timestamp; + dst_entry->flags = src_entry->flags; + dst_entry->field_pic = src_entry->field_pic; + dst_entry->pic_order_cnt_val = src_entry->pic_order_cnt_val; + + GET_HEVC_VDEC_PARAM(poc_st_curr_before[i]); + GET_HEVC_VDEC_PARAM(poc_st_curr_after[i]); + GET_HEVC_VDEC_PARAM(poc_lt_curr[i]); + } + + GET_HEVC_VDEC_PARAM(pic_order_cnt_val); + GET_HEVC_VDEC_PARAM(short_term_ref_pic_set_size); + GET_HEVC_VDEC_PARAM(long_term_ref_pic_set_size); + GET_HEVC_VDEC_PARAM(num_active_dpb_entries); + GET_HEVC_VDEC_PARAM(num_poc_st_curr_before); + GET_HEVC_VDEC_PARAM(num_poc_st_curr_after); + GET_HEVC_VDEC_PARAM(num_delta_pocs_of_ref_rps_idx); + GET_HEVC_VDEC_PARAM(num_poc_lt_curr); + GET_HEVC_VDEC_PARAM(flags); +} + +static int vdec_hevc_slice_fill_decode_parameters(struct vdec_hevc_slice_inst *inst, + struct vdec_hevc_slice_share_info *share_info) +{ + struct vdec_hevc_slice_lat_dec_param *slice_param = &inst->vsi->hevc_slice_params; + const struct v4l2_ctrl_hevc_decode_params *dec_params; + const struct v4l2_ctrl_hevc_scaling_matrix *src_matrix; + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + + dec_params = + vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); + if (IS_ERR(dec_params)) + return PTR_ERR(dec_params); + + src_matrix = + vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); + if (IS_ERR(src_matrix)) + return PTR_ERR(src_matrix); + + sps = vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_SPS); + if (IS_ERR(sps)) + return PTR_ERR(sps); + + pps = vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_PPS); + if (IS_ERR(pps)) + return PTR_ERR(pps); + + vdec_hevc_copy_sps_params(&slice_param->sps, sps); + vdec_hevc_copy_pps_params(&slice_param->pps, pps); + vdec_hevc_copy_scaling_matrix(&slice_param->scaling_matrix, src_matrix); + + memcpy(&share_info->sps, sps, sizeof(*sps)); + memcpy(&share_info->dec_params, dec_params, sizeof(*dec_params)); + + slice_param->decode_params.num_poc_st_curr_before = dec_params->num_poc_st_curr_before; + slice_param->decode_params.num_poc_st_curr_after = dec_params->num_poc_st_curr_after; + slice_param->decode_params.num_poc_lt_curr = dec_params->num_poc_lt_curr; + slice_param->decode_params.num_delta_pocs_of_ref_rps_idx = + dec_params->num_delta_pocs_of_ref_rps_idx; + + return 0; +} + +static void vdec_hevc_slice_fill_decode_reflist(struct vdec_hevc_slice_inst *inst, + struct vdec_hevc_slice_lat_dec_param *slice_param, + struct vdec_hevc_slice_share_info *share_info) +{ + struct v4l2_ctrl_hevc_decode_params *dec_params = &share_info->dec_params; + + vdec_hevc_copy_decode_params(&slice_param->decode_params, dec_params, + share_info->dec_params.dpb); + + vdec_hevc_fill_dpb_info(inst->ctx, &slice_param->decode_params, + slice_param->hevc_dpb_info); +} + +static int vdec_hevc_slice_alloc_mv_buf(struct vdec_hevc_slice_inst *inst, + struct vdec_pic_info *pic) +{ + unsigned int buf_sz = vdec_hevc_get_mv_buf_size(pic->buf_w, pic->buf_h); + struct mtk_vcodec_mem *mem; + int i, err; + + mtk_v4l2_debug(3, "allocate mv buffer size = 0x%x", buf_sz); + for (i = 0; i < HEVC_MAX_MV_NUM; i++) { + mem = &inst->mv_buf[i]; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + mem->size = buf_sz; + err = mtk_vcodec_mem_alloc(inst->ctx, mem); + if (err) { + mtk_vcodec_err(inst, "failed to allocate mv buf"); + return err; + } + } + + return 0; +} + +static void vdec_hevc_slice_free_mv_buf(struct vdec_hevc_slice_inst *inst) +{ + int i; + struct mtk_vcodec_mem *mem; + + for (i = 0; i < HEVC_MAX_MV_NUM; i++) { + mem = &inst->mv_buf[i]; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + } +} + +static void vdec_hevc_slice_get_pic_info(struct vdec_hevc_slice_inst *inst) +{ + struct mtk_vcodec_ctx *ctx = inst->ctx; + u32 data[3]; + + data[0] = ctx->picinfo.pic_w; + data[1] = ctx->picinfo.pic_h; + data[2] = ctx->capture_fourcc; + vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); + + ctx->picinfo.buf_w = ALIGN(ctx->picinfo.pic_w, VCODEC_DEC_ALIGNED_64); + ctx->picinfo.buf_h = ALIGN(ctx->picinfo.pic_h, VCODEC_DEC_ALIGNED_64); + ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0]; + ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1]; + inst->cap_num_planes = + ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes; + + mtk_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)", + ctx->picinfo.pic_w, ctx->picinfo.pic_h, + ctx->picinfo.buf_w, ctx->picinfo.buf_h); + mtk_vcodec_debug(inst, "Y/C(%d, %d)", ctx->picinfo.fb_sz[0], + ctx->picinfo.fb_sz[1]); + + if (ctx->last_decoded_picinfo.pic_w != ctx->picinfo.pic_w || + ctx->last_decoded_picinfo.pic_h != ctx->picinfo.pic_h) { + inst->resolution_changed = true; + if (ctx->last_decoded_picinfo.buf_w != ctx->picinfo.buf_w || + ctx->last_decoded_picinfo.buf_h != ctx->picinfo.buf_h) + inst->realloc_mv_buf = true; + + mtk_v4l2_debug(1, "resChg: (%d %d) : old(%d, %d) -> new(%d, %d)", + inst->resolution_changed, + inst->realloc_mv_buf, + ctx->last_decoded_picinfo.pic_w, + ctx->last_decoded_picinfo.pic_h, + ctx->picinfo.pic_w, ctx->picinfo.pic_h); + } +} + +static void vdec_hevc_slice_get_crop_info(struct vdec_hevc_slice_inst *inst, + struct v4l2_rect *cr) +{ + cr->left = 0; + cr->top = 0; + cr->width = inst->ctx->picinfo.pic_w; + cr->height = inst->ctx->picinfo.pic_h; + + mtk_vcodec_debug(inst, "l=%d, t=%d, w=%d, h=%d", + cr->left, cr->top, cr->width, cr->height); +} + +static int vdec_hevc_slice_setup_lat_buffer(struct vdec_hevc_slice_inst *inst, + struct mtk_vcodec_mem *bs, + struct vdec_lat_buf *lat_buf, + bool *res_chg) +{ + struct mtk_vcodec_mem *mem; + struct mtk_video_dec_buf *src_buf_info; + struct vdec_hevc_slice_share_info *share_info; + int i, err; + + inst->vsi->bs.dma_addr = (u64)bs->dma_addr; + inst->vsi->bs.size = bs->size; + + src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer); + lat_buf->src_buf_req = src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req; + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, true); + + *res_chg = inst->resolution_changed; + if (inst->resolution_changed) { + mtk_vcodec_debug(inst, "- resolution changed -"); + if (inst->realloc_mv_buf) { + err = vdec_hevc_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); + inst->realloc_mv_buf = false; + if (err) + return err; + } + inst->resolution_changed = false; + } + + for (i = 0; i < HEVC_MAX_MV_NUM; i++) { + mem = &inst->mv_buf[i]; + inst->vsi->mv_buf_dma[i].dma_addr = mem->dma_addr; + inst->vsi->mv_buf_dma[i].size = mem->size; + } + + inst->vsi->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size; + + inst->vsi->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr; + inst->vsi->err_map.size = lat_buf->wdma_err_addr.size; + + inst->vsi->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr; + inst->vsi->slice_bc.size = lat_buf->slice_bc_addr.size; + + inst->vsi->trans.dma_addr_end = inst->ctx->msg_queue.wdma_rptr_addr; + inst->vsi->trans.dma_addr = inst->ctx->msg_queue.wdma_wptr_addr; + + share_info = lat_buf->private_data; + share_info->trans.dma_addr = inst->vsi->trans.dma_addr; + share_info->trans.dma_addr_end = inst->vsi->trans.dma_addr_end; + + mtk_vcodec_debug(inst, "lat: ube addr/size(0x%llx 0x%llx) err:0x%llx", + inst->vsi->ube.buf, + inst->vsi->ube.padding, + inst->vsi->err_map.buf); + + mtk_vcodec_debug(inst, "slice addr/size(0x%llx 0x%llx) trans start/end((0x%llx 0x%llx))", + inst->vsi->slice_bc.buf, + inst->vsi->slice_bc.padding, + inst->vsi->trans.buf, + inst->vsi->trans.padding); + + return 0; +} + +static int vdec_hevc_slice_setup_core_buffer(struct vdec_hevc_slice_inst *inst, + struct vdec_hevc_slice_share_info *share_info, + struct vdec_lat_buf *lat_buf) +{ + struct mtk_vcodec_mem *mem; + struct mtk_vcodec_ctx *ctx = inst->ctx; + struct vb2_v4l2_buffer *vb2_v4l2; + struct vdec_fb *fb; + u64 y_fb_dma, c_fb_dma; + int i; + + fb = ctx->dev->vdec_pdata->get_cap_buffer(ctx); + if (!fb) { + mtk_vcodec_err(inst, "fb buffer is NULL"); + return -EBUSY; + } + + y_fb_dma = (u64)fb->base_y.dma_addr; + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 1) + c_fb_dma = + y_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h; + else + c_fb_dma = (u64)fb->base_c.dma_addr; + + mtk_vcodec_debug(inst, "[hevc-core] y/c addr = 0x%llx 0x%llx", y_fb_dma, + c_fb_dma); + + inst->vsi_core->fb.y.dma_addr = y_fb_dma; + inst->vsi_core->fb.y.size = ctx->picinfo.fb_sz[0]; + inst->vsi_core->fb.c.dma_addr = c_fb_dma; + inst->vsi_core->fb.y.size = ctx->picinfo.fb_sz[1]; + + inst->vsi_core->dec.vdec_fb_va = (unsigned long)fb; + + inst->vsi_core->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi_core->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size; + + inst->vsi_core->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr; + inst->vsi_core->err_map.size = lat_buf->wdma_err_addr.size; + + inst->vsi_core->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr; + inst->vsi_core->slice_bc.size = lat_buf->slice_bc_addr.size; + + inst->vsi_core->trans.dma_addr = share_info->trans.dma_addr; + inst->vsi_core->trans.dma_addr_end = share_info->trans.dma_addr_end; + + inst->vsi_core->wrap.dma_addr = inst->wrap_addr.dma_addr; + inst->vsi_core->wrap.size = inst->wrap_addr.size; + + for (i = 0; i < HEVC_MAX_MV_NUM; i++) { + mem = &inst->mv_buf[i]; + inst->vsi_core->mv_buf_dma[i].dma_addr = mem->dma_addr; + inst->vsi_core->mv_buf_dma[i].size = mem->size; + } + + vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); + v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, vb2_v4l2, true); + + return 0; +} + +static int vdec_hevc_slice_init(struct mtk_vcodec_ctx *ctx) +{ + struct vdec_hevc_slice_inst *inst; + int err, vsi_size; + + inst = kzalloc(sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->ctx = ctx; + + inst->vpu.id = SCP_IPI_VDEC_LAT; + inst->vpu.core_id = SCP_IPI_VDEC_CORE; + inst->vpu.ctx = ctx; + inst->vpu.codec_type = ctx->current_codec; + inst->vpu.capture_type = ctx->capture_fourcc; + + ctx->drv_handle = inst; + err = vpu_dec_init(&inst->vpu); + if (err) { + mtk_vcodec_err(inst, "vdec_hevc init err=%d", err); + goto error_free_inst; + } + + vsi_size = round_up(sizeof(struct vdec_hevc_slice_vsi), VCODEC_DEC_ALIGNED_64); + inst->vsi = inst->vpu.vsi; + inst->vsi_core = + (struct vdec_hevc_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size); + + inst->resolution_changed = true; + inst->realloc_mv_buf = true; + + inst->wrap_addr.size = VDEC_HEVC_WRAP_SZ; + err = mtk_vcodec_mem_alloc(ctx, &inst->wrap_addr); + if (err) + goto error_free_inst; + + mtk_vcodec_debug(inst, "lat struct size = %d,%d,%d,%d vsi: %d\n", + (int)sizeof(struct mtk_hevc_sps_param), + (int)sizeof(struct mtk_hevc_pps_param), + (int)sizeof(struct vdec_hevc_slice_lat_dec_param), + (int)sizeof(struct mtk_hevc_dpb_info), + vsi_size); + mtk_vcodec_debug(inst, "lat hevc instance >> %p, codec_type = 0x%x", + inst, inst->vpu.codec_type); + + return 0; +error_free_inst: + kfree(inst); + return err; +} + +static void vdec_hevc_slice_deinit(void *h_vdec) +{ + struct vdec_hevc_slice_inst *inst = h_vdec; + struct mtk_vcodec_mem *mem; + + mtk_vcodec_debug_enter(inst); + + vpu_dec_deinit(&inst->vpu); + vdec_hevc_slice_free_mv_buf(inst); + + mem = &inst->wrap_addr; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + + vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx); + kfree(inst); +} + +static int vdec_hevc_slice_core_decode(struct vdec_lat_buf *lat_buf) +{ + int err, timeout; + struct mtk_vcodec_ctx *ctx = lat_buf->ctx; + struct vdec_hevc_slice_inst *inst = ctx->drv_handle; + struct vdec_hevc_slice_share_info *share_info = lat_buf->private_data; + struct vdec_vpu_inst *vpu = &inst->vpu; + + mtk_vcodec_debug(inst, "[hevc-core] vdec_hevc core decode"); + memcpy(&inst->vsi_core->hevc_slice_params, &share_info->hevc_slice_params, + sizeof(share_info->hevc_slice_params)); + + err = vdec_hevc_slice_setup_core_buffer(inst, share_info, lat_buf); + if (err) + goto vdec_dec_end; + + vdec_hevc_slice_fill_decode_reflist(inst, &inst->vsi_core->hevc_slice_params, + share_info); + err = vpu_dec_core(vpu); + if (err) { + mtk_vcodec_err(inst, "core decode err=%d", err); + goto vdec_dec_end; + } + + /* wait decoder done interrupt */ + timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); + if (timeout) + mtk_vcodec_err(inst, "core decode timeout: pic_%d", + ctx->decoded_frame_cnt); + inst->vsi_core->dec.timeout = !!timeout; + + vpu_dec_core_end(vpu); + mtk_vcodec_debug(inst, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", + ctx->decoded_frame_cnt, + inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1], + inst->vsi_core->dec.crc[2], inst->vsi_core->dec.crc[3], + inst->vsi_core->dec.crc[4], inst->vsi_core->dec.crc[5], + inst->vsi_core->dec.crc[6], inst->vsi_core->dec.crc[7]); + +vdec_dec_end: + vdec_msg_queue_update_ube_rptr(&lat_buf->ctx->msg_queue, share_info->trans.dma_addr_end); + ctx->dev->vdec_pdata->cap_to_disp(ctx, !!err, lat_buf->src_buf_req); + mtk_vcodec_debug(inst, "core decode done err=%d", err); + ctx->decoded_frame_cnt++; + return 0; +} + +static int vdec_hevc_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_hevc_slice_inst *inst = h_vdec; + struct vdec_vpu_inst *vpu = &inst->vpu; + int err, timeout = 0; + unsigned int data[2]; + struct vdec_lat_buf *lat_buf; + struct vdec_hevc_slice_share_info *share_info; + + if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx, + vdec_hevc_slice_core_decode, + sizeof(*share_info))) + return -ENOMEM; + + /* bs NULL means flush decoder */ + if (!bs) { + vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue); + return vpu_dec_reset(vpu); + } + + lat_buf = vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx); + if (!lat_buf) { + mtk_vcodec_debug(inst, "failed to get lat buffer"); + return -EAGAIN; + } + + share_info = lat_buf->private_data; + err = vdec_hevc_slice_fill_decode_parameters(inst, share_info); + if (err) + goto err_free_fb_out; + + err = vdec_hevc_slice_setup_lat_buffer(inst, bs, lat_buf, res_chg); + if (err) + goto err_free_fb_out; + + err = vpu_dec_start(vpu, data, 2); + if (err) { + mtk_vcodec_debug(inst, "lat decode err: %d", err); + goto err_free_fb_out; + } + + if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) { + memcpy(&share_info->hevc_slice_params, &inst->vsi->hevc_slice_params, + sizeof(share_info->hevc_slice_params)); + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf); + } + + /* wait decoder done interrupt */ + timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); + if (timeout) + mtk_vcodec_err(inst, "lat decode timeout: pic_%d", inst->slice_dec_num); + inst->vsi->dec.timeout = !!timeout; + + err = vpu_dec_end(vpu); + if (err == SLICE_HEADER_FULL || err == TRANS_BUFFER_FULL) { + if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf); + inst->slice_dec_num++; + mtk_vcodec_err(inst, "lat dec fail: pic_%d err:%d", inst->slice_dec_num, err); + return -EINVAL; + } + + share_info->trans.dma_addr_end = inst->ctx->msg_queue.wdma_addr.dma_addr + + inst->vsi->dec.wdma_end_addr_offset; + vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue, share_info->trans.dma_addr_end); + + if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) { + memcpy(&share_info->hevc_slice_params, &inst->vsi->hevc_slice_params, + sizeof(share_info->hevc_slice_params)); + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf); + } + mtk_vcodec_debug(inst, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->slice_dec_num, + inst->vsi->dec.crc[0], inst->vsi->dec.crc[1], inst->vsi->dec.crc[2]); + + inst->slice_dec_num++; + return 0; +err_free_fb_out: + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf); + mtk_vcodec_err(inst, "slice dec number: %d err: %d", inst->slice_dec_num, err); + return err; +} + +static int vdec_hevc_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *unused, bool *res_chg) +{ + struct vdec_hevc_slice_inst *inst = h_vdec; + + if (!h_vdec || inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE) + return -EINVAL; + + return vdec_hevc_slice_lat_decode(h_vdec, bs, unused, res_chg); +} + +static int vdec_hevc_slice_get_param(void *h_vdec, enum vdec_get_param_type type, + void *out) +{ + struct vdec_hevc_slice_inst *inst = h_vdec; + + switch (type) { + case GET_PARAM_PIC_INFO: + vdec_hevc_slice_get_pic_info(inst); + break; + case GET_PARAM_DPB_SIZE: + *(unsigned int *)out = 6; + break; + case GET_PARAM_CROP_INFO: + vdec_hevc_slice_get_crop_info(inst, out); + break; + default: + mtk_vcodec_err(inst, "invalid get parameter type=%d", type); + return -EINVAL; + } + return 0; +} + +const struct vdec_common_if vdec_hevc_slice_multi_if = { + .init = vdec_hevc_slice_init, + .decode = vdec_hevc_slice_decode, + .get_param = vdec_hevc_slice_get_param, + .deinit = vdec_hevc_slice_deinit, +}; diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c index cf16cf2807f0..c2f90848f498 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c @@ -2069,7 +2069,7 @@ static int vdec_vp9_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, lat_buf = vdec_msg_queue_dqbuf(&instance->ctx->msg_queue.lat_ctx); if (!lat_buf) { - mtk_vcodec_err(instance, "Failed to get VP9 lat buf\n"); + mtk_vcodec_debug(instance, "Failed to get VP9 lat buf\n"); return -EAGAIN; } pfc = (struct vdec_vp9_slice_pfc *)lat_buf->private_data; @@ -2119,7 +2119,7 @@ static int vdec_vp9_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, vdec_msg_queue_update_ube_wptr(&ctx->msg_queue, vsi->trans.dma_addr_end + ctx->msg_queue.wdma_addr.dma_addr); - vdec_msg_queue_qbuf(&ctx->dev->msg_queue_core_ctx, lat_buf); + vdec_msg_queue_qbuf(&ctx->msg_queue.core_ctx, lat_buf); return 0; err_free_fb_out: diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c index f3807f03d880..06d393174cc2 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c @@ -49,6 +49,14 @@ int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned int fourcc) ctx->dec_if = &vdec_vp9_slice_lat_if; ctx->hw_id = IS_VDEC_LAT_ARCH(hw_arch) ? MTK_VDEC_LAT0 : MTK_VDEC_CORE; break; + case V4L2_PIX_FMT_HEVC_SLICE: + ctx->dec_if = &vdec_hevc_slice_multi_if; + ctx->hw_id = MTK_VDEC_LAT0; + break; + case V4L2_PIX_FMT_AV1_FRAME: + ctx->dec_if = &vdec_av1_slice_lat_if; + ctx->hw_id = MTK_VDEC_LAT0; + break; default: return -EINVAL; } diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h index 076306ff2dd4..a8da6a59a6a5 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h @@ -61,6 +61,8 @@ extern const struct vdec_common_if vdec_vp8_if; extern const struct vdec_common_if vdec_vp8_slice_if; extern const struct vdec_common_if vdec_vp9_if; extern const struct vdec_common_if vdec_vp9_slice_lat_if; +extern const struct vdec_common_if vdec_hevc_slice_multi_if; +extern const struct vdec_common_if vdec_av1_slice_lat_if; /** * vdec_if_init() - initialize decode driver diff --git a/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c b/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c index f3073d1e7f42..f555341ae708 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c @@ -20,6 +20,9 @@ /* the size used to store avc error information */ #define VDEC_ERR_MAP_SZ_AVC (17 * SZ_1K) +#define VDEC_RD_MV_BUFFER_SZ (((SZ_4K * 2304 >> 4) + SZ_1K) << 1) +#define VDEC_LAT_TILE_SZ (64 * V4L2_AV1_MAX_TILE_COUNT) + /* core will read the trans buffer which decoded by lat to decode again. * The trans buffer size of FHD and 4K bitstreams are different. */ @@ -71,7 +74,6 @@ static void vdec_msg_queue_dec(struct vdec_msg_queue *msg_queue, int hardware_in int vdec_msg_queue_qbuf(struct vdec_msg_queue_ctx *msg_ctx, struct vdec_lat_buf *buf) { struct list_head *head; - int status; head = vdec_get_buf_list(msg_ctx->hardware_index, buf); if (!head) { @@ -87,12 +89,9 @@ int vdec_msg_queue_qbuf(struct vdec_msg_queue_ctx *msg_ctx, struct vdec_lat_buf if (msg_ctx->hardware_index != MTK_VDEC_CORE) { wake_up_all(&msg_ctx->ready_to_use); } else { - if (buf->ctx->msg_queue.core_work_cnt < - atomic_read(&buf->ctx->msg_queue.core_list_cnt)) { - status = queue_work(buf->ctx->dev->core_workqueue, - &buf->ctx->msg_queue.core_work); - if (status) - buf->ctx->msg_queue.core_work_cnt++; + if (!(buf->ctx->msg_queue.status & CONTEXT_LIST_QUEUED)) { + queue_work(buf->ctx->dev->core_workqueue, &buf->ctx->msg_queue.core_work); + buf->ctx->msg_queue.status |= CONTEXT_LIST_QUEUED; } } @@ -181,49 +180,23 @@ void vdec_msg_queue_update_ube_wptr(struct vdec_msg_queue *msg_queue, uint64_t u bool vdec_msg_queue_wait_lat_buf_full(struct vdec_msg_queue *msg_queue) { - struct vdec_lat_buf *buf, *tmp; - struct list_head *list_core[3]; - struct vdec_msg_queue_ctx *core_ctx; - int ret, i, in_core_count = 0, count = 0; - long timeout_jiff; - - core_ctx = &msg_queue->ctx->dev->msg_queue_core_ctx; - spin_lock(&core_ctx->ready_lock); - list_for_each_entry_safe(buf, tmp, &core_ctx->ready_queue, core_list) { - if (buf && buf->ctx == msg_queue->ctx) { - list_core[in_core_count++] = &buf->core_list; - list_del(&buf->core_list); - } - } - - for (i = 0; i < in_core_count; i++) { - list_add(list_core[in_core_count - (1 + i)], &core_ctx->ready_queue); - queue_work(msg_queue->ctx->dev->core_workqueue, &msg_queue->core_work); - } - spin_unlock(&core_ctx->ready_lock); - - timeout_jiff = msecs_to_jiffies(1000 * (NUM_BUFFER_COUNT + 2)); - ret = wait_event_timeout(msg_queue->ctx->msg_queue.core_dec_done, - msg_queue->lat_ctx.ready_num == NUM_BUFFER_COUNT, - timeout_jiff); - if (ret) { - mtk_v4l2_debug(3, "success to get lat buf: %d", - msg_queue->lat_ctx.ready_num); + if (atomic_read(&msg_queue->lat_list_cnt) == NUM_BUFFER_COUNT) { + mtk_v4l2_debug(3, "wait buf full: list(%d %d) ready_num:%d status:%d", + atomic_read(&msg_queue->lat_list_cnt), + atomic_read(&msg_queue->core_list_cnt), + msg_queue->lat_ctx.ready_num, + msg_queue->status); return true; } - spin_lock(&core_ctx->ready_lock); - list_for_each_entry_safe(buf, tmp, &core_ctx->ready_queue, core_list) { - if (buf && buf->ctx == msg_queue->ctx) { - count++; - list_del(&buf->core_list); - } - } - spin_unlock(&core_ctx->ready_lock); + msg_queue->flush_done = false; + vdec_msg_queue_qbuf(&msg_queue->core_ctx, &msg_queue->empty_lat_buf); + wait_event(msg_queue->core_dec_done, msg_queue->flush_done); - mtk_v4l2_err("failed with lat buf isn't full: list(%d %d) count:%d", - atomic_read(&msg_queue->lat_list_cnt), - atomic_read(&msg_queue->core_list_cnt), count); + mtk_v4l2_debug(3, "flush done => ready_num:%d status:%d list(%d %d)", + msg_queue->lat_ctx.ready_num, msg_queue->status, + atomic_read(&msg_queue->lat_list_cnt), + atomic_read(&msg_queue->core_list_cnt)); return false; } @@ -249,8 +222,18 @@ void vdec_msg_queue_deinit(struct vdec_msg_queue *msg_queue, if (mem->va) mtk_vcodec_mem_free(ctx, mem); + mem = &lat_buf->rd_mv_addr; + if (mem->va) + mtk_vcodec_mem_free(ctx, mem); + + mem = &lat_buf->tile_addr; + if (mem->va) + mtk_vcodec_mem_free(ctx, mem); + kfree(lat_buf->private_data); } + + cancel_work_sync(&msg_queue->core_work); } static void vdec_msg_queue_core_work(struct work_struct *work) @@ -261,12 +244,23 @@ static void vdec_msg_queue_core_work(struct work_struct *work) container_of(msg_queue, struct mtk_vcodec_ctx, msg_queue); struct mtk_vcodec_dev *dev = ctx->dev; struct vdec_lat_buf *lat_buf; - int status; - lat_buf = vdec_msg_queue_dqbuf(&dev->msg_queue_core_ctx); + spin_lock(&msg_queue->core_ctx.ready_lock); + ctx->msg_queue.status &= ~CONTEXT_LIST_QUEUED; + spin_unlock(&msg_queue->core_ctx.ready_lock); + + lat_buf = vdec_msg_queue_dqbuf(&msg_queue->core_ctx); if (!lat_buf) return; + if (lat_buf->is_last_frame) { + ctx->msg_queue.status = CONTEXT_LIST_DEC_DONE; + msg_queue->flush_done = true; + wake_up(&ctx->msg_queue.core_dec_done); + + return; + } + ctx = lat_buf->ctx; mtk_vcodec_dec_enable_hardware(ctx, MTK_VDEC_CORE); mtk_vcodec_set_curr_ctx(dev, ctx, MTK_VDEC_CORE); @@ -277,18 +271,13 @@ static void vdec_msg_queue_core_work(struct work_struct *work) mtk_vcodec_dec_disable_hardware(ctx, MTK_VDEC_CORE); vdec_msg_queue_qbuf(&ctx->msg_queue.lat_ctx, lat_buf); - wake_up_all(&ctx->msg_queue.core_dec_done); - spin_lock(&dev->msg_queue_core_ctx.ready_lock); - lat_buf->ctx->msg_queue.core_work_cnt--; - - if (lat_buf->ctx->msg_queue.core_work_cnt < - atomic_read(&lat_buf->ctx->msg_queue.core_list_cnt)) { - status = queue_work(lat_buf->ctx->dev->core_workqueue, - &lat_buf->ctx->msg_queue.core_work); - if (status) - lat_buf->ctx->msg_queue.core_work_cnt++; + if (!(ctx->msg_queue.status & CONTEXT_LIST_QUEUED) && + atomic_read(&msg_queue->core_list_cnt)) { + spin_lock(&msg_queue->core_ctx.ready_lock); + ctx->msg_queue.status |= CONTEXT_LIST_QUEUED; + spin_unlock(&msg_queue->core_ctx.ready_lock); + queue_work(ctx->dev->core_workqueue, &msg_queue->core_work); } - spin_unlock(&dev->msg_queue_core_ctx.ready_lock); } int vdec_msg_queue_init(struct vdec_msg_queue *msg_queue, @@ -302,14 +291,14 @@ int vdec_msg_queue_init(struct vdec_msg_queue *msg_queue, if (msg_queue->wdma_addr.size) return 0; - msg_queue->ctx = ctx; - msg_queue->core_work_cnt = 0; vdec_msg_queue_init_ctx(&msg_queue->lat_ctx, MTK_VDEC_LAT0); + vdec_msg_queue_init_ctx(&msg_queue->core_ctx, MTK_VDEC_CORE); INIT_WORK(&msg_queue->core_work, vdec_msg_queue_core_work); atomic_set(&msg_queue->lat_list_cnt, 0); atomic_set(&msg_queue->core_list_cnt, 0); init_waitqueue_head(&msg_queue->core_dec_done); + msg_queue->status = CONTEXT_LIST_EMPTY; msg_queue->wdma_addr.size = vde_msg_queue_get_trans_size(ctx->picinfo.buf_w, @@ -322,6 +311,10 @@ int vdec_msg_queue_init(struct vdec_msg_queue *msg_queue, msg_queue->wdma_rptr_addr = msg_queue->wdma_addr.dma_addr; msg_queue->wdma_wptr_addr = msg_queue->wdma_addr.dma_addr; + msg_queue->empty_lat_buf.ctx = ctx; + msg_queue->empty_lat_buf.core_decode = NULL; + msg_queue->empty_lat_buf.is_last_frame = true; + for (i = 0; i < NUM_BUFFER_COUNT; i++) { lat_buf = &msg_queue->lat_buf[i]; @@ -339,6 +332,22 @@ int vdec_msg_queue_init(struct vdec_msg_queue *msg_queue, goto mem_alloc_err; } + if (ctx->current_codec == V4L2_PIX_FMT_AV1_FRAME) { + lat_buf->rd_mv_addr.size = VDEC_RD_MV_BUFFER_SZ; + err = mtk_vcodec_mem_alloc(ctx, &lat_buf->rd_mv_addr); + if (err) { + mtk_v4l2_err("failed to allocate rd_mv_addr buf[%d]", i); + return -ENOMEM; + } + + lat_buf->tile_addr.size = VDEC_LAT_TILE_SZ; + err = mtk_vcodec_mem_alloc(ctx, &lat_buf->tile_addr); + if (err) { + mtk_v4l2_err("failed to allocate tile_addr buf[%d]", i); + return -ENOMEM; + } + } + lat_buf->private_data = kzalloc(private_size, GFP_KERNEL); if (!lat_buf->private_data) { err = -ENOMEM; @@ -347,6 +356,7 @@ int vdec_msg_queue_init(struct vdec_msg_queue *msg_queue, lat_buf->ctx = ctx; lat_buf->core_decode = core_decode; + lat_buf->is_last_frame = false; err = vdec_msg_queue_qbuf(&msg_queue->lat_ctx, lat_buf); if (err) { mtk_v4l2_err("failed to qbuf buf[%d]", i); diff --git a/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.h b/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.h index a5d44bc97c16..2a745e902ad1 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.h @@ -22,6 +22,18 @@ struct mtk_vcodec_dev; typedef int (*core_decode_cb_t)(struct vdec_lat_buf *lat_buf); /** + * enum core_ctx_status - Context decode status for core hardwre. + * @CONTEXT_LIST_EMPTY: No buffer queued on core hardware(must always be 0) + * @CONTEXT_LIST_QUEUED: Buffer queued to core work list + * @CONTEXT_LIST_DEC_DONE: context decode done + */ +enum core_ctx_status { + CONTEXT_LIST_EMPTY = 0, + CONTEXT_LIST_QUEUED, + CONTEXT_LIST_DEC_DONE, +}; + +/** * struct vdec_msg_queue_ctx - represents a queue for buffers ready to be processed * @ready_to_use: ready used queue used to signalize when get a job queue * @ready_queue: list of ready lat buffer queues @@ -42,6 +54,8 @@ struct vdec_msg_queue_ctx { * struct vdec_lat_buf - lat buffer message used to store lat info for core decode * @wdma_err_addr: wdma error address used for lat hardware * @slice_bc_addr: slice bc address used for lat hardware + * @rd_mv_addr: mv addr for av1 lat hardware output, core hardware input + * @tile_addr: tile buffer for av1 core input * @ts_info: need to set timestamp from output to capture * @src_buf_req: output buffer media request object * @@ -50,10 +64,14 @@ struct vdec_msg_queue_ctx { * @core_decode: different codec use different decode callback function * @lat_list: add lat buffer to lat head list * @core_list: add lat buffer to core head list + * + * @is_last_frame: meaning this buffer is the last frame */ struct vdec_lat_buf { struct mtk_vcodec_mem wdma_err_addr; struct mtk_vcodec_mem slice_bc_addr; + struct mtk_vcodec_mem rd_mv_addr; + struct mtk_vcodec_mem tile_addr; struct vb2_v4l2_buffer ts_info; struct media_request *src_buf_req; @@ -62,6 +80,8 @@ struct vdec_lat_buf { core_decode_cb_t core_decode; struct list_head lat_list; struct list_head core_list; + + bool is_last_frame; }; /** @@ -72,12 +92,14 @@ struct vdec_lat_buf { * @wdma_wptr_addr: ube write point * @core_work: core hardware work * @lat_ctx: used to store lat buffer list - * @ctx: point to mtk_vcodec_ctx + * @core_ctx: used to store core buffer list * * @lat_list_cnt: used to record each instance lat list count * @core_list_cnt: used to record each instance core list count + * @flush_done: core flush done status + * @empty_lat_buf: the last lat buf used to flush decode * @core_dec_done: core work queue decode done event - * @core_work_cnt: the number of core work in work queue + * @status: current context decode status for core hardware */ struct vdec_msg_queue { struct vdec_lat_buf lat_buf[NUM_BUFFER_COUNT]; @@ -88,12 +110,14 @@ struct vdec_msg_queue { struct work_struct core_work; struct vdec_msg_queue_ctx lat_ctx; - struct mtk_vcodec_ctx *ctx; + struct vdec_msg_queue_ctx core_ctx; atomic_t lat_list_cnt; atomic_t core_list_cnt; + bool flush_done; + struct vdec_lat_buf empty_lat_buf; wait_queue_head_t core_dec_done; - int core_work_cnt; + int status; }; /** diff --git a/drivers/media/platform/mediatek/vpu/mtk_vpu.c b/drivers/media/platform/mediatek/vpu/mtk_vpu.c index 5e2bc286f168..4c8f5296d120 100644 --- a/drivers/media/platform/mediatek/vpu/mtk_vpu.c +++ b/drivers/media/platform/mediatek/vpu/mtk_vpu.c @@ -562,15 +562,17 @@ static int load_requested_vpu(struct mtk_vpu *vpu, int vpu_load_firmware(struct platform_device *pdev) { struct mtk_vpu *vpu; - struct device *dev = &pdev->dev; + struct device *dev; struct vpu_run *run; int ret; if (!pdev) { - dev_err(dev, "VPU platform device is invalid\n"); + pr_err("VPU platform device is invalid\n"); return -EINVAL; } + dev = &pdev->dev; + vpu = platform_get_drvdata(pdev); run = &vpu->run; @@ -1016,6 +1018,7 @@ static int mtk_vpu_resume(struct device *dev) clk_prepare(vpu->clk); ret = vpu_clock_enable(vpu); if (ret) { + clk_unprepare(vpu->clk); dev_err(dev, "failed to enable vpu clock\n"); return ret; } diff --git a/drivers/media/platform/nxp/imx7-media-csi.c b/drivers/media/platform/nxp/imx7-media-csi.c index b701e823436a..0bd2613b9320 100644 --- a/drivers/media/platform/nxp/imx7-media-csi.c +++ b/drivers/media/platform/nxp/imx7-media-csi.c @@ -1014,39 +1014,6 @@ static int imx7_csi_enum_mbus_formats(u32 *code, u32 index) return -EINVAL; } -static int imx7_csi_mbus_fmt_to_pix_fmt(struct v4l2_pix_format *pix, - const struct v4l2_mbus_framefmt *mbus, - const struct imx7_csi_pixfmt *cc) -{ - u32 width; - u32 stride; - - if (!cc) { - cc = imx7_csi_find_mbus_format(mbus->code); - if (!cc) - return -EINVAL; - } - - /* Round up width for minimum burst size */ - width = round_up(mbus->width, 8); - - /* Round up stride for IDMAC line start address alignment */ - stride = round_up((width * cc->bpp) >> 3, 8); - - pix->width = width; - pix->height = mbus->height; - pix->pixelformat = cc->fourcc; - pix->colorspace = mbus->colorspace; - pix->xfer_func = mbus->xfer_func; - pix->ycbcr_enc = mbus->ycbcr_enc; - pix->quantization = mbus->quantization; - pix->field = mbus->field; - pix->bytesperline = stride; - pix->sizeimage = stride * pix->height; - - return 0; -} - /* ----------------------------------------------------------------------------- * Video Capture Device - IOCTLs */ @@ -1145,8 +1112,13 @@ static const struct imx7_csi_pixfmt * __imx7_csi_video_try_fmt(struct v4l2_pix_format *pixfmt, struct v4l2_rect *compose) { - struct v4l2_mbus_framefmt fmt_src; const struct imx7_csi_pixfmt *cc; + u32 walign; + + if (compose) { + compose->width = pixfmt->width; + compose->height = pixfmt->height; + } /* * Find the pixel format, default to the first supported format if not @@ -1158,27 +1130,19 @@ __imx7_csi_video_try_fmt(struct v4l2_pix_format *pixfmt, cc = imx7_csi_find_pixel_format(pixfmt->pixelformat); } - /* Allow IDMAC interweave but enforce field order from source. */ - if (V4L2_FIELD_IS_INTERLACED(pixfmt->field)) { - switch (pixfmt->field) { - case V4L2_FIELD_SEQ_TB: - pixfmt->field = V4L2_FIELD_INTERLACED_TB; - break; - case V4L2_FIELD_SEQ_BT: - pixfmt->field = V4L2_FIELD_INTERLACED_BT; - break; - default: - break; - } - } + /* + * The width alignment is 8 bytes as indicated by the + * CSI_IMAG_PARA.IMAGE_WIDTH documentation. Convert it to pixels. + * + * TODO: Implement configurable stride support. + */ + walign = 8 * 8 / cc->bpp; + v4l_bound_align_image(&pixfmt->width, 1, 0xffff, walign, + &pixfmt->height, 1, 0xffff, 1, 0); - v4l2_fill_mbus_format(&fmt_src, pixfmt, 0); - imx7_csi_mbus_fmt_to_pix_fmt(pixfmt, &fmt_src, cc); - - if (compose) { - compose->width = fmt_src.width; - compose->height = fmt_src.height; - } + pixfmt->bytesperline = pixfmt->width * cc->bpp / 8; + pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; + pixfmt->field = V4L2_FIELD_NONE; return cc; } @@ -1606,22 +1570,14 @@ static struct imx7_csi_vb2_buffer *imx7_csi_video_next_buf(struct imx7_csi *csi) return buf; } -static int imx7_csi_video_init_format(struct imx7_csi *csi) +static void imx7_csi_video_init_format(struct imx7_csi *csi) { - struct v4l2_mbus_framefmt format = { }; - - format.code = IMX7_CSI_DEF_MBUS_CODE; - format.width = IMX7_CSI_DEF_PIX_WIDTH; - format.height = IMX7_CSI_DEF_PIX_HEIGHT; - format.field = V4L2_FIELD_NONE; - - imx7_csi_mbus_fmt_to_pix_fmt(&csi->vdev_fmt, &format, NULL); - csi->vdev_compose.width = format.width; - csi->vdev_compose.height = format.height; + struct v4l2_pix_format *pixfmt = &csi->vdev_fmt; - csi->vdev_cc = imx7_csi_find_pixel_format(csi->vdev_fmt.pixelformat); + pixfmt->width = IMX7_CSI_DEF_PIX_WIDTH; + pixfmt->height = IMX7_CSI_DEF_PIX_HEIGHT; - return 0; + csi->vdev_cc = __imx7_csi_video_try_fmt(pixfmt, &csi->vdev_compose); } static int imx7_csi_video_register(struct imx7_csi *csi) @@ -1634,9 +1590,7 @@ static int imx7_csi_video_register(struct imx7_csi *csi) vdev->v4l2_dev = v4l2_dev; /* Initialize the default format and compose rectangle. */ - ret = imx7_csi_video_init_format(csi); - if (ret < 0) - return ret; + imx7_csi_video_init_format(csi); /* Register the video device. */ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c index b5ffde46f31b..f7447b2f4d77 100644 --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c @@ -223,7 +223,7 @@ static int mxc_isi_crossbar_init_cfg(struct v4l2_subdev *sd, route->sink_pad = i; route->source_pad = i + xbar->num_sinks; route->flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE; - }; + } routing.num_routes = xbar->num_sources; routing.routes = routes; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index e0832f3f4f25..06c95568e5af 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -1541,7 +1541,11 @@ int msm_vfe_register_entities(struct vfe_device *vfe, } video_out->ops = &vfe->video_ops; - video_out->bpl_alignment = 8; + if (vfe->camss->version == CAMSS_845 || + vfe->camss->version == CAMSS_8250) + video_out->bpl_alignment = 16; + else + video_out->bpl_alignment = 8; video_out->line_based = 0; if (i == VFE_LINE_PIX) { video_out->bpl_alignment = 16; diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index 4f81669986ba..320bde0f83cb 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -83,6 +83,23 @@ struct venus_resources { const char *fwname; }; +enum venus_fmt { + VENUS_FMT_NV12 = 0, + VENUS_FMT_QC08C = 1, + VENUS_FMT_QC10C = 2, + VENUS_FMT_P010 = 3, + VENUS_FMT_H264 = 4, + VENUS_FMT_VP8 = 5, + VENUS_FMT_VP9 = 6, + VENUS_FMT_HEVC = 7, + VENUS_FMT_VC1_ANNEX_G = 8, + VENUS_FMT_VC1_ANNEX_L = 9, + VENUS_FMT_MPEG4 = 10, + VENUS_FMT_MPEG2 = 11, + VENUS_FMT_H263 = 12, + VENUS_FMT_XVID = 13, +}; + struct venus_format { u32 pixfmt; unsigned int num_planes; @@ -201,6 +218,11 @@ struct venus_core { unsigned int core0_usage_count; unsigned int core1_usage_count; struct dentry *root; + struct venus_img_version { + u32 major; + u32 minor; + u32 rev; + } venus_ver; }; struct vdec_controls { @@ -389,6 +411,7 @@ enum venus_inst_modes { * @sequence_out: a sequence counter for output queue * @m2m_dev: a reference to m2m device structure * @m2m_ctx: a reference to m2m context structure + * @ctx_q_lock: a lock to serialize video device ioctl calls * @state: current state of the instance * @done: a completion for sync HFI operation * @error: an error returned during last HFI sync operation @@ -460,6 +483,7 @@ struct venus_inst { u32 sequence_out; struct v4l2_m2m_dev *m2m_dev; struct v4l2_m2m_ctx *m2m_ctx; + struct mutex ctx_q_lock; unsigned int state; struct completion done; unsigned int error; @@ -508,4 +532,19 @@ venus_caps_by_codec(struct venus_core *core, u32 codec, u32 domain) return NULL; } +static inline bool +is_fw_rev_or_newer(struct venus_core *core, u32 vmajor, u32 vminor, u32 vrev) +{ + return ((core)->venus_ver.major == vmajor && + (core)->venus_ver.minor == vminor && + (core)->venus_ver.rev >= vrev); +} + +static inline bool +is_fw_rev_or_older(struct venus_core *core, u32 vmajor, u32 vminor, u32 vrev) +{ + return ((core)->venus_ver.major == vmajor && + (core)->venus_ver.minor == vminor && + (core)->venus_ver.rev <= vrev); +} #endif diff --git a/drivers/media/platform/qcom/venus/helpers.c b/drivers/media/platform/qcom/venus/helpers.c index a2ceab7f9ddb..1822e85ab6bf 100644 --- a/drivers/media/platform/qcom/venus/helpers.c +++ b/drivers/media/platform/qcom/venus/helpers.c @@ -502,7 +502,6 @@ session_process_buf(struct venus_inst *inst, struct vb2_v4l2_buffer *vbuf) struct vb2_buffer *vb = &vbuf->vb2_buf; unsigned int type = vb->type; struct hfi_frame_data fdata; - int ret; memset(&fdata, 0, sizeof(fdata)); fdata.alloc_len = buf->size; @@ -533,11 +532,7 @@ session_process_buf(struct venus_inst *inst, struct vb2_v4l2_buffer *vbuf) fdata.offset = 0; } - ret = hfi_session_process_buf(inst, &fdata); - if (ret) - return ret; - - return 0; + return hfi_session_process_buf(inst, &fdata); } static bool is_dynamic_bufmode(struct venus_inst *inst) @@ -612,6 +607,8 @@ static u32 to_hfi_raw_fmt(u32 v4l2_fmt) return HFI_COLOR_FORMAT_NV12_UBWC; case V4L2_PIX_FMT_QC10C: return HFI_COLOR_FORMAT_YUV420_TP10_UBWC; + case V4L2_PIX_FMT_P010: + return HFI_COLOR_FORMAT_P010; default: break; } @@ -639,12 +636,16 @@ static int platform_get_bufreq(struct venus_inst *inst, u32 buftype, if (is_dec) { params.width = inst->width; params.height = inst->height; + params.out_width = inst->out_width; + params.out_height = inst->out_height; params.codec = inst->fmt_out->pixfmt; params.hfi_color_fmt = to_hfi_raw_fmt(inst->fmt_cap->pixfmt); params.dec.max_mbs_per_frame = mbs_per_frame_max(inst); params.dec.buffer_size_limit = 0; params.dec.is_secondary_output = inst->opb_buftype == HFI_BUFFER_OUTPUT2; + if (params.dec.is_secondary_output) + params.hfi_dpb_color_fmt = inst->dpb_fmt; params.dec.is_interlaced = inst->pic_struct != HFI_INTERLACE_FRAME_PROGRESSIVE; } else { @@ -1036,8 +1037,8 @@ static u32 get_framesize_raw_yuv420_tp10_ubwc(u32 width, u32 height) u32 extradata = SZ_16K; u32 size; - y_stride = ALIGN(ALIGN(width, 192) * 4 / 3, 256); - uv_stride = ALIGN(ALIGN(width, 192) * 4 / 3, 256); + y_stride = ALIGN(width * 4 / 3, 256); + uv_stride = ALIGN(width * 4 / 3, 256); y_sclines = ALIGN(height, 16); uv_sclines = ALIGN((height + 1) >> 1, 16); @@ -1764,6 +1765,22 @@ int venus_helper_get_out_fmts(struct venus_inst *inst, u32 v4l2_fmt, if (!caps) return -EINVAL; + if (inst->bit_depth == VIDC_BITDEPTH_10 && inst->session_type == VIDC_SESSION_TYPE_DEC) { + found_ubwc = find_fmt_from_caps(caps, HFI_BUFFER_OUTPUT, + HFI_COLOR_FORMAT_YUV420_TP10_UBWC); + found = find_fmt_from_caps(caps, HFI_BUFFER_OUTPUT2, fmt); + if (found_ubwc && found) { + /* + * Hard-code DPB buffers to be 10bit UBWC + * until V4L2 is able to expose compressed/tiled + * formats to applications. + */ + *out_fmt = HFI_COLOR_FORMAT_YUV420_TP10_UBWC; + *out2_fmt = fmt; + return 0; + } + } + if (ubwc) { ubwc_fmt = fmt | HFI_COLOR_FORMAT_UBWC_BASE; found_ubwc = find_fmt_from_caps(caps, HFI_BUFFER_OUTPUT, diff --git a/drivers/media/platform/qcom/venus/hfi_cmds.c b/drivers/media/platform/qcom/venus/hfi_cmds.c index bc3f8ff05840..7f0802a5518c 100644 --- a/drivers/media/platform/qcom/venus/hfi_cmds.c +++ b/drivers/media/platform/qcom/venus/hfi_cmds.c @@ -83,7 +83,7 @@ int pkt_sys_set_resource(struct hfi_sys_set_resource_pkt *pkt, u32 id, u32 size, res->size = size; res->mem = addr; pkt->resource_type = HFI_RESOURCE_OCMEM; - pkt->hdr.size += sizeof(*res) - sizeof(u32); + pkt->hdr.size += sizeof(*res); break; } case VIDC_RESOURCE_NONE: @@ -200,8 +200,8 @@ int pkt_session_set_buffers(struct hfi_session_set_buffers_pkt *pkt, struct hfi_buffer_info *bi; pkt->extradata_size = bd->extradata_size; - pkt->shdr.hdr.size = sizeof(*pkt) - sizeof(u32) + - (bd->num_buffers * sizeof(*bi)); + pkt->shdr.hdr.size = sizeof(*pkt) + + bd->num_buffers * sizeof(*bi); bi = (struct hfi_buffer_info *)pkt->buffer_info; for (i = 0; i < pkt->num_buffers; i++) { bi->buffer_addr = bd->device_addr; @@ -209,8 +209,8 @@ int pkt_session_set_buffers(struct hfi_session_set_buffers_pkt *pkt, } } else { pkt->extradata_size = 0; - pkt->shdr.hdr.size = sizeof(*pkt) + - ((bd->num_buffers - 1) * sizeof(u32)); + pkt->shdr.hdr.size = struct_size(pkt, buffer_info, + bd->num_buffers); for (i = 0; i < pkt->num_buffers; i++) pkt->buffer_info[i] = bd->device_addr; } @@ -243,16 +243,16 @@ int pkt_session_unset_buffers(struct hfi_session_release_buffer_pkt *pkt, bi->extradata_addr = bd->extradata_addr; } pkt->shdr.hdr.size = - sizeof(struct hfi_session_set_buffers_pkt) - - sizeof(u32) + (bd->num_buffers * sizeof(*bi)); + sizeof(struct hfi_session_set_buffers_pkt) + + bd->num_buffers * sizeof(*bi); } else { for (i = 0; i < pkt->num_buffers; i++) pkt->buffer_info[i] = bd->device_addr; pkt->extradata_size = 0; pkt->shdr.hdr.size = - sizeof(struct hfi_session_set_buffers_pkt) + - ((bd->num_buffers - 1) * sizeof(u32)); + struct_size((struct hfi_session_set_buffers_pkt *)0, + buffer_info, bd->num_buffers); } pkt->response_req = bd->response_required; @@ -521,6 +521,7 @@ static int pkt_session_set_property_1x(struct hfi_session_set_property_pkt *pkt, pkt->shdr.hdr.size += sizeof(u32) + sizeof(*en); break; } + case HFI_PROPERTY_PARAM_VDEC_ENABLE_SUFFICIENT_SEQCHANGE_EVENT: case HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER: { struct hfi_enable *in = pdata; struct hfi_enable *en = prop_data; diff --git a/drivers/media/platform/qcom/venus/hfi_cmds.h b/drivers/media/platform/qcom/venus/hfi_cmds.h index 99bc0b6db67c..dd9c5066442d 100644 --- a/drivers/media/platform/qcom/venus/hfi_cmds.h +++ b/drivers/media/platform/qcom/venus/hfi_cmds.h @@ -56,7 +56,7 @@ struct hfi_sys_set_resource_pkt { struct hfi_pkt_hdr hdr; u32 resource_handle; u32 resource_type; - u32 resource_data[1]; + u32 resource_data[]; }; struct hfi_sys_release_resource_pkt { @@ -117,7 +117,7 @@ struct hfi_session_set_buffers_pkt { u32 extradata_size; u32 min_buffer_size; u32 num_buffers; - u32 buffer_info[1]; + u32 buffer_info[]; }; struct hfi_session_get_sequence_header_pkt { diff --git a/drivers/media/platform/qcom/venus/hfi_helper.h b/drivers/media/platform/qcom/venus/hfi_helper.h index 105792a68060..0abbc50c5864 100644 --- a/drivers/media/platform/qcom/venus/hfi_helper.h +++ b/drivers/media/platform/qcom/venus/hfi_helper.h @@ -469,6 +469,8 @@ #define HFI_PROPERTY_PARAM_VDEC_PIXEL_BITDEPTH 0x1003007 #define HFI_PROPERTY_PARAM_VDEC_PIC_STRUCT 0x1003009 #define HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE 0x100300a +#define HFI_PROPERTY_PARAM_VDEC_ENABLE_SUFFICIENT_SEQCHANGE_EVENT \ + 0x100300b /* * HFI_PROPERTY_CONFIG_VDEC_COMMON_START diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.c b/drivers/media/platform/qcom/venus/hfi_msgs.c index df96db3761a7..3d5dadfa1900 100644 --- a/drivers/media/platform/qcom/venus/hfi_msgs.c +++ b/drivers/media/platform/qcom/venus/hfi_msgs.c @@ -233,7 +233,7 @@ static void hfi_sys_init_done(struct venus_core *core, struct venus_inst *inst, goto done; } - rem_bytes = pkt->hdr.size - sizeof(*pkt) + sizeof(u32); + rem_bytes = pkt->hdr.size - sizeof(*pkt); if (rem_bytes <= 0) { /* missing property data */ error = HFI_ERR_SYS_INSUFFICIENT_RESOURCES; @@ -248,13 +248,15 @@ done: } static void -sys_get_prop_image_version(struct device *dev, +sys_get_prop_image_version(struct venus_core *core, struct hfi_msg_sys_property_info_pkt *pkt) { + struct device *dev = core->dev; u8 *smem_tbl_ptr; u8 *img_ver; int req_bytes; size_t smem_blk_sz; + int ret; req_bytes = pkt->hdr.size - sizeof(*pkt); @@ -263,8 +265,30 @@ sys_get_prop_image_version(struct device *dev, return; img_ver = pkt->data; + if (!img_ver) + return; + + ret = sscanf(img_ver, "14:video-firmware.%u.%u-%u", + &core->venus_ver.major, &core->venus_ver.minor, &core->venus_ver.rev); + if (ret) + goto done; + + ret = sscanf(img_ver, "14:VIDEO.VPU.%u.%u-%u", + &core->venus_ver.major, &core->venus_ver.minor, &core->venus_ver.rev); + if (ret) + goto done; + + ret = sscanf(img_ver, "14:VIDEO.VE.%u.%u-%u", + &core->venus_ver.major, &core->venus_ver.minor, &core->venus_ver.rev); + if (ret) + goto done; - dev_dbg(dev, VDBGL "F/W version: %s\n", img_ver); + dev_err(dev, VDBGL "error reading F/W version\n"); + return; + +done: + dev_dbg(dev, VDBGL "F/W version: %s, major %u, minor %u, revision %u\n", + img_ver, core->venus_ver.major, core->venus_ver.minor, core->venus_ver.rev); smem_tbl_ptr = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMG_VER_TBL, &smem_blk_sz); @@ -286,7 +310,7 @@ static void hfi_sys_property_info(struct venus_core *core, switch (pkt->property) { case HFI_PROPERTY_SYS_IMAGE_VERSION: - sys_get_prop_image_version(dev, pkt); + sys_get_prop_image_version(core, pkt); break; default: dev_dbg(dev, VDBGL "unknown property data\n"); @@ -434,7 +458,7 @@ static void hfi_session_init_done(struct venus_core *core, if (!IS_V1(core)) goto done; - rem_bytes = pkt->shdr.hdr.size - sizeof(*pkt) + sizeof(u32); + rem_bytes = pkt->shdr.hdr.size - sizeof(*pkt); if (rem_bytes <= 0) { error = HFI_ERR_SESSION_INSUFFICIENT_RESOURCES; goto done; diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.h b/drivers/media/platform/qcom/venus/hfi_msgs.h index 510513697335..8c2e17b0d36f 100644 --- a/drivers/media/platform/qcom/venus/hfi_msgs.h +++ b/drivers/media/platform/qcom/venus/hfi_msgs.h @@ -50,7 +50,7 @@ struct hfi_msg_event_notify_pkt { u32 event_id; u32 event_data1; u32 event_data2; - u32 ext_event_data[1]; + u32 ext_event_data[]; }; struct hfi_msg_event_release_buffer_ref_pkt { @@ -63,7 +63,7 @@ struct hfi_msg_sys_init_done_pkt { struct hfi_pkt_hdr hdr; u32 error_type; u32 num_properties; - u32 data[1]; + u32 data[]; }; struct hfi_msg_sys_pc_prep_done_pkt { @@ -81,7 +81,7 @@ struct hfi_msg_session_init_done_pkt { struct hfi_session_hdr_pkt shdr; u32 error_type; u32 num_properties; - u32 data[1]; + u32 data[]; }; struct hfi_msg_session_end_done_pkt { @@ -228,7 +228,7 @@ struct hfi_msg_session_parse_sequence_header_done_pkt { struct hfi_session_hdr_pkt shdr; u32 error_type; u32 num_properties; - u32 data[1]; + u32 data[]; }; struct hfi_msg_session_property_info_pkt { @@ -247,7 +247,7 @@ struct hfi_msg_session_release_buffers_done_pkt { struct hfi_session_hdr_pkt shdr; u32 error_type; u32 num_buffers; - u32 buffer_info[1]; + u32 buffer_info[]; }; struct hfi_msg_sys_debug_pkt { @@ -256,7 +256,7 @@ struct hfi_msg_sys_debug_pkt { u32 msg_size; u32 time_stamp_hi; u32 time_stamp_lo; - u8 msg_data[1]; + u8 msg_data[]; }; struct hfi_msg_sys_coverage_pkt { @@ -264,7 +264,7 @@ struct hfi_msg_sys_coverage_pkt { u32 msg_size; u32 time_stamp_hi; u32 time_stamp_lo; - u8 msg_data[1]; + u8 msg_data[]; }; struct venus_core; diff --git a/drivers/media/platform/qcom/venus/hfi_plat_bufs.h b/drivers/media/platform/qcom/venus/hfi_plat_bufs.h index 52a51a3b964a..25e607452096 100644 --- a/drivers/media/platform/qcom/venus/hfi_plat_bufs.h +++ b/drivers/media/platform/qcom/venus/hfi_plat_bufs.h @@ -12,8 +12,11 @@ struct hfi_plat_buffers_params { u32 width; u32 height; + u32 out_width; + u32 out_height; u32 codec; u32 hfi_color_fmt; + u32 hfi_dpb_color_fmt; enum hfi_version version; u32 num_vpp_pipes; union { diff --git a/drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c b/drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c index a9be31ec6927..e97ff8cf6d64 100644 --- a/drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c +++ b/drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c @@ -1185,6 +1185,7 @@ static int bufreq_dec(struct hfi_plat_buffers_params *params, u32 buftype, enum hfi_version version = params->version; u32 codec = params->codec; u32 width = params->width, height = params->height, out_min_count; + u32 out_width = params->out_width, out_height = params->out_height; struct dec_bufsize_ops *dec_ops; bool is_secondary_output = params->dec.is_secondary_output; bool is_interlaced = params->dec.is_interlaced; @@ -1230,12 +1231,16 @@ static int bufreq_dec(struct hfi_plat_buffers_params *params, u32 buftype, calculate_dec_input_frame_size(width, height, codec, max_mbs_per_frame, buffer_size_limit); - } else if (buftype == HFI_BUFFER_OUTPUT || - buftype == HFI_BUFFER_OUTPUT2) { + } else if (buftype == HFI_BUFFER_OUTPUT || buftype == HFI_BUFFER_OUTPUT2) { bufreq->count_min = out_min_count; bufreq->size = venus_helper_get_framesz_raw(params->hfi_color_fmt, - width, height); + out_width, out_height); + if (buftype == HFI_BUFFER_OUTPUT && + params->dec.is_secondary_output) + bufreq->size = + venus_helper_get_framesz_raw(params->hfi_dpb_color_fmt, + out_width, out_height); } else if (buftype == HFI_BUFFER_INTERNAL_SCRATCH(version)) { bufreq->size = dec_ops->scratch(width, height, is_interlaced); } else if (buftype == HFI_BUFFER_INTERNAL_SCRATCH_1(version)) { diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c index 2ad40b3945b0..f0b46389e8d5 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus.c +++ b/drivers/media/platform/qcom/venus/hfi_venus.c @@ -835,34 +835,24 @@ static int venus_sys_set_debug(struct venus_hfi_device *hdev, u32 debug) { struct hfi_sys_set_property_pkt *pkt; u8 packet[IFACEQ_VAR_SMALL_PKT_SIZE]; - int ret; pkt = (struct hfi_sys_set_property_pkt *)packet; pkt_sys_debug_config(pkt, HFI_DEBUG_MODE_QUEUE, debug); - ret = venus_iface_cmdq_write(hdev, pkt, false); - if (ret) - return ret; - - return 0; + return venus_iface_cmdq_write(hdev, pkt, false); } static int venus_sys_set_coverage(struct venus_hfi_device *hdev, u32 mode) { struct hfi_sys_set_property_pkt *pkt; u8 packet[IFACEQ_VAR_SMALL_PKT_SIZE]; - int ret; pkt = (struct hfi_sys_set_property_pkt *)packet; pkt_sys_coverage_config(pkt, mode); - ret = venus_iface_cmdq_write(hdev, pkt, false); - if (ret) - return ret; - - return 0; + return venus_iface_cmdq_write(hdev, pkt, false); } static int venus_sys_set_idle_message(struct venus_hfi_device *hdev, @@ -870,7 +860,6 @@ static int venus_sys_set_idle_message(struct venus_hfi_device *hdev, { struct hfi_sys_set_property_pkt *pkt; u8 packet[IFACEQ_VAR_SMALL_PKT_SIZE]; - int ret; if (!enable) return 0; @@ -879,11 +868,7 @@ static int venus_sys_set_idle_message(struct venus_hfi_device *hdev, pkt_sys_idle_indicator(pkt, enable); - ret = venus_iface_cmdq_write(hdev, pkt, false); - if (ret) - return ret; - - return 0; + return venus_iface_cmdq_write(hdev, pkt, false); } static int venus_sys_set_power_control(struct venus_hfi_device *hdev, @@ -891,17 +876,12 @@ static int venus_sys_set_power_control(struct venus_hfi_device *hdev, { struct hfi_sys_set_property_pkt *pkt; u8 packet[IFACEQ_VAR_SMALL_PKT_SIZE]; - int ret; pkt = (struct hfi_sys_set_property_pkt *)packet; pkt_sys_power_control(pkt, enable); - ret = venus_iface_cmdq_write(hdev, pkt, false); - if (ret) - return ret; - - return 0; + return venus_iface_cmdq_write(hdev, pkt, false); } static int venus_sys_set_ubwc_config(struct venus_hfi_device *hdev) diff --git a/drivers/media/platform/qcom/venus/vdec.c b/drivers/media/platform/qcom/venus/vdec.c index 51a53bf82bd3..f5676440dd36 100644 --- a/drivers/media/platform/qcom/venus/vdec.c +++ b/drivers/media/platform/qcom/venus/vdec.c @@ -30,69 +30,87 @@ * - future firmware versions could add support for >1 planes */ static const struct venus_format vdec_formats[] = { - { + [VENUS_FMT_NV12] = { .pixfmt = V4L2_PIX_FMT_NV12, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, - }, { + }, + [VENUS_FMT_QC08C] = { .pixfmt = V4L2_PIX_FMT_QC08C, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, - }, { + }, + [VENUS_FMT_QC10C] = { .pixfmt = V4L2_PIX_FMT_QC10C, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, - }, { - .pixfmt = V4L2_PIX_FMT_MPEG4, + }, + [VENUS_FMT_P010] = { + .pixfmt = V4L2_PIX_FMT_P010, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, + }, + [VENUS_FMT_H264] = { + .pixfmt = V4L2_PIX_FMT_H264, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_MPEG2, + }, + [VENUS_FMT_VP8] = { + .pixfmt = V4L2_PIX_FMT_VP8, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_H263, + }, + [VENUS_FMT_VP9] = { + .pixfmt = V4L2_PIX_FMT_VP9, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_G, + }, + [VENUS_FMT_HEVC] = { + .pixfmt = V4L2_PIX_FMT_HEVC, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_L, + }, + [VENUS_FMT_VC1_ANNEX_G] = { + .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_G, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_H264, + }, + [VENUS_FMT_VC1_ANNEX_L] = { + .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_L, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_VP8, + }, + [VENUS_FMT_MPEG4] = { + .pixfmt = V4L2_PIX_FMT_MPEG4, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_VP9, + }, + [VENUS_FMT_MPEG2] = { + .pixfmt = V4L2_PIX_FMT_MPEG2, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_XVID, + }, + [VENUS_FMT_H263] = { + .pixfmt = V4L2_PIX_FMT_H263, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, - }, { - .pixfmt = V4L2_PIX_FMT_HEVC, + }, + [VENUS_FMT_XVID] = { + .pixfmt = V4L2_PIX_FMT_XVID, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, }, + }; static const struct venus_format * @@ -551,7 +569,7 @@ vdec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *cmd) fdata.buffer_type = HFI_BUFFER_INPUT; fdata.flags |= HFI_BUFFERFLAG_EOS; - if (IS_V6(inst->core)) + if (IS_V6(inst->core) && is_fw_rev_or_older(inst->core, 1, 0, 87)) fdata.device_addr = 0; else fdata.device_addr = 0xdeadb000; @@ -684,6 +702,14 @@ static int vdec_set_properties(struct venus_inst *inst) return ret; } + /* Enabling sufficient sequence change support for VP9 */ + if (is_fw_rev_or_newer(inst->core, 5, 4, 51)) { + ptype = HFI_PROPERTY_PARAM_VDEC_ENABLE_SUFFICIENT_SEQCHANGE_EVENT; + ret = hfi_session_set_property(inst, ptype, &en); + if (ret) + return ret; + } + ptype = HFI_PROPERTY_PARAM_VDEC_CONCEAL_COLOR; conceal = ctr->conceal_color & 0xffff; conceal |= ((ctr->conceal_color >> 16) & 0xffff) << 10; @@ -710,6 +736,9 @@ static int vdec_set_work_route(struct venus_inst *inst) } #define is_ubwc_fmt(fmt) (!!((fmt) & HFI_COLOR_FORMAT_UBWC_BASE)) +#define is_10bit_ubwc_fmt(fmt) (!!((fmt) & HFI_COLOR_FORMAT_10_BIT_BASE & \ + HFI_COLOR_FORMAT_UBWC_BASE)) + static int vdec_output_conf(struct venus_inst *inst) { @@ -757,7 +786,7 @@ static int vdec_output_conf(struct venus_inst *inst) inst->opb_fmt = out2_fmt; inst->dpb_buftype = HFI_BUFFER_OUTPUT; inst->dpb_fmt = out_fmt; - } else if (is_ubwc_fmt(out2_fmt)) { + } else if (is_ubwc_fmt(out2_fmt) || is_10bit_ubwc_fmt(out_fmt)) { inst->opb_buftype = HFI_BUFFER_OUTPUT; inst->opb_fmt = out_fmt; inst->dpb_buftype = HFI_BUFFER_OUTPUT2; @@ -1474,8 +1503,13 @@ static void vdec_event_change(struct venus_inst *inst, inst->out_width = ev_data->width; inst->out_height = ev_data->height; - if (inst->bit_depth != ev_data->bit_depth) + if (inst->bit_depth != ev_data->bit_depth) { inst->bit_depth = ev_data->bit_depth; + if (inst->bit_depth == VIDC_BITDEPTH_10) + inst->fmt_cap = &vdec_formats[VENUS_FMT_P010]; + else + inst->fmt_cap = &vdec_formats[VENUS_FMT_NV12]; + } if (inst->pic_struct != ev_data->pic_struct) inst->pic_struct = ev_data->pic_struct; @@ -1567,8 +1601,8 @@ static const struct hfi_inst_ops vdec_hfi_ops = { static void vdec_inst_init(struct venus_inst *inst) { inst->hfi_codec = HFI_VIDEO_CODEC_H264; - inst->fmt_out = &vdec_formats[8]; - inst->fmt_cap = &vdec_formats[0]; + inst->fmt_out = &vdec_formats[VENUS_FMT_H264]; + inst->fmt_cap = &vdec_formats[VENUS_FMT_NV12]; inst->width = frame_width_min(inst); inst->height = ALIGN(frame_height_min(inst), 32); inst->crop.left = 0; @@ -1609,6 +1643,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, src_vq->allow_zero_bytesused = 1; src_vq->min_buffers_needed = 0; src_vq->dev = inst->core->dev; + src_vq->lock = &inst->ctx_q_lock; ret = vb2_queue_init(src_vq); if (ret) return ret; @@ -1623,6 +1658,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->allow_zero_bytesused = 1; dst_vq->min_buffers_needed = 0; dst_vq->dev = inst->core->dev; + dst_vq->lock = &inst->ctx_q_lock; return vb2_queue_init(dst_vq); } @@ -1641,6 +1677,7 @@ static int vdec_open(struct file *file) INIT_LIST_HEAD(&inst->internalbufs); INIT_LIST_HEAD(&inst->list); mutex_init(&inst->lock); + mutex_init(&inst->ctx_q_lock); inst->core = core; inst->session_type = VIDC_SESSION_TYPE_DEC; @@ -1716,6 +1753,7 @@ static int vdec_close(struct file *file) ida_destroy(&inst->dpb_ids); hfi_session_destroy(inst); mutex_destroy(&inst->lock); + mutex_destroy(&inst->ctx_q_lock); v4l2_fh_del(&inst->fh); v4l2_fh_exit(&inst->fh); diff --git a/drivers/media/platform/qcom/venus/venc.c b/drivers/media/platform/qcom/venus/venc.c index 4666f42feea3..6d773b000e8a 100644 --- a/drivers/media/platform/qcom/venus/venc.c +++ b/drivers/media/platform/qcom/venus/venc.c @@ -32,28 +32,33 @@ * - future firmware versions could add support for >1 planes */ static const struct venus_format venc_formats[] = { - { + [VENUS_FMT_NV12] = { .pixfmt = V4L2_PIX_FMT_NV12, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, { - .pixfmt = V4L2_PIX_FMT_MPEG4, + }, + [VENUS_FMT_H264] = { + .pixfmt = V4L2_PIX_FMT_H264, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, - }, { - .pixfmt = V4L2_PIX_FMT_H263, + }, + [VENUS_FMT_VP8] = { + .pixfmt = V4L2_PIX_FMT_VP8, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, - }, { - .pixfmt = V4L2_PIX_FMT_H264, + }, + [VENUS_FMT_HEVC] = { + .pixfmt = V4L2_PIX_FMT_HEVC, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, - }, { - .pixfmt = V4L2_PIX_FMT_VP8, + }, + [VENUS_FMT_MPEG4] = { + .pixfmt = V4L2_PIX_FMT_MPEG4, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, - }, { - .pixfmt = V4L2_PIX_FMT_HEVC, + }, + [VENUS_FMT_H263] = { + .pixfmt = V4L2_PIX_FMT_H263, .num_planes = 1, .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, }, @@ -1395,6 +1400,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, src_vq->allow_zero_bytesused = 1; src_vq->min_buffers_needed = 1; src_vq->dev = inst->core->dev; + src_vq->lock = &inst->ctx_q_lock; if (inst->core->res->hfi_version == HFI_VERSION_1XX) src_vq->bidirectional = 1; ret = vb2_queue_init(src_vq); @@ -1411,13 +1417,14 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->allow_zero_bytesused = 1; dst_vq->min_buffers_needed = 1; dst_vq->dev = inst->core->dev; + dst_vq->lock = &inst->ctx_q_lock; return vb2_queue_init(dst_vq); } static void venc_inst_init(struct venus_inst *inst) { - inst->fmt_cap = &venc_formats[3]; - inst->fmt_out = &venc_formats[0]; + inst->fmt_cap = &venc_formats[VENUS_FMT_H264]; + inst->fmt_out = &venc_formats[VENUS_FMT_NV12]; inst->width = 1280; inst->height = ALIGN(720, 32); inst->out_width = 1280; @@ -1443,6 +1450,7 @@ static int venc_open(struct file *file) INIT_LIST_HEAD(&inst->internalbufs); INIT_LIST_HEAD(&inst->list); mutex_init(&inst->lock); + mutex_init(&inst->ctx_q_lock); inst->core = core; inst->session_type = VIDC_SESSION_TYPE_ENC; @@ -1512,6 +1520,7 @@ static int venc_close(struct file *file) venc_ctrl_deinit(inst); hfi_session_destroy(inst); mutex_destroy(&inst->lock); + mutex_destroy(&inst->ctx_q_lock); v4l2_fh_del(&inst->fh); v4l2_fh_exit(&inst->fh); diff --git a/drivers/media/platform/renesas/rcar-isp.c b/drivers/media/platform/renesas/rcar-isp.c index f666b621338d..fee1a066f56b 100644 --- a/drivers/media/platform/renesas/rcar-isp.c +++ b/drivers/media/platform/renesas/rcar-isp.c @@ -430,6 +430,7 @@ static int risp_probe_resources(struct rcar_isp *isp, static const struct of_device_id risp_of_id_table[] = { { .compatible = "renesas,r8a779a0-isp" }, + { .compatible = "renesas,r8a779g0-isp" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, risp_of_id_table); diff --git a/drivers/media/platform/renesas/rcar-vin/rcar-core.c b/drivers/media/platform/renesas/rcar-vin/rcar-core.c index ff4bde9cc0e3..3c4f5eb93be1 100644 --- a/drivers/media/platform/renesas/rcar-vin/rcar-core.c +++ b/drivers/media/platform/renesas/rcar-vin/rcar-core.c @@ -1284,6 +1284,15 @@ static const struct rvin_info rcar_info_r8a779a0 = { .max_height = 4096, }; +static const struct rvin_info rcar_info_r8a779g0 = { + .model = RCAR_GEN3, + .use_mc = true, + .use_isp = true, + .nv12 = true, + .max_width = 4096, + .max_height = 4096, +}; + static const struct of_device_id rvin_of_id_table[] = { { .compatible = "renesas,vin-r8a774a1", @@ -1349,6 +1358,10 @@ static const struct of_device_id rvin_of_id_table[] = { .compatible = "renesas,vin-r8a779a0", .data = &rcar_info_r8a779a0, }, + { + .compatible = "renesas,vin-r8a779g0", + .data = &rcar_info_r8a779g0, + }, { /* Sentinel */ }, }; MODULE_DEVICE_TABLE(of, rvin_of_id_table); diff --git a/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c b/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c index e34060c2b039..7a134c0eff57 100644 --- a/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c @@ -483,11 +483,15 @@ enum rcar_csi2_pads { struct rcar_csi2_info { int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); int (*phy_post_init)(struct rcar_csi2 *priv); + int (*start_receiver)(struct rcar_csi2 *priv); + void (*enter_standby)(struct rcar_csi2 *priv); const struct rcsi2_mbps_reg *hsfreqrange; unsigned int csi0clkfreqrange; unsigned int num_channels; bool clear_ulps; bool use_isp; + bool support_dphy; + bool support_cphy; }; struct rcar_csi2 { @@ -509,6 +513,7 @@ struct rcar_csi2 { struct v4l2_mbus_framefmt mf; int stream_count; + bool cphy; unsigned short lanes; unsigned char lane_swap[4]; }; @@ -533,10 +538,17 @@ static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) iowrite32(data, priv->base + reg); } -static void rcsi2_enter_standby(struct rcar_csi2 *priv) +static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) { rcsi2_write(priv, PHYCNT_REG, 0); rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR); +} + +static void rcsi2_enter_standby(struct rcar_csi2 *priv) +{ + if (priv->info->enter_standby) + priv->info->enter_standby(priv); + reset_control_assert(priv->rstc); usleep_range(100, 150); pm_runtime_put(priv->dev); @@ -656,7 +668,16 @@ static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, return ret; } - if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) { + switch (mbus_config.type) { + case V4L2_MBUS_CSI2_CPHY: + if (!priv->cphy) + return -EINVAL; + break; + case V4L2_MBUS_CSI2_DPHY: + if (priv->cphy) + return -EINVAL; + break; + default: dev_err(priv->dev, "Unsupported media bus type %u\n", mbus_config.type); return -EINVAL; @@ -674,7 +695,7 @@ static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, return 0; } -static int rcsi2_start_receiver(struct rcar_csi2 *priv) +static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv) { const struct rcar_csi2_format *format; u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; @@ -821,7 +842,7 @@ static int rcsi2_start(struct rcar_csi2 *priv) if (ret < 0) return ret; - ret = rcsi2_start_receiver(priv); + ret = priv->info->start_receiver(priv); if (ret) { rcsi2_enter_standby(priv); return ret; @@ -1016,15 +1037,41 @@ static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, if (vep->base.port || vep->base.id) return -ENOTCONN; - if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) { - dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); - return -EINVAL; - } - priv->lanes = vep->bus.mipi_csi2.num_data_lanes; - if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { - dev_err(priv->dev, "Unsupported number of data-lanes: %u\n", - priv->lanes); + + switch (vep->bus_type) { + case V4L2_MBUS_CSI2_DPHY: + if (!priv->info->support_dphy) { + dev_err(priv->dev, "D-PHY not supported\n"); + return -EINVAL; + } + + if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { + dev_err(priv->dev, + "Unsupported number of data-lanes for D-PHY: %u\n", + priv->lanes); + return -EINVAL; + } + + priv->cphy = false; + break; + case V4L2_MBUS_CSI2_CPHY: + if (!priv->info->support_cphy) { + dev_err(priv->dev, "C-PHY not supported\n"); + return -EINVAL; + } + + if (priv->lanes != 3) { + dev_err(priv->dev, + "Unsupported number of data-lanes for C-PHY: %u\n", + priv->lanes); + return -EINVAL; + } + + priv->cphy = true; + break; + default: + dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); return -EINVAL; } @@ -1048,7 +1095,7 @@ static int rcsi2_parse_dt(struct rcar_csi2 *priv) struct fwnode_handle *fwnode; struct fwnode_handle *ep; struct v4l2_fwnode_endpoint v4l2_ep = { - .bus_type = V4L2_MBUS_CSI2_DPHY + .bus_type = V4L2_MBUS_UNKNOWN, }; int ret; @@ -1363,63 +1410,90 @@ static int rcsi2_probe_resources(struct rcar_csi2 *priv, static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_h3_v3h_m3n, .csi0clkfreqrange = 0x20, .num_channels = 4, .clear_ulps = true, + .support_dphy = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { .init_phtw = rcsi2_init_phtw_h3es2, + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_h3_v3h_m3n, .csi0clkfreqrange = 0x20, .num_channels = 4, .clear_ulps = true, + .support_dphy = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_m3w, .num_channels = 4, + .support_dphy = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_m3w, .num_channels = 4, + .support_dphy = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_h3_v3h_m3n, .csi0clkfreqrange = 0x20, .num_channels = 4, .clear_ulps = true, + .support_dphy = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { .init_phtw = rcsi2_init_phtw_v3m_e3, .phy_post_init = rcsi2_phy_post_init_v3m_e3, + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .num_channels = 4, + .support_dphy = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_h3_v3h_m3n, .csi0clkfreqrange = 0x20, .clear_ulps = true, + .support_dphy = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { .init_phtw = rcsi2_init_phtw_v3m_e3, .phy_post_init = rcsi2_phy_post_init_v3m_e3, + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .num_channels = 2, + .support_dphy = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { .init_phtw = rcsi2_init_phtw_v3u, + .start_receiver = rcsi2_start_receiver_gen3, + .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_v3u, .csi0clkfreqrange = 0x20, .clear_ulps = true, .use_isp = true, + .support_dphy = true, }; static const struct of_device_id rcar_csi2_of_table[] = { diff --git a/drivers/media/platform/renesas/rcar_fdp1.c b/drivers/media/platform/renesas/rcar_fdp1.c index f43e458590b8..ab39cd2201c8 100644 --- a/drivers/media/platform/renesas/rcar_fdp1.c +++ b/drivers/media/platform/renesas/rcar_fdp1.c @@ -254,6 +254,8 @@ MODULE_PARM_DESC(debug, "activate debug info"); /* Internal Data (HW Version) */ #define FD1_IP_INTDATA 0x0800 +/* R-Car Gen2 HW manual says zero, but actual value matches R-Car H3 ES1.x */ +#define FD1_IP_GEN2 0x02010101 #define FD1_IP_M3W 0x02010202 #define FD1_IP_H3 0x02010203 #define FD1_IP_M3N 0x02010204 @@ -2360,6 +2362,9 @@ static int fdp1_probe(struct platform_device *pdev) hw_version = fdp1_read(fdp1, FD1_IP_INTDATA); switch (hw_version) { + case FD1_IP_GEN2: + dprintk(fdp1, "FDP1 Version R-Car Gen2\n"); + break; case FD1_IP_M3W: dprintk(fdp1, "FDP1 Version R-Car M3-W\n"); break; diff --git a/drivers/media/platform/renesas/rcar_jpu.c b/drivers/media/platform/renesas/rcar_jpu.c index e7f604807825..2b8cb50f54de 100644 --- a/drivers/media/platform/renesas/rcar_jpu.c +++ b/drivers/media/platform/renesas/rcar_jpu.c @@ -28,6 +28,7 @@ #include <linux/spinlock.h> #include <linux/string.h> #include <linux/videodev2.h> +#include <media/jpeg.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-event.h> @@ -71,19 +72,6 @@ #define JPU_JPEG_DEFAULT_422_PIX_FMT V4L2_PIX_FMT_NV16M #define JPU_JPEG_DEFAULT_420_PIX_FMT V4L2_PIX_FMT_NV12M -/* JPEG markers */ -#define TEM 0x01 -#define SOF0 0xc0 -#define RST 0xd0 -#define SOI 0xd8 -#define EOI 0xd9 -#define DHP 0xde -#define DHT 0xc4 -#define COM 0xfe -#define DQT 0xdb -#define DRI 0xdd -#define APP0 0xe0 - #define JPU_RESET_TIMEOUT 100 /* ms */ #define JPU_JOB_TIMEOUT 300 /* ms */ #define JPU_MAX_QUALITY 4 @@ -330,26 +318,32 @@ static const u8 zigzag[] = { * Huffman tables; Padding with 0xff (33.3.27 R01UH0501EJ0100 Rev.1.00) */ #define JPU_JPEG_HDR_BLOB { \ - 0xff, SOI, 0xff, DQT, 0x00, JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_LUM, \ - [JPU_JPEG_QTBL_LUM_OFFSET ... \ + 0xff, JPEG_MARKER_SOI, 0xff, JPEG_MARKER_DQT, 0x00, \ + JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_LUM, \ + [JPU_JPEG_QTBL_LUM_OFFSET ... \ JPU_JPEG_QTBL_LUM_OFFSET + JPU_JPEG_QTBL_SIZE - 1] = 0x00, \ - 0xff, DQT, 0x00, JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_CHR, \ + 0xff, JPEG_MARKER_DQT, 0x00, JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_CHR, \ [JPU_JPEG_QTBL_CHR_OFFSET ... JPU_JPEG_QTBL_CHR_OFFSET + \ - JPU_JPEG_QTBL_SIZE - 1] = 0x00, 0xff, SOF0, 0x00, 0x11, 0x08, \ + JPU_JPEG_QTBL_SIZE - 1] = 0x00, \ + 0xff, JPEG_MARKER_SOF0, 0x00, 0x11, 0x08, \ [JPU_JPEG_HEIGHT_OFFSET ... JPU_JPEG_HEIGHT_OFFSET + 1] = 0x00, \ [JPU_JPEG_WIDTH_OFFSET ... JPU_JPEG_WIDTH_OFFSET + 1] = 0x00, \ 0x03, 0x01, [JPU_JPEG_SUBS_OFFSET] = 0x00, JPU_JPEG_LUM, \ 0x02, 0x11, JPU_JPEG_CHR, 0x03, 0x11, JPU_JPEG_CHR, \ - 0xff, DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, JPU_JPEG_LUM|JPU_JPEG_DC, \ + 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, \ + JPU_JPEG_LUM | JPU_JPEG_DC, \ [JPU_JPEG_HDCTBL_LUM_OFFSET ... \ JPU_JPEG_HDCTBL_LUM_OFFSET + JPU_JPEG_HDCTBL_SIZE - 1] = 0x00, \ - 0xff, DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, JPU_JPEG_LUM|JPU_JPEG_AC, \ + 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, \ + JPU_JPEG_LUM | JPU_JPEG_AC, \ [JPU_JPEG_HACTBL_LUM_OFFSET ... \ JPU_JPEG_HACTBL_LUM_OFFSET + JPU_JPEG_HACTBL_SIZE - 1] = 0x00, \ - 0xff, DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, JPU_JPEG_CHR|JPU_JPEG_DC, \ + 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, \ + JPU_JPEG_CHR | JPU_JPEG_DC, \ [JPU_JPEG_HDCTBL_CHR_OFFSET ... \ JPU_JPEG_HDCTBL_CHR_OFFSET + JPU_JPEG_HDCTBL_SIZE - 1] = 0x00, \ - 0xff, DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, JPU_JPEG_CHR|JPU_JPEG_AC, \ + 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, \ + JPU_JPEG_CHR | JPU_JPEG_AC, \ [JPU_JPEG_HACTBL_CHR_OFFSET ... \ JPU_JPEG_HACTBL_CHR_OFFSET + JPU_JPEG_HACTBL_SIZE - 1] = 0x00, \ [JPU_JPEG_PADDING_OFFSET ... JPU_JPEG_HDR_SIZE - 1] = 0xff \ @@ -613,7 +607,8 @@ static u8 jpu_parse_hdr(void *buffer, unsigned long size, unsigned int *width, * basic size check and EOI - we don't want to let JPU cross * buffer bounds in any case. Hope it's stopping by EOI. */ - if (size < JPU_JPEG_MIN_SIZE || *(u8 *)(buffer + size - 1) != EOI) + if (size < JPU_JPEG_MIN_SIZE || + *(u8 *)(buffer + size - 1) != JPEG_MARKER_EOI) return 0; for (;;) { @@ -624,14 +619,14 @@ static u8 jpu_parse_hdr(void *buffer, unsigned long size, unsigned int *width, c = get_byte(&jpeg_buffer); while (c == 0xff || c == 0); - if (!soi && c == SOI) { + if (!soi && c == JPEG_MARKER_SOI) { soi = true; continue; - } else if (soi != (c != SOI)) + } else if (soi != (c != JPEG_MARKER_SOI)) return 0; switch (c) { - case SOF0: /* SOF0: baseline JPEG */ + case JPEG_MARKER_SOF0: /* SOF0: baseline JPEG */ skip(&jpeg_buffer, 3); /* segment length and bpp */ if (get_word_be(&jpeg_buffer, height) || get_word_be(&jpeg_buffer, width) || @@ -640,11 +635,11 @@ static u8 jpu_parse_hdr(void *buffer, unsigned long size, unsigned int *width, skip(&jpeg_buffer, 1); return get_byte(&jpeg_buffer); - case DHT: - case DQT: - case COM: - case DRI: - case APP0 ... APP0 + 0x0f: + case JPEG_MARKER_DHT: + case JPEG_MARKER_DQT: + case JPEG_MARKER_COM: + case JPEG_MARKER_DRI: + case JPEG_MARKER_APP0 ... JPEG_MARKER_APP0 + 0x0f: if (get_word_be(&jpeg_buffer, &word)) return 0; skip(&jpeg_buffer, (long)word - 2); diff --git a/drivers/media/platform/renesas/renesas-ceu.c b/drivers/media/platform/renesas/renesas-ceu.c index 56b9c59cfda8..5c9e27f8c94b 100644 --- a/drivers/media/platform/renesas/renesas-ceu.c +++ b/drivers/media/platform/renesas/renesas-ceu.c @@ -702,12 +702,6 @@ static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count) /* Grab the first available buffer and trigger the first capture. */ buf = list_first_entry(&ceudev->capture, struct ceu_buffer, queue); - if (!buf) { - spin_unlock_irqrestore(&ceudev->lock, irqflags); - dev_dbg(ceudev->dev, - "No buffer available for capture.\n"); - goto error_stop_sensor; - } list_del(&buf->queue); ceudev->active = &buf->vb; @@ -722,9 +716,6 @@ static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count) return 0; -error_stop_sensor: - v4l2_subdev_call(v4l2_sd, video, s_stream, 0); - error_return_bufs: spin_lock_irqsave(&ceudev->lock, irqflags); list_for_each_entry(buf, &ceudev->capture, queue) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c index 30dad7383654..d6489c62b081 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c @@ -81,10 +81,10 @@ #define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x) (((x) & 0x3) << 4) #define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x) (((x) & 0x3) << 8) #define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x) (((x) & 0x3) << 12) -#define CSIDPHYSKW0_DEFAULT_SKW CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \ - CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \ - CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \ - CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1) +#define CSIDPHYSKW0_DEFAULT_SKW (CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \ + CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \ + CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \ + CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1)) #define VSRSTS_RETRIES 20 diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c index 67dcf22e5ba3..f1c532a5802a 100644 --- a/drivers/media/platform/rockchip/rga/rga.c +++ b/drivers/media/platform/rockchip/rga/rga.c @@ -76,10 +76,7 @@ static irqreturn_t rga_isr(int irq, void *prv) WARN_ON(!src); WARN_ON(!dst); - dst->timecode = src->timecode; - dst->vb2_buf.timestamp = src->vb2_buf.timestamp; - dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; - dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + v4l2_m2m_buf_copy_metadata(src, dst, true); v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE); v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE); @@ -726,10 +723,10 @@ static int rga_enable_clocks(struct rockchip_rga *rga) return 0; -err_disable_sclk: - clk_disable_unprepare(rga->sclk); err_disable_aclk: clk_disable_unprepare(rga->aclk); +err_disable_sclk: + clk_disable_unprepare(rga->sclk); return ret; } diff --git a/drivers/media/platform/samsung/exynos4-is/Kconfig b/drivers/media/platform/samsung/exynos4-is/Kconfig index da33faa7132e..7f9ba053dd8e 100644 --- a/drivers/media/platform/samsung/exynos4-is/Kconfig +++ b/drivers/media/platform/samsung/exynos4-is/Kconfig @@ -47,7 +47,7 @@ config VIDEO_S5P_MIPI_CSIS config VIDEO_EXYNOS_FIMC_LITE tristate "EXYNOS FIMC-LITE camera interface driver" depends on I2C - depends on SOC_EXYNOS4412 || SOC_EXYNOS5250 || COMPILE_TEST + depends on SOC_EXYNOS4212 || SOC_EXYNOS4412 || SOC_EXYNOS5250 || COMPILE_TEST depends on HAS_DMA select VIDEOBUF2_DMA_CONTIG select VIDEO_EXYNOS4_IS_COMMON diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-core.c b/drivers/media/platform/samsung/exynos4-is/fimc-core.c index a2034ade8b9e..976b4f747ad4 100644 --- a/drivers/media/platform/samsung/exynos4-is/fimc-core.c +++ b/drivers/media/platform/samsung/exynos4-is/fimc-core.c @@ -1128,7 +1128,7 @@ static const struct fimc_drvdata fimc_drvdata_exynos4210 = { .out_buf_count = 32, }; -/* EXYNOS4412 */ +/* EXYNOS4212, EXYNOS4412 */ static const struct fimc_drvdata fimc_drvdata_exynos4x12 = { .num_entities = 4, .lclk_frequency = 166000000UL, diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-lite.c b/drivers/media/platform/samsung/exynos4-is/fimc-lite.c index 24b3dda26714..c3146ae08447 100644 --- a/drivers/media/platform/samsung/exynos4-is/fimc-lite.c +++ b/drivers/media/platform/samsung/exynos4-is/fimc-lite.c @@ -1621,7 +1621,7 @@ static const struct dev_pm_ops fimc_lite_pm_ops = { NULL) }; -/* EXYNOS4412 */ +/* EXYNOS4212, EXYNOS4412 */ static struct flite_drvdata fimc_lite_drvdata_exynos4 = { .max_width = 8192, .max_height = 8192, diff --git a/drivers/media/platform/samsung/s5p-jpeg/jpeg-core.h b/drivers/media/platform/samsung/s5p-jpeg/jpeg-core.h index 5570c79f122f..4b665a3b630f 100644 --- a/drivers/media/platform/samsung/s5p-jpeg/jpeg-core.h +++ b/drivers/media/platform/samsung/s5p-jpeg/jpeg-core.h @@ -11,6 +11,7 @@ #define JPEG_CORE_H_ #include <linux/interrupt.h> +#include <media/jpeg.h> #include <media/v4l2-device.h> #include <media/v4l2-fh.h> #include <media/v4l2-ctrls.h> @@ -36,17 +37,6 @@ #define EXYNOS3250_IRQ_TIMEOUT 0x10000000 -/* a selection of JPEG markers */ -#define JPEG_MARKER_TEM 0x01 -#define JPEG_MARKER_SOF0 0xc0 -#define JPEG_MARKER_DHT 0xc4 -#define JPEG_MARKER_RST 0xd0 -#define JPEG_MARKER_SOI 0xd8 -#define JPEG_MARKER_EOI 0xd9 -#define JPEG_MARKER_SOS 0xda -#define JPEG_MARKER_DQT 0xdb -#define JPEG_MARKER_DHP 0xde - /* Flags that indicate a format can be used for capture/output */ #define SJPEG_FMT_FLAG_ENC_CAPTURE (1 << 0) #define SJPEG_FMT_FLAG_ENC_OUTPUT (1 << 1) diff --git a/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c b/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c index 45ade7210d26..5dc1f908b49b 100644 --- a/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c +++ b/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c @@ -16,8 +16,10 @@ #include <linux/dma-mapping.h> #include <linux/dvb/dmx.h> #include <linux/dvb/frontend.h> +#include <linux/err.h> #include <linux/errno.h> #include <linux/firmware.h> +#include <linux/gpio/consumer.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> @@ -135,7 +137,7 @@ static void channel_swdemux_tsklet(struct tasklet_struct *t) static int c8sectpfe_start_feed(struct dvb_demux_feed *dvbdmxfeed) { struct dvb_demux *demux = dvbdmxfeed->demux; - struct stdemux *stdemux = (struct stdemux *)demux->priv; + struct stdemux *stdemux = demux->priv; struct c8sectpfei *fei = stdemux->c8sectpfei; struct channel_info *channel; u32 tmp; @@ -256,7 +258,7 @@ static int c8sectpfe_stop_feed(struct dvb_demux_feed *dvbdmxfeed) { struct dvb_demux *demux = dvbdmxfeed->demux; - struct stdemux *stdemux = (struct stdemux *)demux->priv; + struct stdemux *stdemux = demux->priv; struct c8sectpfei *fei = stdemux->c8sectpfei; struct channel_info *channel; int idlereq; @@ -812,30 +814,23 @@ static int c8sectpfe_probe(struct platform_device *pdev) } of_node_put(i2c_bus); - tsin->rst_gpio = of_get_named_gpio(child, "reset-gpios", 0); - - ret = gpio_is_valid(tsin->rst_gpio); - if (!ret) { - dev_err(dev, - "reset gpio for tsin%d not valid (gpio=%d)\n", - tsin->tsin_id, tsin->rst_gpio); - ret = -EINVAL; - goto err_node_put; - } - - ret = devm_gpio_request_one(dev, tsin->rst_gpio, - GPIOF_OUT_INIT_LOW, "NIM reset"); + /* Acquire reset GPIO and activate it */ + tsin->rst_gpio = devm_fwnode_gpiod_get(dev, + of_fwnode_handle(child), + "reset", GPIOD_OUT_HIGH, + "NIM reset"); + ret = PTR_ERR_OR_ZERO(tsin->rst_gpio); if (ret && ret != -EBUSY) { - dev_err(dev, "Can't request tsin%d reset gpio\n" - , fei->channel_data[index]->tsin_id); + dev_err(dev, "Can't request tsin%d reset gpio\n", + fei->channel_data[index]->tsin_id); goto err_node_put; } if (!ret) { - /* toggle reset lines */ - gpio_direction_output(tsin->rst_gpio, 0); + /* wait for the chip to reset */ usleep_range(3500, 5000); - gpio_direction_output(tsin->rst_gpio, 1); + /* release the reset line */ + gpiod_set_value_cansleep(tsin->rst_gpio, 0); usleep_range(3000, 5000); } @@ -1173,7 +1168,7 @@ MODULE_DEVICE_TABLE(of, c8sectpfe_match); static struct platform_driver c8sectpfe_driver = { .driver = { .name = "c8sectpfe", - .of_match_table = of_match_ptr(c8sectpfe_match), + .of_match_table = c8sectpfe_match, }, .probe = c8sectpfe_probe, .remove_new = c8sectpfe_remove, diff --git a/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.h b/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.h index c9d6021904cd..bf377cc82225 100644 --- a/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.h +++ b/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.h @@ -16,6 +16,8 @@ #define C8SECTPFE_MAX_TSIN_CHAN 8 +struct gpio_desc; + struct channel_info { int tsin_id; @@ -25,7 +27,7 @@ struct channel_info { int i2c; int dvb_card; - int rst_gpio; + struct gpio_desc *rst_gpio; struct i2c_adapter *i2c_adapter; struct i2c_adapter *tuner_i2c; diff --git a/drivers/media/platform/st/sti/hva/hva-h264.c b/drivers/media/platform/st/sti/hva/hva-h264.c index 98cb00d2d868..196e631fa4b8 100644 --- a/drivers/media/platform/st/sti/hva/hva-h264.c +++ b/drivers/media/platform/st/sti/hva/hva-h264.c @@ -591,7 +591,7 @@ static int hva_h264_prepare_task(struct hva_ctx *pctx, { struct hva_dev *hva = ctx_to_hdev(pctx); struct device *dev = ctx_to_dev(pctx); - struct hva_h264_ctx *ctx = (struct hva_h264_ctx *)pctx->priv; + struct hva_h264_ctx *ctx = pctx->priv; struct hva_buffer *seq_info = ctx->seq_info; struct hva_buffer *fwd_ref_frame = ctx->ref_frame; struct hva_buffer *loc_rec_frame = ctx->rec_frame; @@ -984,7 +984,7 @@ err: static int hva_h264_close(struct hva_ctx *pctx) { - struct hva_h264_ctx *ctx = (struct hva_h264_ctx *)pctx->priv; + struct hva_h264_ctx *ctx = pctx->priv; struct device *dev = ctx_to_dev(pctx); if (ctx->seq_info) @@ -1007,8 +1007,8 @@ static int hva_h264_close(struct hva_ctx *pctx) static int hva_h264_encode(struct hva_ctx *pctx, struct hva_frame *frame, struct hva_stream *stream) { - struct hva_h264_ctx *ctx = (struct hva_h264_ctx *)pctx->priv; - struct hva_h264_task *task = (struct hva_h264_task *)ctx->task->vaddr; + struct hva_h264_ctx *ctx = pctx->priv; + struct hva_h264_task *task = ctx->task->vaddr; u32 stuffing_bytes = 0; int ret = 0; diff --git a/drivers/media/platform/verisilicon/Makefile b/drivers/media/platform/verisilicon/Makefile index ebd5ede7bef7..6ad2ef885920 100644 --- a/drivers/media/platform/verisilicon/Makefile +++ b/drivers/media/platform/verisilicon/Makefile @@ -18,6 +18,9 @@ hantro-vpu-y += \ rockchip_vpu2_hw_h264_dec.o \ rockchip_vpu2_hw_mpeg2_dec.o \ rockchip_vpu2_hw_vp8_dec.o \ + rockchip_vpu981_hw_av1_dec.o \ + rockchip_av1_filmgrain.o \ + rockchip_av1_entropymode.o \ hantro_jpeg.o \ hantro_h264.o \ hantro_hevc.o \ diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h index 2989ebc631cc..6523ffb74881 100644 --- a/drivers/media/platform/verisilicon/hantro.h +++ b/drivers/media/platform/verisilicon/hantro.h @@ -38,6 +38,7 @@ struct hantro_postproc_ops; #define HANTRO_H264_DECODER BIT(18) #define HANTRO_HEVC_DECODER BIT(19) #define HANTRO_VP9_DECODER BIT(20) +#define HANTRO_AV1_DECODER BIT(21) #define HANTRO_DECODERS 0xffff0000 /** @@ -111,6 +112,7 @@ struct hantro_variant { * @HANTRO_MODE_VP8_DEC: VP8 decoder. * @HANTRO_MODE_HEVC_DEC: HEVC decoder. * @HANTRO_MODE_VP9_DEC: VP9 decoder. + * @HANTRO_MODE_AV1_DEC: AV1 decoder */ enum hantro_codec_mode { HANTRO_MODE_NONE = -1, @@ -120,6 +122,7 @@ enum hantro_codec_mode { HANTRO_MODE_VP8_DEC, HANTRO_MODE_HEVC_DEC, HANTRO_MODE_VP9_DEC, + HANTRO_MODE_AV1_DEC, }; /* @@ -228,6 +231,8 @@ struct hantro_dev { * @ctrl_handler: Control handler used to register controls. * @jpeg_quality: User-specified JPEG compression quality. * @bit_depth: Bit depth of current frame + * @need_postproc: Set to true if the bitstream features require to + * use the post-processor. * * @codec_ops: Set of operations related to codec mode. * @postproc: Post-processing context. @@ -237,6 +242,7 @@ struct hantro_dev { * @vp8_dec: VP8-decoding context. * @hevc_dec: HEVC-decoding context. * @vp9_dec: VP9-decoding context. + * @av1_dec: AV1-decoding context. */ struct hantro_ctx { struct hantro_dev *dev; @@ -257,6 +263,7 @@ struct hantro_ctx { const struct hantro_codec_ops *codec_ops; struct hantro_postproc_ctx postproc; + bool need_postproc; /* Specific for particular codec modes. */ union { @@ -265,6 +272,7 @@ struct hantro_ctx { struct hantro_vp8_dec_hw_ctx vp8_dec; struct hantro_hevc_dec_hw_ctx hevc_dec; struct hantro_vp9_dec_hw_ctx vp9_dec; + struct hantro_av1_dec_hw_ctx av1_dec; }; }; diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 09c74a573ddb..c0a368bacf88 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -275,7 +275,13 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) /* We only support profile 0 */ if (dec_params->profile != 0) return -EINVAL; + } else if (ctrl->id == V4L2_CID_STATELESS_AV1_SEQUENCE) { + const struct v4l2_ctrl_av1_sequence *sequence = ctrl->p_new.p_av1_sequence; + + if (sequence->bit_depth != 8 && sequence->bit_depth != 10) + return -EINVAL; } + return 0; } @@ -313,7 +319,7 @@ static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl) if (ctx->bit_depth == bit_depth) return 0; - return hantro_reset_raw_fmt(ctx, bit_depth); + return hantro_reset_raw_fmt(ctx, bit_depth, HANTRO_AUTO_POSTPROC); } default: return -EINVAL; @@ -337,7 +343,37 @@ static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) if (ctx->bit_depth == bit_depth) return 0; - return hantro_reset_raw_fmt(ctx, bit_depth); + return hantro_reset_raw_fmt(ctx, bit_depth, HANTRO_AUTO_POSTPROC); + } + default: + return -EINVAL; + } + + return 0; +} + +static int hantro_av1_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hantro_ctx *ctx; + + ctx = container_of(ctrl->handler, + struct hantro_ctx, ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_STATELESS_AV1_SEQUENCE: + { + int bit_depth = ctrl->p_new.p_av1_sequence->bit_depth; + bool need_postproc = HANTRO_AUTO_POSTPROC; + + if (ctrl->p_new.p_av1_sequence->flags + & V4L2_AV1_SEQUENCE_FLAG_FILM_GRAIN_PARAMS_PRESENT) + need_postproc = HANTRO_FORCE_POSTPROC; + + if (ctx->bit_depth == bit_depth && + ctx->need_postproc == need_postproc) + return 0; + + return hantro_reset_raw_fmt(ctx, bit_depth, need_postproc); } default: return -EINVAL; @@ -363,6 +399,11 @@ static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { .s_ctrl = hantro_hevc_s_ctrl, }; +static const struct v4l2_ctrl_ops hantro_av1_ctrl_ops = { + .try_ctrl = hantro_try_ctrl, + .s_ctrl = hantro_av1_s_ctrl, +}; + #define HANTRO_JPEG_ACTIVE_MARKERS (V4L2_JPEG_ACTIVE_MARKER_APP0 | \ V4L2_JPEG_ACTIVE_MARKER_COM | \ V4L2_JPEG_ACTIVE_MARKER_DQT | \ @@ -525,6 +566,28 @@ static const struct hantro_ctrl controls[] = { .cfg = { .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, }, + }, { + .codec = HANTRO_AV1_DECODER, + .cfg = { + .id = V4L2_CID_STATELESS_AV1_FRAME, + }, + }, { + .codec = HANTRO_AV1_DECODER, + .cfg = { + .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY, + .dims = { V4L2_AV1_MAX_TILE_COUNT }, + }, + }, { + .codec = HANTRO_AV1_DECODER, + .cfg = { + .id = V4L2_CID_STATELESS_AV1_SEQUENCE, + .ops = &hantro_av1_ctrl_ops, + }, + }, { + .codec = HANTRO_AV1_DECODER, + .cfg = { + .id = V4L2_CID_STATELESS_AV1_FILM_GRAIN, + }, }, }; @@ -656,6 +719,7 @@ static const struct of_device_id of_hantro_match[] = { { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, + { .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, }, #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, diff --git a/drivers/media/platform/verisilicon/hantro_hevc.c b/drivers/media/platform/verisilicon/hantro_hevc.c index 9383fb7081f6..2c14330bc562 100644 --- a/drivers/media/platform/verisilicon/hantro_hevc.c +++ b/drivers/media/platform/verisilicon/hantro_hevc.c @@ -109,7 +109,7 @@ static int tile_buffer_reallocate(struct hantro_ctx *ctx) &hevc_dec->tile_filter.dma, GFP_KERNEL); if (!hevc_dec->tile_filter.cpu) - goto err_free_tile_buffers; + return -ENOMEM; hevc_dec->tile_filter.size = size; size = (VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8; @@ -125,31 +125,26 @@ static int tile_buffer_reallocate(struct hantro_ctx *ctx) &hevc_dec->tile_bsd.dma, GFP_KERNEL); if (!hevc_dec->tile_bsd.cpu) - goto err_free_tile_buffers; + goto err_free_sao_buffers; hevc_dec->tile_bsd.size = size; hevc_dec->num_tile_cols_allocated = num_tile_cols; return 0; -err_free_tile_buffers: - if (hevc_dec->tile_filter.cpu) - dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, - hevc_dec->tile_filter.cpu, - hevc_dec->tile_filter.dma); - hevc_dec->tile_filter.cpu = NULL; - +err_free_sao_buffers: if (hevc_dec->tile_sao.cpu) dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, hevc_dec->tile_sao.cpu, hevc_dec->tile_sao.dma); hevc_dec->tile_sao.cpu = NULL; - if (hevc_dec->tile_bsd.cpu) - dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size, - hevc_dec->tile_bsd.cpu, - hevc_dec->tile_bsd.dma); - hevc_dec->tile_bsd.cpu = NULL; +err_free_tile_buffers: + if (hevc_dec->tile_filter.cpu) + dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, + hevc_dec->tile_filter.cpu, + hevc_dec->tile_filter.dma); + hevc_dec->tile_filter.cpu = NULL; return -ENOMEM; } diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index e83f0c523a30..7f33f7b07ce4 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -15,6 +15,9 @@ #include <media/v4l2-vp9.h> #include <media/videobuf2-core.h> +#include "rockchip_av1_entropymode.h" +#include "rockchip_av1_filmgrain.h" + #define DEC_8190_ALIGN_MASK 0x07U #define MB_DIM 16 @@ -35,6 +38,8 @@ #define NUM_REF_PICTURES (V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1) +#define AV1_MAX_FRAME_BUF_COUNT (V4L2_AV1_TOTAL_REFS_PER_FRAME + 1) + struct hantro_dev; struct hantro_ctx; struct hantro_buf; @@ -248,6 +253,84 @@ struct hantro_vp9_dec_hw_ctx { }; /** + * struct hantro_av1_dec_ctrls + * @sequence: AV1 Sequence + * @tile_group_entry: AV1 Tile Group entry + * @frame: AV1 Frame Header OBU + * @film_grain: AV1 Film Grain + */ +struct hantro_av1_dec_ctrls { + const struct v4l2_ctrl_av1_sequence *sequence; + const struct v4l2_ctrl_av1_tile_group_entry *tile_group_entry; + const struct v4l2_ctrl_av1_frame *frame; + const struct v4l2_ctrl_av1_film_grain *film_grain; +}; + +struct hantro_av1_frame_ref { + int width; + int height; + int mi_cols; + int mi_rows; + u64 timestamp; + enum v4l2_av1_frame_type frame_type; + bool used; + u32 order_hint; + u32 order_hints[V4L2_AV1_TOTAL_REFS_PER_FRAME]; + struct vb2_v4l2_buffer *vb2_ref; +}; + +/** + * struct hantro_av1_dec_hw_ctx + * @db_data_col: db tile col data buffer + * @db_ctrl_col: db tile col ctrl buffer + * @cdef_col: cdef tile col buffer + * @sr_col: sr tile col buffer + * @lr_col: lr tile col buffer + * @global_model: global model buffer + * @tile_info: tile info buffer + * @segment: segmentation info buffer + * @film_grain: film grain buffer + * @prob_tbl: probability table + * @prob_tbl_out: probability table output + * @tile_buf: tile buffer + * @ctrls: V4L2 controls attached to a run + * @frame_refs: reference frames info slots + * @ref_frame_sign_bias: array of sign bias + * @num_tile_cols_allocated: number of allocated tiles + * @cdfs: current probabilities structure + * @cdfs_ndvc: current mv probabilities structure + * @default_cdfs: default probabilities structure + * @default_cdfs_ndvc: default mv probabilties structure + * @cdfs_last: stored probabilities structures + * @cdfs_last_ndvc: stored mv probabilities structures + * @current_frame_index: index of the current in frame_refs array + */ +struct hantro_av1_dec_hw_ctx { + struct hantro_aux_buf db_data_col; + struct hantro_aux_buf db_ctrl_col; + struct hantro_aux_buf cdef_col; + struct hantro_aux_buf sr_col; + struct hantro_aux_buf lr_col; + struct hantro_aux_buf global_model; + struct hantro_aux_buf tile_info; + struct hantro_aux_buf segment; + struct hantro_aux_buf film_grain; + struct hantro_aux_buf prob_tbl; + struct hantro_aux_buf prob_tbl_out; + struct hantro_aux_buf tile_buf; + struct hantro_av1_dec_ctrls ctrls; + struct hantro_av1_frame_ref frame_refs[AV1_MAX_FRAME_BUF_COUNT]; + u32 ref_frame_sign_bias[V4L2_AV1_TOTAL_REFS_PER_FRAME]; + unsigned int num_tile_cols_allocated; + struct av1cdfs *cdfs; + struct mvcdfs *cdfs_ndvc; + struct av1cdfs default_cdfs; + struct mvcdfs default_cdfs_ndvc; + struct av1cdfs cdfs_last[NUM_REF_FRAMES]; + struct mvcdfs cdfs_last_ndvc[NUM_REF_FRAMES]; + int current_frame_index; +}; +/** * struct hantro_postproc_ctx * * @dec_q: References buffers, in decoder format. @@ -320,11 +403,13 @@ extern const struct hantro_variant rk3328_vpu_variant; extern const struct hantro_variant rk3399_vpu_variant; extern const struct hantro_variant rk3568_vepu_variant; extern const struct hantro_variant rk3568_vpu_variant; +extern const struct hantro_variant rk3588_vpu981_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; +extern const struct hantro_postproc_ops rockchip_vpu981_postproc_ops; extern const u32 hantro_vp8_dec_mc_filter[8][6]; @@ -361,6 +446,10 @@ void hantro_hevc_ref_init(struct hantro_ctx *ctx); dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc); int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr); +int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx); +void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx); +int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx); +void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx); static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension) { @@ -417,6 +506,19 @@ hantro_hevc_mv_size(unsigned int width, unsigned int height) return width * height / 16; } +static inline unsigned short hantro_av1_num_sbs(unsigned short dimension) +{ + return DIV_ROUND_UP(dimension, 64); +} + +static inline size_t +hantro_av1_mv_size(unsigned int width, unsigned int height) +{ + size_t num_sbs = hantro_av1_num_sbs(width) * hantro_av1_num_sbs(height); + + return ALIGN(num_sbs * 384, 16) * 2 + 512; +} + int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx); int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx); void hantro_mpeg2_dec_copy_qtable(u8 *qtable, diff --git a/drivers/media/platform/verisilicon/hantro_postproc.c b/drivers/media/platform/verisilicon/hantro_postproc.c index 6437423ccf3a..c977d64105b1 100644 --- a/drivers/media/platform/verisilicon/hantro_postproc.c +++ b/drivers/media/platform/verisilicon/hantro_postproc.c @@ -57,6 +57,10 @@ bool hantro_needs_postproc(const struct hantro_ctx *ctx, { if (ctx->is_encoder) return false; + + if (ctx->need_postproc) + return true; + return fmt->postprocessed; } @@ -197,7 +201,7 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) unsigned int i, buf_size; /* this should always pick native format */ - fmt = hantro_get_default_fmt(ctx, false, ctx->bit_depth); + fmt = hantro_get_default_fmt(ctx, false, ctx->bit_depth, HANTRO_AUTO_POSTPROC); if (!fmt) return -EINVAL; v4l2_fill_pixfmt_mp(&pix_mp, fmt->fourcc, ctx->src_fmt.width, @@ -213,6 +217,9 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) buf_size += hantro_hevc_mv_size(pix_mp.width, pix_mp.height); + else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_AV1_FRAME) + buf_size += hantro_av1_mv_size(pix_mp.width, + pix_mp.height); for (i = 0; i < num_buffers; ++i) { struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/media/platform/verisilicon/hantro_v4l2.c index 61cfaaf4e927..e871c078dd59 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.c +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c @@ -31,15 +31,21 @@ #define HANTRO_DEFAULT_BIT_DEPTH 8 static int hantro_set_fmt_out(struct hantro_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp); + struct v4l2_pix_format_mplane *pix_mp, + bool need_postproc); static int hantro_set_fmt_cap(struct hantro_ctx *ctx, struct v4l2_pix_format_mplane *pix_mp); static const struct hantro_fmt * -hantro_get_formats(const struct hantro_ctx *ctx, unsigned int *num_fmts) +hantro_get_formats(const struct hantro_ctx *ctx, unsigned int *num_fmts, bool need_postproc) { const struct hantro_fmt *formats; + if (need_postproc) { + *num_fmts = 0; + return NULL; + } + if (ctx->is_encoder) { formats = ctx->dev->variant->enc_fmts; *num_fmts = ctx->dev->variant->num_enc_fmts; @@ -71,6 +77,7 @@ int hantro_get_format_depth(u32 fourcc) switch (fourcc) { case V4L2_PIX_FMT_P010: case V4L2_PIX_FMT_P010_4L4: + case V4L2_PIX_FMT_NV15_4L4: return 10; default: return 8; @@ -85,6 +92,10 @@ hantro_check_depth_match(const struct hantro_fmt *fmt, int bit_depth) if (!fmt->match_depth && !fmt->postprocessed) return true; + /* 0 means default depth, which is 8 */ + if (!bit_depth) + bit_depth = HANTRO_DEFAULT_BIT_DEPTH; + fmt_depth = hantro_get_format_depth(fmt->fourcc); /* @@ -103,7 +114,7 @@ hantro_find_format(const struct hantro_ctx *ctx, u32 fourcc) const struct hantro_fmt *formats; unsigned int i, num_fmts; - formats = hantro_get_formats(ctx, &num_fmts); + formats = hantro_get_formats(ctx, &num_fmts, HANTRO_AUTO_POSTPROC); for (i = 0; i < num_fmts; i++) if (formats[i].fourcc == fourcc) return &formats[i]; @@ -116,18 +127,28 @@ hantro_find_format(const struct hantro_ctx *ctx, u32 fourcc) } const struct hantro_fmt * -hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream, int bit_depth) +hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream, + int bit_depth, bool need_postproc) { const struct hantro_fmt *formats; unsigned int i, num_fmts; - formats = hantro_get_formats(ctx, &num_fmts); + formats = hantro_get_formats(ctx, &num_fmts, need_postproc); + for (i = 0; i < num_fmts; i++) { + if (bitstream == (formats[i].codec_mode != + HANTRO_MODE_NONE) && + hantro_check_depth_match(&formats[i], bit_depth)) + return &formats[i]; + } + + formats = hantro_get_postproc_formats(ctx, &num_fmts); for (i = 0; i < num_fmts; i++) { if (bitstream == (formats[i].codec_mode != HANTRO_MODE_NONE) && hantro_check_depth_match(&formats[i], bit_depth)) return &formats[i]; } + return NULL; } @@ -194,7 +215,7 @@ static int vidioc_enum_fmt(struct file *file, void *priv, */ skip_mode_none = capture == ctx->is_encoder; - formats = hantro_get_formats(ctx, &num_fmts); + formats = hantro_get_formats(ctx, &num_fmts, HANTRO_AUTO_POSTPROC); for (i = 0; i < num_fmts; i++) { bool mode_none = formats[i].codec_mode == HANTRO_MODE_NONE; fmt = &formats[i]; @@ -289,7 +310,7 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx, fmt = hantro_find_format(ctx, pix_mp->pixelformat); if (!fmt) { - fmt = hantro_get_default_fmt(ctx, coded, HANTRO_DEFAULT_BIT_DEPTH); + fmt = hantro_get_default_fmt(ctx, coded, HANTRO_DEFAULT_BIT_DEPTH, HANTRO_AUTO_POSTPROC); pix_mp->pixelformat = fmt->fourcc; } @@ -328,6 +349,11 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx, pix_mp->plane_fmt[0].sizeimage += hantro_hevc_mv_size(pix_mp->width, pix_mp->height); + else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_AV1_FRAME && + !hantro_needs_postproc(ctx, fmt)) + pix_mp->plane_fmt[0].sizeimage += + hantro_av1_mv_size(pix_mp->width, + pix_mp->height); } else if (!pix_mp->plane_fmt[0].sizeimage) { /* * For coded formats the application can specify @@ -373,7 +399,7 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx) const struct hantro_fmt *vpu_fmt; struct v4l2_pix_format_mplane fmt; - vpu_fmt = hantro_get_default_fmt(ctx, true, HANTRO_DEFAULT_BIT_DEPTH); + vpu_fmt = hantro_get_default_fmt(ctx, true, HANTRO_DEFAULT_BIT_DEPTH, HANTRO_AUTO_POSTPROC); if (!vpu_fmt) return; @@ -383,17 +409,17 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx) if (ctx->is_encoder) hantro_set_fmt_cap(ctx, &fmt); else - hantro_set_fmt_out(ctx, &fmt); + hantro_set_fmt_out(ctx, &fmt, HANTRO_AUTO_POSTPROC); } int -hantro_reset_raw_fmt(struct hantro_ctx *ctx, int bit_depth) +hantro_reset_raw_fmt(struct hantro_ctx *ctx, int bit_depth, bool need_postproc) { const struct hantro_fmt *raw_vpu_fmt; struct v4l2_pix_format_mplane raw_fmt, *encoded_fmt; int ret; - raw_vpu_fmt = hantro_get_default_fmt(ctx, false, bit_depth); + raw_vpu_fmt = hantro_get_default_fmt(ctx, false, bit_depth, need_postproc); if (!raw_vpu_fmt) return -EINVAL; @@ -408,12 +434,14 @@ hantro_reset_raw_fmt(struct hantro_ctx *ctx, int bit_depth) raw_fmt.width = encoded_fmt->width; raw_fmt.height = encoded_fmt->height; if (ctx->is_encoder) - ret = hantro_set_fmt_out(ctx, &raw_fmt); + ret = hantro_set_fmt_out(ctx, &raw_fmt, need_postproc); else ret = hantro_set_fmt_cap(ctx, &raw_fmt); - if (!ret) + if (!ret) { ctx->bit_depth = bit_depth; + ctx->need_postproc = need_postproc; + } return ret; } @@ -421,7 +449,7 @@ hantro_reset_raw_fmt(struct hantro_ctx *ctx, int bit_depth) void hantro_reset_fmts(struct hantro_ctx *ctx) { hantro_reset_encoded_fmt(ctx); - hantro_reset_raw_fmt(ctx, HANTRO_DEFAULT_BIT_DEPTH); + hantro_reset_raw_fmt(ctx, HANTRO_DEFAULT_BIT_DEPTH, HANTRO_AUTO_POSTPROC); } static void @@ -468,7 +496,8 @@ hantro_update_requires_hold_capture_buf(struct hantro_ctx *ctx, u32 fourcc) } static int hantro_set_fmt_out(struct hantro_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp) + struct v4l2_pix_format_mplane *pix_mp, + bool need_postproc) { struct vb2_queue *vq; int ret; @@ -521,7 +550,9 @@ static int hantro_set_fmt_out(struct hantro_ctx *ctx, * changes to the raw format. */ if (!ctx->is_encoder) - hantro_reset_raw_fmt(ctx, hantro_get_format_depth(pix_mp->pixelformat)); + hantro_reset_raw_fmt(ctx, + hantro_get_format_depth(pix_mp->pixelformat), + need_postproc); /* Colorimetry information are always propagated. */ ctx->dst_fmt.colorspace = pix_mp->colorspace; @@ -584,7 +615,7 @@ static int hantro_set_fmt_cap(struct hantro_ctx *ctx, * changes to the raw format. */ if (ctx->is_encoder) - hantro_reset_raw_fmt(ctx, HANTRO_DEFAULT_BIT_DEPTH); + hantro_reset_raw_fmt(ctx, HANTRO_DEFAULT_BIT_DEPTH, HANTRO_AUTO_POSTPROC); /* Colorimetry information are always propagated. */ ctx->src_fmt.colorspace = pix_mp->colorspace; @@ -604,7 +635,7 @@ static int hantro_set_fmt_cap(struct hantro_ctx *ctx, static int vidioc_s_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f) { - return hantro_set_fmt_out(fh_to_ctx(priv), &f->fmt.pix_mp); + return hantro_set_fmt_out(fh_to_ctx(priv), &f->fmt.pix_mp, HANTRO_AUTO_POSTPROC); } static int diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.h b/drivers/media/platform/verisilicon/hantro_v4l2.h index 9ea2fef57dcd..fca7e3a690e5 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.h +++ b/drivers/media/platform/verisilicon/hantro_v4l2.h @@ -18,13 +18,17 @@ #include "hantro.h" +#define HANTRO_FORCE_POSTPROC true +#define HANTRO_AUTO_POSTPROC false + extern const struct v4l2_ioctl_ops hantro_ioctl_ops; extern const struct vb2_ops hantro_queue_ops; -int hantro_reset_raw_fmt(struct hantro_ctx *ctx, int bit_depth); +int hantro_reset_raw_fmt(struct hantro_ctx *ctx, int bit_depth, bool need_postproc); void hantro_reset_fmts(struct hantro_ctx *ctx); int hantro_get_format_depth(u32 fourcc); const struct hantro_fmt * -hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream, int bit_depth); +hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream, + int bit_depth, bool need_postproc); #endif /* HANTRO_V4L2_H_ */ diff --git a/drivers/media/platform/verisilicon/rockchip_av1_entropymode.c b/drivers/media/platform/verisilicon/rockchip_av1_entropymode.c new file mode 100644 index 000000000000..b1ae72ad675e --- /dev/null +++ b/drivers/media/platform/verisilicon/rockchip_av1_entropymode.c @@ -0,0 +1,4424 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (c) 2016, Alliance for Open Media. All rights reserved + * + * This source code is subject to the terms of the BSD 2 Clause License and + * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License + * was not distributed with this source code in the LICENSE file, you can + * obtain it at www.aomedia.org/license/software. If the Alliance for Open + * Media Patent License 1.0 was not distributed with this source code in the + * PATENTS file, you can obtain it at www.aomedia.org/license/patent. + */ + +#include "hantro.h" +#include "rockchip_av1_entropymode.h" + +#define AOM_ICDF ICDF +#define AOM_CDF2(a0) AOM_ICDF(a0) +#define AOM_CDF3(a0, a1) \ + AOM_ICDF(a0), AOM_ICDF(a1) +#define AOM_CDF4(a0, a1, a2) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2) +#define AOM_CDF5(a0, a1, a2, a3) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3) +#define AOM_CDF6(a0, a1, a2, a3, a4) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), AOM_ICDF(a4) +#define AOM_CDF7(a0, a1, a2, a3, a4, a5) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), \ + AOM_ICDF(a3), AOM_ICDF(a4), AOM_ICDF(a5) +#define AOM_CDF8(a0, a1, a2, a3, a4, a5, a6) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), \ + AOM_ICDF(a3), AOM_ICDF(a4), AOM_ICDF(a5), AOM_ICDF(a6) +#define AOM_CDF9(a0, a1, a2, a3, a4, a5, a6, a7) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), \ + AOM_ICDF(a4), AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7) +#define AOM_CDF10(a0, a1, a2, a3, a4, a5, a6, a7, a8) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), \ + AOM_ICDF(a4), AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8) +#define AOM_CDF11(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), AOM_ICDF(a4), \ + AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9) +#define AOM_CDF12(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), AOM_ICDF(a4), AOM_ICDF(a5), \ + AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), AOM_ICDF(a10) +#define AOM_CDF13(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), AOM_ICDF(a4), AOM_ICDF(a5), \ + AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), AOM_ICDF(a10), AOM_ICDF(a11) +#define AOM_CDF14(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), AOM_ICDF(a4), \ + AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), \ + AOM_ICDF(a10), AOM_ICDF(a11), AOM_ICDF(a12) +#define AOM_CDF15(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), AOM_ICDF(a4), \ + AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), \ + AOM_ICDF(a10), AOM_ICDF(a11), AOM_ICDF(a12), AOM_ICDF(a13) +#define AOM_CDF16(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) \ + AOM_ICDF(a0), AOM_ICDF(a1), AOM_ICDF(a2), AOM_ICDF(a3), AOM_ICDF(a4), \ + AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), \ + AOM_ICDF(a10), AOM_ICDF(a11), AOM_ICDF(a12), AOM_ICDF(a13), AOM_ICDF(a14) + +static const u16 default_kf_y_mode_cdf + [KF_MODE_CONTEXTS][KF_MODE_CONTEXTS][CDF_SIZE(AV1_INTRA_MODES)] = { + { + { + AOM_CDF13(15588, 17027, 19338, 20218, 20682, 21110, + 21825, 23244, 24189, 28165, 29093, 30466) + }, + { + AOM_CDF13(12016, 18066, 19516, 20303, 20719, 21444, + 21888, 23032, 24434, 28658, 30172, 31409) + }, + { + AOM_CDF13(10052, 10771, 22296, 22788, 23055, 23239, + 24133, 25620, 26160, 29336, 29929, 31567) + }, + { + AOM_CDF13(14091, 15406, 16442, 18808, 19136, 19546, + 19998, 22096, 24746, 29585, 30958, 32462) + }, + { + AOM_CDF13(12122, 13265, 15603, 16501, 18609, 20033, + 22391, 25583, 26437, 30261, 31073, 32475) + } + }, + { + { + AOM_CDF13(10023, 19585, 20848, 21440, 21832, 22760, + 23089, 24023, 25381, 29014, 30482, 31436) + }, + { + AOM_CDF13(5983, 24099, 24560, 24886, 25066, 25795, + 25913, 26423, 27610, 29905, 31276, 31794) + }, + { + AOM_CDF13(7444, 12781, 20177, 20728, 21077, 21607, + 22170, 23405, 24469, 27915, 29090, 30492) + }, + { + AOM_CDF13(8537, 14689, 15432, 17087, 17408, 18172, + 18408, 19825, 24649, 29153, 31096, 32210) + }, + { + AOM_CDF13(7543, 14231, 15496, 16195, 17905, 20717, + 21984, 24516, 26001, 29675, 30981, 31994) + } + }, + { + { + AOM_CDF13(12613, 13591, 21383, 22004, 22312, 22577, + 23401, 25055, 25729, 29538, 30305, 32077) + }, + { + AOM_CDF13(9687, 13470, 18506, 19230, 19604, 20147, + 20695, 22062, 23219, 27743, 29211, 30907) + }, + { + AOM_CDF13(6183, 6505, 26024, 26252, 26366, 26434, + 27082, 28354, 28555, 30467, 30794, 32086) + }, + { + AOM_CDF13(10718, 11734, 14954, 17224, 17565, 17924, + 18561, 21523, 23878, 28975, 30287, 32252) + }, + { + AOM_CDF13(9194, 9858, 16501, 17263, 18424, 19171, + 21563, 25961, 26561, 30072, 30737, 32463) + } + }, + { + { + AOM_CDF13(12602, 14399, 15488, 18381, 18778, 19315, + 19724, 21419, 25060, 29696, 30917, 32409) + }, + { + AOM_CDF13(8203, 13821, 14524, 17105, 17439, 18131, + 18404, 19468, 25225, 29485, 31158, 32342) + }, + { + AOM_CDF13(8451, 9731, 15004, 17643, 18012, 18425, + 19070, 21538, 24605, 29118, 30078, 32018) + }, + { + AOM_CDF13(7714, 9048, 9516, 16667, 16817, 16994, + 17153, 18767, 26743, 30389, 31536, 32528) + }, + { + AOM_CDF13(8843, 10280, 11496, 15317, 16652, 17943, + 19108, 22718, 25769, 29953, 30983, 32485) + } + }, + { + { + AOM_CDF13(12578, 13671, 15979, 16834, 19075, 20913, + 22989, 25449, 26219, 30214, 31150, 32477) + }, + { + AOM_CDF13(9563, 13626, 15080, 15892, 17756, 20863, + 22207, 24236, 25380, 29653, 31143, 32277) + }, + { + AOM_CDF13(8356, 8901, 17616, 18256, 19350, 20106, + 22598, 25947, 26466, 29900, 30523, 32261) + }, + { + AOM_CDF13(10835, 11815, 13124, 16042, 17018, 18039, + 18947, 22753, 24615, 29489, 30883, 32482) + }, + { + AOM_CDF13(7618, 8288, 9859, 10509, 15386, 18657, + 22903, 28776, 29180, 31355, 31802, 32593) + } + } +}; + +static const u16 default_angle_delta_cdf[DIRECTIONAL_MODES] + [CDF_SIZE(2 * MAX_ANGLE_DELTA + 1)] = { + { AOM_CDF7(2180, 5032, 7567, 22776, 26989, 30217) }, + { AOM_CDF7(2301, 5608, 8801, 23487, 26974, 30330) }, + { AOM_CDF7(3780, 11018, 13699, 19354, 23083, 31286) }, + { AOM_CDF7(4581, 11226, 15147, 17138, 21834, 28397) }, + { AOM_CDF7(1737, 10927, 14509, 19588, 22745, 28823) }, + { AOM_CDF7(2664, 10176, 12485, 17650, 21600, 30495) }, + { AOM_CDF7(2240, 11096, 15453, 20341, 22561, 28917) }, + { AOM_CDF7(3605, 10428, 12459, 17676, 21244, 30655) } +}; + +static const u16 default_if_y_mode_cdf[BLOCK_SIZE_GROUPS][CDF_SIZE(AV1_INTRA_MODES)] = { + { + AOM_CDF13(22801, 23489, 24293, 24756, 25601, 26123, + 26606, 27418, 27945, 29228, 29685, 30349) + }, + { + AOM_CDF13(18673, 19845, 22631, 23318, 23950, 24649, + 25527, 27364, 28152, 29701, 29984, 30852) + }, + { + AOM_CDF13(19770, 20979, 23396, 23939, 24241, 24654, + 25136, 27073, 27830, 29360, 29730, 30659) + }, + { + AOM_CDF13(20155, 21301, 22838, 23178, 23261, 23533, + 23703, 24804, 25352, 26575, 27016, 28049) + } +}; + +static const u16 default_uv_mode_cdf[CFL_ALLOWED_TYPES] + [AV1_INTRA_MODES][CDF_SIZE(UV_INTRA_MODES)] = { + { + { + AOM_CDF13(22631, 24152, 25378, 25661, 25986, 26520, + 27055, 27923, 28244, 30059, 30941, 31961) + }, + { + AOM_CDF13(9513, 26881, 26973, 27046, 27118, 27664, + 27739, 27824, 28359, 29505, 29800, 31796) + }, + { + AOM_CDF13(9845, 9915, 28663, 28704, 28757, 28780, + 29198, 29822, 29854, 30764, 31777, 32029) + }, + { + AOM_CDF13(13639, 13897, 14171, 25331, 25606, 25727, + 25953, 27148, 28577, 30612, 31355, 32493) + }, + { + AOM_CDF13(9764, 9835, 9930, 9954, 25386, 27053, + 27958, 28148, 28243, 31101, 31744, 32363) + }, + { + AOM_CDF13(11825, 13589, 13677, 13720, 15048, 29213, + 29301, 29458, 29711, 31161, 31441, 32550) + }, + { + AOM_CDF13(14175, 14399, 16608, 16821, 17718, 17775, + 28551, 30200, 30245, 31837, 32342, 32667) + }, + { + AOM_CDF13(12885, 13038, 14978, 15590, 15673, 15748, + 16176, 29128, 29267, 30643, 31961, 32461) + }, + { + AOM_CDF13(12026, 13661, 13874, 15305, 15490, 15726, + 15995, 16273, 28443, 30388, 30767, 32416) + }, + { + AOM_CDF13(19052, 19840, 20579, 20916, 21150, 21467, + 21885, 22719, 23174, 28861, 30379, 32175) + }, + { + AOM_CDF13(18627, 19649, 20974, 21219, 21492, 21816, + 22199, 23119, 23527, 27053, 31397, 32148) + }, + { + AOM_CDF13(17026, 19004, 19997, 20339, 20586, 21103, + 21349, 21907, 22482, 25896, 26541, 31819) + }, + { + AOM_CDF13(12124, 13759, 14959, 14992, 15007, 15051, + 15078, 15166, 15255, 15753, 16039, 16606) + } + }, + { + { + AOM_CDF14(10407, 11208, 12900, 13181, 13823, 14175, + 14899, 15656, 15986, 20086, 20995, 22455, + 24212) + }, + { + AOM_CDF14(4532, 19780, 20057, 20215, 20428, 21071, + 21199, 21451, 22099, 24228, 24693, 27032, + 29472) + }, + { + AOM_CDF14(5273, 5379, 20177, 20270, 20385, 20439, + 20949, 21695, 21774, 23138, 24256, 24703, + 26679) + }, + { + AOM_CDF14(6740, 7167, 7662, 14152, 14536, 14785, + 15034, 16741, 18371, 21520, 22206, 23389, + 24182) + }, + { + AOM_CDF14(4987, 5368, 5928, 6068, 19114, 20315, 21857, + 22253, 22411, 24911, 25380, 26027, 26376) + }, + { + AOM_CDF14(5370, 6889, 7247, 7393, 9498, 21114, 21402, + 21753, 21981, 24780, 25386, 26517, 27176) + }, + { + AOM_CDF14(4816, 4961, 7204, 7326, 8765, 8930, 20169, + 20682, 20803, 23188, 23763, 24455, 24940) + }, + { + AOM_CDF14(6608, 6740, 8529, 9049, 9257, 9356, 9735, + 18827, 19059, 22336, 23204, 23964, 24793) + }, + { + AOM_CDF14(5998, 7419, 7781, 8933, 9255, 9549, 9753, + 10417, 18898, 22494, 23139, 24764, 25989) + }, + { + AOM_CDF14(10660, 11298, 12550, 12957, 13322, 13624, + 14040, 15004, 15534, 20714, 21789, 23443, + 24861) + }, + { + AOM_CDF14(10522, 11530, 12552, 12963, 13378, 13779, + 14245, 15235, 15902, 20102, 22696, 23774, + 25838) + }, + { + AOM_CDF14(10099, 10691, 12639, 13049, 13386, 13665, + 14125, 15163, 15636, 19676, 20474, 23519, + 25208) + }, + { + AOM_CDF14(3144, 5087, 7382, 7504, 7593, 7690, 7801, + 8064, 8232, 9248, 9875, 10521, 29048) + } + } +}; + +static const u16 default_partition_cdf[13][16] = { + { + AOM_CDF4(19132, 25510, 30392), AOM_CDF4(13928, 19855, 28540), + AOM_CDF4(12522, 23679, 28629), AOM_CDF4(9896, 18783, 25853), + AOM_CDF2(11570), AOM_CDF2(16855), AOM_CDF3(9413, 22581) + }, + { + AOM_CDF10(15597, 20929, 24571, 26706, 27664, 28821, 29601, 30571, 31902) + }, + { + AOM_CDF10(7925, 11043, 16785, 22470, 23971, 25043, 26651, 28701, 29834) + }, + { + AOM_CDF10(5414, 13269, 15111, 20488, 22360, 24500, 25537, 26336, 32117) + }, + { + AOM_CDF10(2662, 6362, 8614, 20860, 23053, 24778, 26436, 27829, 31171) + }, + { + AOM_CDF10(18462, 20920, 23124, 27647, 28227, 29049, 29519, 30178, 31544) + }, + { + AOM_CDF10(7689, 9060, 12056, 24992, 25660, 26182, 26951, 28041, 29052) + }, + { + AOM_CDF10(6015, 9009, 10062, 24544, 25409, 26545, 27071, 27526, 32047) + }, + { + AOM_CDF10(1394, 2208, 2796, 28614, 29061, 29466, 29840, 30185, 31899) + }, + { + AOM_CDF10(20137, 21547, 23078, 29566, 29837, 30261, 30524, 30892, 31724), + AOM_CDF8(27899, 28219, 28529, 32484, 32539, 32619, 32639) + }, + { + AOM_CDF10(6732, 7490, 9497, 27944, 28250, 28515, 28969, 29630, 30104), + AOM_CDF8(6607, 6990, 8268, 32060, 32219, 32338, 32371) + }, + { + AOM_CDF10(5945, 7663, 8348, 28683, 29117, 29749, 30064, 30298, 32238), + AOM_CDF8(5429, 6676, 7122, 32027, 32227, 32531, 32582) + }, + { + AOM_CDF10(870, 1212, 1487, 31198, 31394, 31574, 31743, 31881, 32332), + AOM_CDF8(711, 966, 1172, 32448, 32538, 32617, 32664) + }, +}; + +static const u16 default_intra_ext_tx0_cdf[EXTTX_SIZES][AV1_INTRA_MODES][8] = { + { + { AOM_CDF7(1535, 8035, 9461, 12751, 23467, 27825)}, + { AOM_CDF7(564, 3335, 9709, 10870, 18143, 28094)}, + { AOM_CDF7(672, 3247, 3676, 11982, 19415, 23127)}, + { AOM_CDF7(5279, 13885, 15487, 18044, 23527, 30252)}, + { AOM_CDF7(4423, 6074, 7985, 10416, 25693, 29298)}, + { AOM_CDF7(1486, 4241, 9460, 10662, 16456, 27694)}, + { AOM_CDF7(439, 2838, 3522, 6737, 18058, 23754)}, + { AOM_CDF7(1190, 4233, 4855, 11670, 20281, 24377)}, + { AOM_CDF7(1045, 4312, 8647, 10159, 18644, 29335)}, + { AOM_CDF7(202, 3734, 4747, 7298, 17127, 24016)}, + { AOM_CDF7(447, 4312, 6819, 8884, 16010, 23858)}, + { AOM_CDF7(277, 4369, 5255, 8905, 16465, 22271)}, + { AOM_CDF7(3409, 5436, 10599, 15599, 19687, 24040)}, + }, + { + { AOM_CDF7(1870, 13742, 14530, 16498, 23770, 27698)}, + { AOM_CDF7(326, 8796, 14632, 15079, 19272, 27486)}, + { AOM_CDF7(484, 7576, 7712, 14443, 19159, 22591)}, + { AOM_CDF7(1126, 15340, 15895, 17023, 20896, 30279)}, + { AOM_CDF7(655, 4854, 5249, 5913, 22099, 27138)}, + { AOM_CDF7(1299, 6458, 8885, 9290, 14851, 25497)}, + { AOM_CDF7(311, 5295, 5552, 6885, 16107, 22672)}, + { AOM_CDF7(883, 8059, 8270, 11258, 17289, 21549)}, + { AOM_CDF7(741, 7580, 9318, 10345, 16688, 29046)}, + { AOM_CDF7(110, 7406, 7915, 9195, 16041, 23329)}, + { AOM_CDF7(363, 7974, 9357, 10673, 15629, 24474)}, + { AOM_CDF7(153, 7647, 8112, 9936, 15307, 19996)}, + { AOM_CDF7(3511, 6332, 11165, 15335, 19323, 23594)}, + }, + { + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + }, + { + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + { AOM_CDF7(4681, 9362, 14043, 18725, 23406, 28087)}, + }, +}; + +static const u16 default_intra_ext_tx1_cdf[EXTTX_SIZES][AV1_INTRA_MODES][4] = { + { + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + }, + { + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + }, + { + { AOM_CDF5(1127, 12814, 22772, 27483)}, + { AOM_CDF5(145, 6761, 11980, 26667)}, + { AOM_CDF5(362, 5887, 11678, 16725)}, + { AOM_CDF5(385, 15213, 18587, 30693)}, + { AOM_CDF5(25, 2914, 23134, 27903)}, + { AOM_CDF5(60, 4470, 11749, 23991)}, + { AOM_CDF5(37, 3332, 14511, 21448)}, + { AOM_CDF5(157, 6320, 13036, 17439)}, + { AOM_CDF5(119, 6719, 12906, 29396)}, + { AOM_CDF5(47, 5537, 12576, 21499)}, + { AOM_CDF5(269, 6076, 11258, 23115)}, + { AOM_CDF5(83, 5615, 12001, 17228)}, + { AOM_CDF5(1968, 5556, 12023, 18547)}, + }, + { + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + { AOM_CDF5(6554, 13107, 19661, 26214)}, + }, +}; + +static const u16 default_inter_ext_tx_cdf[2][EXTTX_SIZES][EXT_TX_TYPES] = { + { + { + AOM_CDF16(4458, 5560, 7695, 9709, 13330, 14789, 17537, 20266, + 21504, 22848, 23934, 25474, 27727, 28915, 30631) + }, + { + AOM_CDF16(1645, 2573, 4778, 5711, 7807, 8622, 10522, 15357, 17674, + 20408, 22517, 25010, 27116, 28856, 30749) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, + 18432, 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, + 18432, 20480, 22528, 24576, 26624, 28672, 30720) + }, + }, + { + { + AOM_CDF12(2731, 5461, 8192, 10923, 13653, 16384, 19115, 21845, + 24576, 27307, 30037), + AOM_CDF2(16384) + }, + { + AOM_CDF12(2731, 5461, 8192, 10923, 13653, 16384, 19115, 21845, + 24576, 27307, 30037), + AOM_CDF2(4167) + }, + { + AOM_CDF12(770, 2421, 5225, 12907, 15819, 18927, 21561, 24089, + 26595, 28526, 30529), + AOM_CDF2(1998) + }, + { + AOM_CDF12(2731, 5461, 8192, 10923, 13653, 16384, 19115, 21845, + 24576, 27307, 30037), + AOM_CDF2(748) + }, + } +}; + +static const u16 default_cfl_sign_cdf[CDF_SIZE(CFL_JOINT_SIGNS)] = { + AOM_CDF8(1418, 2123, 13340, 18405, 26972, 28343, 32294) +}; + +static const u16 default_cfl_alpha_cdf[CFL_ALPHA_CONTEXTS][CDF_SIZE(CFL_ALPHABET_SIZE)] = { + { + AOM_CDF16(7637, 20719, 31401, 32481, 32657, 32688, 32692, 32696, 32700, + 32704, 32708, 32712, 32716, 32720, 32724) + }, + { + AOM_CDF16(14365, 23603, 28135, 31168, 32167, 32395, 32487, 32573, + 32620, 32647, 32668, 32672, 32676, 32680, 32684) + }, + { + AOM_CDF16(11532, 22380, 28445, 31360, 32349, 32523, 32584, 32649, + 32673, 32677, 32681, 32685, 32689, 32693, 32697) + }, + { + AOM_CDF16(26990, 31402, 32282, 32571, 32692, 32696, 32700, 32704, + 32708, 32712, 32716, 32720, 32724, 32728, 32732) + }, + { + AOM_CDF16(17248, 26058, 28904, 30608, 31305, 31877, 32126, 32321, + 32394, 32464, 32516, 32560, 32576, 32593, 32622) + }, + { + AOM_CDF16(14738, 21678, 25779, 27901, 29024, 30302, 30980, 31843, + 32144, 32413, 32520, 32594, 32622, 32656, 32660) + } +}; + +static const u16 default_switchable_interp_cdf[SWITCHABLE_FILTER_CONTEXTS] + [CDF_SIZE(AV1_SWITCHABLE_FILTERS)] = { + { AOM_CDF3(31935, 32720) }, { AOM_CDF3(5568, 32719) }, + { AOM_CDF3(422, 2938) }, { AOM_CDF3(28244, 32608) }, + { AOM_CDF3(31206, 31953) }, { AOM_CDF3(4862, 32121) }, + { AOM_CDF3(770, 1152) }, { AOM_CDF3(20889, 25637) }, + { AOM_CDF3(31910, 32724) }, { AOM_CDF3(4120, 32712) }, + { AOM_CDF3(305, 2247) }, { AOM_CDF3(27403, 32636) }, + { AOM_CDF3(31022, 32009) }, { AOM_CDF3(2963, 32093) }, + { AOM_CDF3(601, 943) }, { AOM_CDF3(14969, 21398) } +}; + +static const u16 default_newmv_cdf[NEWMV_MODE_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(24035) }, { AOM_CDF2(16630) }, { AOM_CDF2(15339) }, + { AOM_CDF2(8386) }, { AOM_CDF2(12222) }, { AOM_CDF2(4676) } +}; + +static const u16 default_zeromv_cdf[GLOBALMV_MODE_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(2175) }, { AOM_CDF2(1054) } +}; + +static const u16 default_refmv_cdf[REFMV_MODE_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(23974) }, { AOM_CDF2(24188) }, { AOM_CDF2(17848) }, + { AOM_CDF2(28622) }, { AOM_CDF2(24312) }, { AOM_CDF2(19923) } +}; + +static const u16 default_drl_cdf[DRL_MODE_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(13104) }, { AOM_CDF2(24560) }, { AOM_CDF2(18945) } +}; + +static const u16 default_inter_compound_mode_cdf[AV1_INTER_MODE_CONTEXTS] + [CDF_SIZE(INTER_COMPOUND_MODES)] = { + { AOM_CDF8(7760, 13823, 15808, 17641, 19156, 20666, 26891) }, + { AOM_CDF8(10730, 19452, 21145, 22749, 24039, 25131, 28724) }, + { AOM_CDF8(10664, 20221, 21588, 22906, 24295, 25387, 28436) }, + { AOM_CDF8(13298, 16984, 20471, 24182, 25067, 25736, 26422) }, + { AOM_CDF8(18904, 23325, 25242, 27432, 27898, 28258, 30758) }, + { AOM_CDF8(10725, 17454, 20124, 22820, 24195, 25168, 26046) }, + { AOM_CDF8(17125, 24273, 25814, 27492, 28214, 28704, 30592) }, + { AOM_CDF8(13046, 23214, 24505, 25942, 27435, 28442, 29330) } +}; + +static const u16 default_interintra_cdf[BLOCK_SIZE_GROUPS][CDF_SIZE(2)] = { + { AOM_CDF2(16384) }, { AOM_CDF2(26887) }, { AOM_CDF2(27597) }, + { AOM_CDF2(30237) } +}; + +static const u16 default_interintra_mode_cdf[BLOCK_SIZE_GROUPS][CDF_SIZE(INTERINTRA_MODES)] = { + { AOM_CDF4(8192, 16384, 24576) }, + { AOM_CDF4(1875, 11082, 27332) }, + { AOM_CDF4(2473, 9996, 26388) }, + { AOM_CDF4(4238, 11537, 25926) } +}; + +static const u16 default_wedge_interintra_cdf[BLOCK_SIZES_ALL][CDF_SIZE(2)] = { + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(20036) }, { AOM_CDF2(24957) }, { AOM_CDF2(26704) }, + { AOM_CDF2(27530) }, { AOM_CDF2(29564) }, { AOM_CDF2(29444) }, + { AOM_CDF2(26872) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(16384) } +}; + +static const u16 default_compound_type_cdf[BLOCK_SIZES_ALL][CDF_SIZE(COMPOUND_TYPES - 1)] = { + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(23431) }, + { AOM_CDF2(13171) }, { AOM_CDF2(11470) }, { AOM_CDF2(9770) }, + { AOM_CDF2(9100) }, + { AOM_CDF2(8233) }, { AOM_CDF2(6172) }, { AOM_CDF2(16384) }, + { AOM_CDF2(16384) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(16384) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(11820) }, + { AOM_CDF2(7701) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) } +}; + +static const u16 default_wedge_idx_cdf[BLOCK_SIZES_ALL][CDF_SIZE(16)] = { + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, + 18432, 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, + 18432, 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, + 18432, 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2438, 4440, 6599, 8663, 11005, 12874, 15751, 18094, + 20359, 22362, 24127, 25702, 27752, 29450, 31171) + }, + { + AOM_CDF16(806, 3266, 6005, 6738, 7218, 7367, 7771, 14588, 16323, + 17367, 18452, 19422, 22839, 26127, 29629) + }, + { + AOM_CDF16(2779, 3738, 4683, 7213, 7775, 8017, 8655, 14357, 17939, + 21332, 24520, 27470, 29456, 30529, 31656) + }, + { + AOM_CDF16(1684, 3625, 5675, 7108, 9302, 11274, 14429, 17144, 19163, + 20961, 22884, 24471, 26719, 28714, 30877) + }, + { + AOM_CDF16(1142, 3491, 6277, 7314, 8089, 8355, 9023, 13624, 15369, + 16730, 18114, 19313, 22521, 26012, 29550) + }, + { + AOM_CDF16(2742, 4195, 5727, 8035, 8980, 9336, 10146, 14124, 17270, + 20533, 23434, 25972, 27944, 29570, 31416) + }, + { + AOM_CDF16(1727, 3948, 6101, 7796, 9841, 12344, 15766, 18944, 20638, + 22038, 23963, 25311, 26988, 28766, 31012) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(154, 987, 1925, 2051, 2088, 2111, 2151, 23033, 23703, 24284, + 24985, 25684, 27259, 28883, 30911) + }, + { + AOM_CDF16(1135, 1322, 1493, 2635, 2696, 2737, 2770, 21016, 22935, + 25057, 27251, 29173, 30089, 30960, 31933) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + }, + { + AOM_CDF16(2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432, + 20480, 22528, 24576, 26624, 28672, 30720) + } +}; + +static const u16 default_motion_mode_cdf[BLOCK_SIZES_ALL][CDF_SIZE(MOTION_MODES)] = { + { AOM_CDF3(10923, 21845) }, { AOM_CDF3(10923, 21845) }, + { AOM_CDF3(10923, 21845) }, { AOM_CDF3(7651, 24760) }, + { AOM_CDF3(4738, 24765) }, { AOM_CDF3(5391, 25528) }, + { AOM_CDF3(19419, 26810) }, { AOM_CDF3(5123, 23606) }, + { AOM_CDF3(11606, 24308) }, { AOM_CDF3(26260, 29116) }, + { AOM_CDF3(20360, 28062) }, { AOM_CDF3(21679, 26830) }, + { AOM_CDF3(29516, 30701) }, { AOM_CDF3(28898, 30397) }, + { AOM_CDF3(30878, 31335) }, { AOM_CDF3(32507, 32558) }, + { AOM_CDF3(10923, 21845) }, { AOM_CDF3(10923, 21845) }, + { AOM_CDF3(28799, 31390) }, { AOM_CDF3(26431, 30774) }, + { AOM_CDF3(28973, 31594) }, { AOM_CDF3(29742, 31203) } +}; + +static const u16 default_obmc_cdf[BLOCK_SIZES_ALL][CDF_SIZE(2)] = { + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(10437) }, + { AOM_CDF2(9371) }, { AOM_CDF2(9301) }, { AOM_CDF2(17432) }, + { AOM_CDF2(14423) }, + { AOM_CDF2(15142) }, { AOM_CDF2(25817) }, { AOM_CDF2(22823) }, + { AOM_CDF2(22083) }, + { AOM_CDF2(30128) }, { AOM_CDF2(31014) }, { AOM_CDF2(31560) }, + { AOM_CDF2(32638) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(23664) }, + { AOM_CDF2(20901) }, + { AOM_CDF2(24008) }, { AOM_CDF2(26879) } +}; + +static const u16 default_intra_inter_cdf[INTRA_INTER_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(806) }, + { AOM_CDF2(16662) }, + { AOM_CDF2(20186) }, + { AOM_CDF2(26538) } +}; + +static const u16 default_comp_inter_cdf[COMP_INTER_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(26828) }, + { AOM_CDF2(24035) }, + { AOM_CDF2(12031) }, + { AOM_CDF2(10640) }, + { AOM_CDF2(2901) } +}; + +static const u16 default_comp_ref_type_cdf[COMP_REF_TYPE_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(1198) }, + { AOM_CDF2(2070) }, + { AOM_CDF2(9166) }, + { AOM_CDF2(7499) }, + { AOM_CDF2(22475) } +}; + +static const u16 default_uni_comp_ref_cdf[UNI_COMP_REF_CONTEXTS] + [UNIDIR_COMP_REFS - 1][CDF_SIZE(2)] = { + { { AOM_CDF2(5284)}, { AOM_CDF2(3865)}, { AOM_CDF2(3128)} }, + { { AOM_CDF2(23152)}, { AOM_CDF2(14173)}, { AOM_CDF2(15270)} }, + { { AOM_CDF2(31774)}, { AOM_CDF2(25120)}, { AOM_CDF2(26710)} } +}; + +static const u16 default_single_ref_cdf[REF_CONTEXTS][SINGLE_REFS - 1][CDF_SIZE(2)] = { + { + { AOM_CDF2(4897)}, + { AOM_CDF2(1555)}, + { AOM_CDF2(4236)}, + { AOM_CDF2(8650)}, + { AOM_CDF2(904)}, + { AOM_CDF2(1444)} + }, + { + { AOM_CDF2(16973)}, + { AOM_CDF2(16751)}, + { AOM_CDF2(19647)}, + { AOM_CDF2(24773)}, + { AOM_CDF2(11014)}, + { AOM_CDF2(15087)} + }, + { + { AOM_CDF2(29744)}, + { AOM_CDF2(30279)}, + { AOM_CDF2(31194)}, + { AOM_CDF2(31895)}, + { AOM_CDF2(26875)}, + { AOM_CDF2(30304)} + } +}; + +static const u16 default_comp_ref_cdf[REF_CONTEXTS][FWD_REFS - 1][CDF_SIZE(2)] = { + { { AOM_CDF2(4946)}, { AOM_CDF2(9468)}, { AOM_CDF2(1503)} }, + { { AOM_CDF2(19891)}, { AOM_CDF2(22441)}, { AOM_CDF2(15160)} }, + { { AOM_CDF2(30731)}, { AOM_CDF2(31059)}, { AOM_CDF2(27544)} } +}; + +static const u16 default_comp_bwdref_cdf[REF_CONTEXTS][BWD_REFS - 1][CDF_SIZE(2)] = { + { { AOM_CDF2(2235)}, { AOM_CDF2(1423)} }, + { { AOM_CDF2(17182)}, { AOM_CDF2(15175)} }, + { { AOM_CDF2(30606)}, { AOM_CDF2(30489)} } +}; + +static const u16 default_palette_y_size_cdf[PALETTE_BLOCK_SIZES][CDF_SIZE(PALETTE_SIZES)] = { + { AOM_CDF7(7952, 13000, 18149, 21478, 25527, 29241) }, + { AOM_CDF7(7139, 11421, 16195, 19544, 23666, 28073) }, + { AOM_CDF7(7788, 12741, 17325, 20500, 24315, 28530) }, + { AOM_CDF7(8271, 14064, 18246, 21564, 25071, 28533) }, + { AOM_CDF7(12725, 19180, 21863, 24839, 27535, 30120) }, + { AOM_CDF7(9711, 14888, 16923, 21052, 25661, 27875) }, + { AOM_CDF7(14940, 20797, 21678, 24186, 27033, 28999) } +}; + +static const u16 default_palette_uv_size_cdf[PALETTE_BLOCK_SIZES][CDF_SIZE(PALETTE_SIZES)] = { + { AOM_CDF7(8713, 19979, 27128, 29609, 31331, 32272) }, + { AOM_CDF7(5839, 15573, 23581, 26947, 29848, 31700) }, + { AOM_CDF7(4426, 11260, 17999, 21483, 25863, 29430) }, + { AOM_CDF7(3228, 9464, 14993, 18089, 22523, 27420) }, + { AOM_CDF7(3768, 8886, 13091, 17852, 22495, 27207) }, + { AOM_CDF7(2464, 8451, 12861, 21632, 25525, 28555) }, + { AOM_CDF7(1269, 5435, 10433, 18963, 21700, 25865) } +}; + +static const u16 default_palette_y_mode_cdf[PALETTE_BLOCK_SIZES] + [PALETTE_Y_MODE_CONTEXTS][CDF_SIZE(2)] = { + { { AOM_CDF2(31676)}, { AOM_CDF2(3419)}, { AOM_CDF2(1261)} }, + { { AOM_CDF2(31912)}, { AOM_CDF2(2859)}, { AOM_CDF2(980)} }, + { { AOM_CDF2(31823)}, { AOM_CDF2(3400)}, { AOM_CDF2(781)} }, + { { AOM_CDF2(32030)}, { AOM_CDF2(3561)}, { AOM_CDF2(904)} }, + { { AOM_CDF2(32309)}, { AOM_CDF2(7337)}, { AOM_CDF2(1462)} }, + { { AOM_CDF2(32265)}, { AOM_CDF2(4015)}, { AOM_CDF2(1521)} }, + { { AOM_CDF2(32450)}, { AOM_CDF2(7946)}, { AOM_CDF2(129)} } +}; + +static const u16 default_palette_uv_mode_cdf[PALETTE_UV_MODE_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(32461) }, { AOM_CDF2(21488) } +}; + +static const u16 default_palette_y_color_index_cdf[PALETTE_IDX_CONTEXTS][8] = { + // Palette sizes 2 & 8 + { + AOM_CDF2(28710), + AOM_CDF8(21689, 23883, 25163, 26352, 27506, 28827, 30195) + }, + { + AOM_CDF2(16384), + AOM_CDF8(6892, 15385, 17840, 21606, 24287, 26753, 29204) + }, + { + AOM_CDF2(10553), + AOM_CDF8(5651, 23182, 25042, 26518, 27982, 29392, 30900) + }, + { + AOM_CDF2(27036), + AOM_CDF8(19349, 22578, 24418, 25994, 27524, 29031, 30448) + }, + { + AOM_CDF2(31603), + AOM_CDF8(31028, 31270, 31504, 31705, 31927, 32153, 32392) + }, + // Palette sizes 3 & 7 + { + AOM_CDF3(27877, 30490), + AOM_CDF7(23105, 25199, 26464, 27684, 28931, 30318) + }, + { + AOM_CDF3(11532, 25697), + AOM_CDF7(6950, 15447, 18952, 22681, 25567, 28563) + }, + { + AOM_CDF3(6544, 30234), + AOM_CDF7(7560, 23474, 25490, 27203, 28921, 30708) + }, + { + AOM_CDF3(23018, 28072), + AOM_CDF7(18544, 22373, 24457, 26195, 28119, 30045) + }, + { + AOM_CDF3(31915, 32385), + AOM_CDF7(31198, 31451, 31670, 31882, 32123, 32391) + }, + // Palette sizes 4 & 6 + { + AOM_CDF4(25572, 28046, 30045), + AOM_CDF6(23132, 25407, 26970, 28435, 30073) + }, + { + AOM_CDF4(9478, 21590, 27256), + AOM_CDF6(7443, 17242, 20717, 24762, 27982) + }, + { + AOM_CDF4(7248, 26837, 29824), + AOM_CDF6(6300, 24862, 26944, 28784, 30671) + }, + { + AOM_CDF4(19167, 24486, 28349), + AOM_CDF6(18916, 22895, 25267, 27435, 29652) + }, + { + AOM_CDF4(31400, 31825, 32250), + AOM_CDF6(31270, 31550, 31808, 32059, 32353) + }, + // Palette size 5 + { + AOM_CDF5(24779, 26955, 28576, 30282), + AOM_CDF5(8669, 20364, 24073, 28093) + }, + { + AOM_CDF5(4255, 27565, 29377, 31067), + AOM_CDF5(19864, 23674, 26716, 29530) + }, + { + AOM_CDF5(31646, 31893, 32147, 32426), + 0, 0, 0, 0 + } +}; + +static const u16 default_palette_uv_color_index_cdf[PALETTE_IDX_CONTEXTS][8] = { + // Palette sizes 2 & 8 + { + AOM_CDF2(29089), + AOM_CDF8(21442, 23288, 24758, 26246, 27649, 28980, 30563) + }, + { + AOM_CDF2(16384), + AOM_CDF8(5863, 14933, 17552, 20668, 23683, 26411, 29273) + }, + { + AOM_CDF2(8713), + AOM_CDF8(3415, 25810, 26877, 27990, 29223, 30394, 31618) + }, + { + AOM_CDF2(29257), + AOM_CDF8(17965, 20084, 22232, 23974, 26274, 28402, 30390) + }, + { + AOM_CDF2(31610), + AOM_CDF8(31190, 31329, 31516, 31679, 31825, 32026, 32322) + }, + // Palette sizes 3 & 7 + { + AOM_CDF3(25257, 29145), + AOM_CDF7(21239, 23168, 25044, 26962, 28705, 30506) + }, + { + AOM_CDF3(12287, 27293), + AOM_CDF7(6545, 15012, 18004, 21817, 25503, 28701) + }, + { + AOM_CDF3(7033, 27960), + AOM_CDF7(3448, 26295, 27437, 28704, 30126, 31442) + }, + { + AOM_CDF3(20145, 25405), + AOM_CDF7(15889, 18323, 21704, 24698, 26976, 29690) + }, + { + AOM_CDF3(30608, 31639), + AOM_CDF7(30988, 31204, 31479, 31734, 31983, 32325) + }, + // Palette sizes 4 & 6 + { + AOM_CDF4(24210, 27175, 29903), + AOM_CDF6(22217, 24567, 26637, 28683, 30548) + }, + { + AOM_CDF4(9888, 22386, 27214), + AOM_CDF6(7307, 16406, 19636, 24632, 28424) + }, + { + AOM_CDF4(5901, 26053, 29293), + AOM_CDF6(4441, 25064, 26879, 28942, 30919) + }, + { + AOM_CDF4(18318, 22152, 28333), + AOM_CDF6(17210, 20528, 23319, 26750, 29582) + }, + { + AOM_CDF4(30459, 31136, 31926), + AOM_CDF6(30674, 30953, 31396, 31735, 32207) + }, + // Palette size 5 + { + AOM_CDF5(22980, 25479, 27781, 29986), + AOM_CDF5(8413, 21408, 24859, 28874) + }, + { + AOM_CDF5(2257, 29449, 30594, 31598), + AOM_CDF5(19189, 21202, 25915, 28620) + }, + { + AOM_CDF5(31844, 32044, 32281, 32518), + 0, 0, 0, 0 + } +}; + +static const u16 default_txfm_partition_cdf[TXFM_PARTITION_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(28581) }, { AOM_CDF2(23846) }, { AOM_CDF2(20847) }, + { AOM_CDF2(24315) }, { AOM_CDF2(18196) }, { AOM_CDF2(12133) }, + { AOM_CDF2(18791) }, { AOM_CDF2(10887) }, { AOM_CDF2(11005) }, + { AOM_CDF2(27179) }, { AOM_CDF2(20004) }, { AOM_CDF2(11281) }, + { AOM_CDF2(26549) }, { AOM_CDF2(19308) }, { AOM_CDF2(14224) }, + { AOM_CDF2(28015) }, { AOM_CDF2(21546) }, { AOM_CDF2(14400) }, + { AOM_CDF2(28165) }, { AOM_CDF2(22401) }, { AOM_CDF2(16088) } +}; + +static const u16 default_skip_cdfs[SKIP_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(31671) }, { AOM_CDF2(16515) }, { AOM_CDF2(4576) } +}; + +static const u16 default_skip_mode_cdfs[SKIP_MODE_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(32621) }, { AOM_CDF2(20708) }, { AOM_CDF2(8127) } +}; + +static const u16 default_compound_idx_cdfs[COMP_INDEX_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(18244) }, { AOM_CDF2(12865) }, { AOM_CDF2(7053) }, + { AOM_CDF2(13259) }, { AOM_CDF2(9334) }, { AOM_CDF2(4644) } +}; + +static const u16 default_comp_group_idx_cdfs[COMP_GROUP_IDX_CONTEXTS][CDF_SIZE(2)] = { + { AOM_CDF2(26607) }, { AOM_CDF2(22891) }, { AOM_CDF2(18840) }, + { AOM_CDF2(24594) }, { AOM_CDF2(19934) }, { AOM_CDF2(22674) } +}; + +static const u16 default_intrabc_cdf[CDF_SIZE(2)] = { AOM_CDF2(30531) }; + +static const u16 default_filter_intra_mode_cdf[CDF_SIZE(FILTER_INTRA_MODES)] = { + AOM_CDF5(8949, 12776, 17211, 29558) +}; + +static const u16 default_filter_intra_cdfs[BLOCK_SIZES_ALL][CDF_SIZE(2)] = { + { AOM_CDF2(4621) }, { AOM_CDF2(6743) }, { AOM_CDF2(5893) }, { AOM_CDF2(7866) }, + { AOM_CDF2(12551) }, { AOM_CDF2(9394) }, { AOM_CDF2(12408) }, { AOM_CDF2(14301) }, + { AOM_CDF2(12756) }, { AOM_CDF2(22343) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, { AOM_CDF2(16384) }, + { AOM_CDF2(12770) }, { AOM_CDF2(10368) }, { AOM_CDF2(20229) }, { AOM_CDF2(18101) }, + { AOM_CDF2(16384) }, { AOM_CDF2(16384) } +}; + +static const u16 default_delta_q_cdf[CDF_SIZE(DELTA_Q_PROBS + 1)] = { + AOM_CDF4(28160, 32120, 32677) +}; + +static const u16 default_delta_lf_multi_cdf[FRAME_LF_COUNT][CDF_SIZE(DELTA_LF_PROBS + 1)] = { + { AOM_CDF4(28160, 32120, 32677) }, + { AOM_CDF4(28160, 32120, 32677) }, + { AOM_CDF4(28160, 32120, 32677) }, + { AOM_CDF4(28160, 32120, 32677) } +}; + +static const u16 default_delta_lf_cdf[CDF_SIZE(DELTA_LF_PROBS + 1)] = { + AOM_CDF4(28160, 32120, 32677) +}; + +static const u16 default_segment_pred_cdf[SEG_TEMPORAL_PRED_CTXS][CDF_SIZE(2)] = { + { AOM_CDF2(128 * 128) }, + { AOM_CDF2(128 * 128) }, + { AOM_CDF2(128 * 128) } +}; + +static const u16 default_spatial_pred_seg_tree_cdf[SPATIAL_PREDICTION_PROBS] + [CDF_SIZE(MAX_SEGMENTS)] = { + { + AOM_CDF8(5622, 7893, 16093, 18233, 27809, 28373, 32533), + }, + { + AOM_CDF8(14274, 18230, 22557, 24935, 29980, 30851, 32344), + }, + { + AOM_CDF8(27527, 28487, 28723, 28890, 32397, 32647, 32679), + }, +}; + +static const u16 default_tx_size_cdf[MAX_TX_CATS] + [AV1_TX_SIZE_CONTEXTS][CDF_SIZE(MAX_TX_DEPTH + 1)] = { + { + { AOM_CDF2(19968)}, + { AOM_CDF2(19968)}, + { AOM_CDF2(24320)} + }, + { + { AOM_CDF3(12272, 30172)}, + { AOM_CDF3(12272, 30172)}, + { AOM_CDF3(18677, 30848)} + }, + { + { AOM_CDF3(12986, 15180)}, + { AOM_CDF3(12986, 15180)}, + { AOM_CDF3(24302, 25602)} + }, + { + { AOM_CDF3(5782, 11475)}, + { AOM_CDF3(5782, 11475)}, + { AOM_CDF3(16803, 22759)} + }, +}; + +static const u16 av1_default_dc_sign_cdfs[TOKEN_CDF_Q_CTXS] + [PLANE_TYPES][DC_SIGN_CONTEXTS][CDF_SIZE(2)] = { + { + { + { AOM_CDF2(128 * 125)}, + { AOM_CDF2(128 * 102)}, + { AOM_CDF2(128 * 147)}, + }, + { + { AOM_CDF2(128 * 119)}, + { AOM_CDF2(128 * 101)}, + { AOM_CDF2(128 * 135)}, + } + }, + { + { + { AOM_CDF2(128 * 125)}, + { AOM_CDF2(128 * 102)}, + { AOM_CDF2(128 * 147)}, + }, + { + { AOM_CDF2(128 * 119)}, + { AOM_CDF2(128 * 101)}, + { AOM_CDF2(128 * 135)}, + } + }, + { + { + { AOM_CDF2(128 * 125)}, + { AOM_CDF2(128 * 102)}, + { AOM_CDF2(128 * 147)}, + }, + { + { AOM_CDF2(128 * 119)}, + { AOM_CDF2(128 * 101)}, + { AOM_CDF2(128 * 135)}, + } + }, + { + { + { AOM_CDF2(128 * 125)}, + { AOM_CDF2(128 * 102)}, + { AOM_CDF2(128 * 147)}, + }, + { + { AOM_CDF2(128 * 119)}, + { AOM_CDF2(128 * 101)}, + { AOM_CDF2(128 * 135)}, + } + }, +}; + +static const u16 av1_default_txb_skip_cdfs[TOKEN_CDF_Q_CTXS] + [TX_SIZES][TXB_SKIP_CONTEXTS][CDF_SIZE(2)] = { + { + { + { AOM_CDF2(31849)}, + { AOM_CDF2(5892)}, + { AOM_CDF2(12112)}, + { AOM_CDF2(21935)}, + { AOM_CDF2(20289)}, + { AOM_CDF2(27473)}, + { AOM_CDF2(32487)}, + { AOM_CDF2(7654)}, + { AOM_CDF2(19473)}, + { AOM_CDF2(29984)}, + { AOM_CDF2(9961)}, + { AOM_CDF2(30242)}, + { AOM_CDF2(32117)} + }, + { + { AOM_CDF2(31548)}, + { AOM_CDF2(1549)}, + { AOM_CDF2(10130)}, + { AOM_CDF2(16656)}, + { AOM_CDF2(18591)}, + { AOM_CDF2(26308)}, + { AOM_CDF2(32537)}, + { AOM_CDF2(5403)}, + { AOM_CDF2(18096)}, + { AOM_CDF2(30003)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(29957)}, + { AOM_CDF2(5391)}, + { AOM_CDF2(18039)}, + { AOM_CDF2(23566)}, + { AOM_CDF2(22431)}, + { AOM_CDF2(25822)}, + { AOM_CDF2(32197)}, + { AOM_CDF2(3778)}, + { AOM_CDF2(15336)}, + { AOM_CDF2(28981)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(17920)}, + { AOM_CDF2(1818)}, + { AOM_CDF2(7282)}, + { AOM_CDF2(25273)}, + { AOM_CDF2(10923)}, + { AOM_CDF2(31554)}, + { AOM_CDF2(32624)}, + { AOM_CDF2(1366)}, + { AOM_CDF2(15628)}, + { AOM_CDF2(30462)}, + { AOM_CDF2(146)}, + { AOM_CDF2(5132)}, + { AOM_CDF2(31657)} + }, + { + { AOM_CDF2(6308)}, + { AOM_CDF2(117)}, + { AOM_CDF2(1638)}, + { AOM_CDF2(2161)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(10923)}, + { AOM_CDF2(30247)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + } + }, + { + { + { AOM_CDF2(30371)}, + { AOM_CDF2(7570)}, + { AOM_CDF2(13155)}, + { AOM_CDF2(20751)}, + { AOM_CDF2(20969)}, + { AOM_CDF2(27067)}, + { AOM_CDF2(32013)}, + { AOM_CDF2(5495)}, + { AOM_CDF2(17942)}, + { AOM_CDF2(28280)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(31782)}, + { AOM_CDF2(1836)}, + { AOM_CDF2(10689)}, + { AOM_CDF2(17604)}, + { AOM_CDF2(21622)}, + { AOM_CDF2(27518)}, + { AOM_CDF2(32399)}, + { AOM_CDF2(4419)}, + { AOM_CDF2(16294)}, + { AOM_CDF2(28345)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(31901)}, + { AOM_CDF2(10311)}, + { AOM_CDF2(18047)}, + { AOM_CDF2(24806)}, + { AOM_CDF2(23288)}, + { AOM_CDF2(27914)}, + { AOM_CDF2(32296)}, + { AOM_CDF2(4215)}, + { AOM_CDF2(15756)}, + { AOM_CDF2(28341)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(26726)}, + { AOM_CDF2(1045)}, + { AOM_CDF2(11703)}, + { AOM_CDF2(20590)}, + { AOM_CDF2(18554)}, + { AOM_CDF2(25970)}, + { AOM_CDF2(31938)}, + { AOM_CDF2(5583)}, + { AOM_CDF2(21313)}, + { AOM_CDF2(29390)}, + { AOM_CDF2(641)}, + { AOM_CDF2(22265)}, + { AOM_CDF2(31452)} + }, + { + { AOM_CDF2(26584)}, + { AOM_CDF2(188)}, + { AOM_CDF2(8847)}, + { AOM_CDF2(24519)}, + { AOM_CDF2(22938)}, + { AOM_CDF2(30583)}, + { AOM_CDF2(32608)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + } + }, + { + { + { AOM_CDF2(29614)}, + { AOM_CDF2(9068)}, + { AOM_CDF2(12924)}, + { AOM_CDF2(19538)}, + { AOM_CDF2(17737)}, + { AOM_CDF2(24619)}, + { AOM_CDF2(30642)}, + { AOM_CDF2(4119)}, + { AOM_CDF2(16026)}, + { AOM_CDF2(25657)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(31957)}, + { AOM_CDF2(3230)}, + { AOM_CDF2(11153)}, + { AOM_CDF2(18123)}, + { AOM_CDF2(20143)}, + { AOM_CDF2(26536)}, + { AOM_CDF2(31986)}, + { AOM_CDF2(3050)}, + { AOM_CDF2(14603)}, + { AOM_CDF2(25155)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(32363)}, + { AOM_CDF2(10692)}, + { AOM_CDF2(19090)}, + { AOM_CDF2(24357)}, + { AOM_CDF2(24442)}, + { AOM_CDF2(28312)}, + { AOM_CDF2(32169)}, + { AOM_CDF2(3648)}, + { AOM_CDF2(15690)}, + { AOM_CDF2(26815)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(30669)}, + { AOM_CDF2(3832)}, + { AOM_CDF2(11663)}, + { AOM_CDF2(18889)}, + { AOM_CDF2(19782)}, + { AOM_CDF2(23313)}, + { AOM_CDF2(31330)}, + { AOM_CDF2(5124)}, + { AOM_CDF2(18719)}, + { AOM_CDF2(28468)}, + { AOM_CDF2(3082)}, + { AOM_CDF2(20982)}, + { AOM_CDF2(29443)} + }, + { + { AOM_CDF2(28573)}, + { AOM_CDF2(3183)}, + { AOM_CDF2(17802)}, + { AOM_CDF2(25977)}, + { AOM_CDF2(26677)}, + { AOM_CDF2(27832)}, + { AOM_CDF2(32387)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + } + }, + { + { + { AOM_CDF2(26887)}, + { AOM_CDF2(6729)}, + { AOM_CDF2(10361)}, + { AOM_CDF2(17442)}, + { AOM_CDF2(15045)}, + { AOM_CDF2(22478)}, + { AOM_CDF2(29072)}, + { AOM_CDF2(2713)}, + { AOM_CDF2(11861)}, + { AOM_CDF2(20773)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(31903)}, + { AOM_CDF2(2044)}, + { AOM_CDF2(7528)}, + { AOM_CDF2(14618)}, + { AOM_CDF2(16182)}, + { AOM_CDF2(24168)}, + { AOM_CDF2(31037)}, + { AOM_CDF2(2786)}, + { AOM_CDF2(11194)}, + { AOM_CDF2(20155)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(32510)}, + { AOM_CDF2(8430)}, + { AOM_CDF2(17318)}, + { AOM_CDF2(24154)}, + { AOM_CDF2(23674)}, + { AOM_CDF2(28789)}, + { AOM_CDF2(32139)}, + { AOM_CDF2(3440)}, + { AOM_CDF2(13117)}, + { AOM_CDF2(22702)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + }, + { + { AOM_CDF2(31671)}, + { AOM_CDF2(2056)}, + { AOM_CDF2(11746)}, + { AOM_CDF2(16852)}, + { AOM_CDF2(18635)}, + { AOM_CDF2(24715)}, + { AOM_CDF2(31484)}, + { AOM_CDF2(4656)}, + { AOM_CDF2(16074)}, + { AOM_CDF2(24704)}, + { AOM_CDF2(1806)}, + { AOM_CDF2(14645)}, + { AOM_CDF2(25336)} + }, + { + { AOM_CDF2(31539)}, + { AOM_CDF2(8433)}, + { AOM_CDF2(20576)}, + { AOM_CDF2(27904)}, + { AOM_CDF2(27852)}, + { AOM_CDF2(30026)}, + { AOM_CDF2(32441)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)} + } + } +}; + +static const u16 av1_default_eob_extra_cdfs[TOKEN_CDF_Q_CTXS][TX_SIZES][PLANE_TYPES] + [EOB_COEF_CONTEXTS][CDF_SIZE(2)] = { + { + { + { + { AOM_CDF2(16961)}, + { AOM_CDF2(17223)}, + { AOM_CDF2(7621)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(19069)}, + { AOM_CDF2(22525)}, + { AOM_CDF2(13377)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(20401)}, + { AOM_CDF2(17025)}, + { AOM_CDF2(12845)}, + { AOM_CDF2(12873)}, + { AOM_CDF2(14094)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(20681)}, + { AOM_CDF2(20701)}, + { AOM_CDF2(15250)}, + { AOM_CDF2(15017)}, + { AOM_CDF2(14928)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(23905)}, + { AOM_CDF2(17194)}, + { AOM_CDF2(16170)}, + { AOM_CDF2(17695)}, + { AOM_CDF2(13826)}, + { AOM_CDF2(15810)}, + { AOM_CDF2(12036)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(23959)}, + { AOM_CDF2(20799)}, + { AOM_CDF2(19021)}, + { AOM_CDF2(16203)}, + { AOM_CDF2(17886)}, + { AOM_CDF2(14144)}, + { AOM_CDF2(12010)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(27399)}, + { AOM_CDF2(16327)}, + { AOM_CDF2(18071)}, + { AOM_CDF2(19584)}, + { AOM_CDF2(20721)}, + { AOM_CDF2(18432)}, + { AOM_CDF2(19560)}, + { AOM_CDF2(10150)}, + { AOM_CDF2(8805)}, + }, + { + { AOM_CDF2(24932)}, + { AOM_CDF2(20833)}, + { AOM_CDF2(12027)}, + { AOM_CDF2(16670)}, + { AOM_CDF2(19914)}, + { AOM_CDF2(15106)}, + { AOM_CDF2(17662)}, + { AOM_CDF2(13783)}, + { AOM_CDF2(28756)}, + } + }, + { + { + { AOM_CDF2(23406)}, + { AOM_CDF2(21845)}, + { AOM_CDF2(18432)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(17096)}, + { AOM_CDF2(12561)}, + { AOM_CDF2(17320)}, + { AOM_CDF2(22395)}, + { AOM_CDF2(21370)}, + }, + { + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + } + }, + { + { + { + { AOM_CDF2(17471)}, + { AOM_CDF2(20223)}, + { AOM_CDF2(11357)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(20335)}, + { AOM_CDF2(21667)}, + { AOM_CDF2(14818)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(20430)}, + { AOM_CDF2(20662)}, + { AOM_CDF2(15367)}, + { AOM_CDF2(16970)}, + { AOM_CDF2(14657)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(22117)}, + { AOM_CDF2(22028)}, + { AOM_CDF2(18650)}, + { AOM_CDF2(16042)}, + { AOM_CDF2(15885)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(22409)}, + { AOM_CDF2(21012)}, + { AOM_CDF2(15650)}, + { AOM_CDF2(17395)}, + { AOM_CDF2(15469)}, + { AOM_CDF2(20205)}, + { AOM_CDF2(19511)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(24220)}, + { AOM_CDF2(22480)}, + { AOM_CDF2(17737)}, + { AOM_CDF2(18916)}, + { AOM_CDF2(19268)}, + { AOM_CDF2(18412)}, + { AOM_CDF2(18844)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(25991)}, + { AOM_CDF2(20314)}, + { AOM_CDF2(17731)}, + { AOM_CDF2(19678)}, + { AOM_CDF2(18649)}, + { AOM_CDF2(17307)}, + { AOM_CDF2(21798)}, + { AOM_CDF2(17549)}, + { AOM_CDF2(15630)}, + }, + { + { AOM_CDF2(26585)}, + { AOM_CDF2(21469)}, + { AOM_CDF2(20432)}, + { AOM_CDF2(17735)}, + { AOM_CDF2(19280)}, + { AOM_CDF2(15235)}, + { AOM_CDF2(20297)}, + { AOM_CDF2(22471)}, + { AOM_CDF2(28997)}, + } + }, + { + { + { AOM_CDF2(26605)}, + { AOM_CDF2(11304)}, + { AOM_CDF2(16726)}, + { AOM_CDF2(16560)}, + { AOM_CDF2(20866)}, + { AOM_CDF2(23524)}, + { AOM_CDF2(19878)}, + { AOM_CDF2(13469)}, + { AOM_CDF2(23084)}, + }, + { + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + } + }, + { + { + { + { AOM_CDF2(18983)}, + { AOM_CDF2(20512)}, + { AOM_CDF2(14885)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(20090)}, + { AOM_CDF2(19444)}, + { AOM_CDF2(17286)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(19139)}, + { AOM_CDF2(21487)}, + { AOM_CDF2(18959)}, + { AOM_CDF2(20910)}, + { AOM_CDF2(19089)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(20536)}, + { AOM_CDF2(20664)}, + { AOM_CDF2(20625)}, + { AOM_CDF2(19123)}, + { AOM_CDF2(14862)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(19833)}, + { AOM_CDF2(21502)}, + { AOM_CDF2(17485)}, + { AOM_CDF2(20267)}, + { AOM_CDF2(18353)}, + { AOM_CDF2(23329)}, + { AOM_CDF2(21478)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(22041)}, + { AOM_CDF2(23434)}, + { AOM_CDF2(20001)}, + { AOM_CDF2(20554)}, + { AOM_CDF2(20951)}, + { AOM_CDF2(20145)}, + { AOM_CDF2(15562)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(23312)}, + { AOM_CDF2(21607)}, + { AOM_CDF2(16526)}, + { AOM_CDF2(18957)}, + { AOM_CDF2(18034)}, + { AOM_CDF2(18934)}, + { AOM_CDF2(24247)}, + { AOM_CDF2(16921)}, + { AOM_CDF2(17080)}, + }, + { + { AOM_CDF2(26579)}, + { AOM_CDF2(24910)}, + { AOM_CDF2(18637)}, + { AOM_CDF2(19800)}, + { AOM_CDF2(20388)}, + { AOM_CDF2(9887)}, + { AOM_CDF2(15642)}, + { AOM_CDF2(30198)}, + { AOM_CDF2(24721)}, + } + }, + { + { + { AOM_CDF2(26998)}, + { AOM_CDF2(16737)}, + { AOM_CDF2(17838)}, + { AOM_CDF2(18922)}, + { AOM_CDF2(19515)}, + { AOM_CDF2(18636)}, + { AOM_CDF2(17333)}, + { AOM_CDF2(15776)}, + { AOM_CDF2(22658)}, + }, + { + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + } + }, + { + { + { + { AOM_CDF2(20177)}, + { AOM_CDF2(20789)}, + { AOM_CDF2(20262)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(21416)}, + { AOM_CDF2(20855)}, + { AOM_CDF2(23410)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(20238)}, + { AOM_CDF2(21057)}, + { AOM_CDF2(19159)}, + { AOM_CDF2(22337)}, + { AOM_CDF2(20159)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(20125)}, + { AOM_CDF2(20559)}, + { AOM_CDF2(21707)}, + { AOM_CDF2(22296)}, + { AOM_CDF2(17333)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(19941)}, + { AOM_CDF2(20527)}, + { AOM_CDF2(21470)}, + { AOM_CDF2(22487)}, + { AOM_CDF2(19558)}, + { AOM_CDF2(22354)}, + { AOM_CDF2(20331)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + }, + { + { AOM_CDF2(22752)}, + { AOM_CDF2(25006)}, + { AOM_CDF2(22075)}, + { AOM_CDF2(21576)}, + { AOM_CDF2(17740)}, + { AOM_CDF2(21690)}, + { AOM_CDF2(19211)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + }, + { + { + { AOM_CDF2(21442)}, + { AOM_CDF2(22358)}, + { AOM_CDF2(18503)}, + { AOM_CDF2(20291)}, + { AOM_CDF2(19945)}, + { AOM_CDF2(21294)}, + { AOM_CDF2(21178)}, + { AOM_CDF2(19400)}, + { AOM_CDF2(10556)}, + }, + { + { AOM_CDF2(24648)}, + { AOM_CDF2(24949)}, + { AOM_CDF2(20708)}, + { AOM_CDF2(23905)}, + { AOM_CDF2(20501)}, + { AOM_CDF2(9558)}, + { AOM_CDF2(9423)}, + { AOM_CDF2(30365)}, + { AOM_CDF2(19253)}, + } + }, + { + { + { AOM_CDF2(26064)}, + { AOM_CDF2(22098)}, + { AOM_CDF2(19613)}, + { AOM_CDF2(20525)}, + { AOM_CDF2(17595)}, + { AOM_CDF2(16618)}, + { AOM_CDF2(20497)}, + { AOM_CDF2(18989)}, + { AOM_CDF2(15513)}, + }, + { + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + { AOM_CDF2(16384)}, + } + } + } +}; + +static const u16 av1_default_eob_multi16_cdfs[TOKEN_CDF_Q_CTXS][PLANE_TYPES][2][4] = { + { + { + { AOM_CDF5(840, 1039, 1980, 4895)}, + { AOM_CDF5(370, 671, 1883, 4471)} + }, + { + { AOM_CDF5(3247, 4950, 9688, 14563)}, + { AOM_CDF5(1904, 3354, 7763, 14647)} + } + }, + { + { + { AOM_CDF5(2125, 2551, 5165, 8946)}, + { AOM_CDF5(513, 765, 1859, 6339)} + }, + { + { AOM_CDF5(7637, 9498, 14259, 19108)}, + { AOM_CDF5(2497, 4096, 8866, 16993)} + } + }, + { + { + { AOM_CDF5(4016, 4897, 8881, 14968)}, + { AOM_CDF5(716, 1105, 2646, 10056)} + }, + { + { AOM_CDF5(11139, 13270, 18241, 23566)}, + { AOM_CDF5(3192, 5032, 10297, 19755)} + } + }, + { + { + { AOM_CDF5(6708, 8958, 14746, 22133)}, + { AOM_CDF5(1222, 2074, 4783, 15410)} + }, + { + { AOM_CDF5(19575, 21766, 26044, 29709)}, + { AOM_CDF5(7297, 10767, 19273, 28194)} + } + } +}; + +static const u16 av1_default_eob_multi32_cdfs[TOKEN_CDF_Q_CTXS][PLANE_TYPES][2][8] = { + { + { + { AOM_CDF6(400, 520, 977, 2102, 6542)}, + { AOM_CDF6(210, 405, 1315, 3326, 7537)} + }, + { + { AOM_CDF6(2636, 4273, 7588, 11794, 20401)}, + { AOM_CDF6(1786, 3179, 6902, 11357, 19054)} + } + }, + { + { + { AOM_CDF6(989, 1249, 2019, 4151, 10785)}, + { AOM_CDF6(313, 441, 1099, 2917, 8562)} + }, + { + { AOM_CDF6(8394, 10352, 13932, 18855, 26014)}, + { AOM_CDF6(2578, 4124, 8181, 13670, 24234)} + } + }, + { + { + { AOM_CDF6(2515, 3003, 4452, 8162, 16041)}, + { AOM_CDF6(574, 821, 1836, 5089, 13128)} + }, + { + { AOM_CDF6(13468, 16303, 20361, 25105, 29281)}, + { AOM_CDF6(3542, 5502, 10415, 16760, 25644)} + } + }, + { + { + { AOM_CDF6(4617, 5709, 8446, 13584, 23135)}, + { AOM_CDF6(1156, 1702, 3675, 9274, 20539)} + }, + { + { AOM_CDF6(22086, 24282, 27010, 29770, 31743)}, + { AOM_CDF6(7699, 10897, 20891, 26926, 31628)} + } + } +}; + +static const u16 av1_default_eob_multi64_cdfs[TOKEN_CDF_Q_CTXS][PLANE_TYPES][2][8] = { + { + { + { AOM_CDF7(329, 498, 1101, 1784, 3265, 7758)}, + { AOM_CDF7(335, 730, 1459, 5494, 8755, 12997)} + }, + { + { AOM_CDF7(3505, 5304, 10086, 13814, 17684, 23370)}, + { AOM_CDF7(1563, 2700, 4876, 10911, 14706, 22480)} + } + }, + { + { + { AOM_CDF7(1260, 1446, 2253, 3712, 6652, 13369)}, + { AOM_CDF7(401, 605, 1029, 2563, 5845, 12626)} + }, + { + { AOM_CDF7(8609, 10612, 14624, 18714, 22614, 29024)}, + { AOM_CDF7(1923, 3127, 5867, 9703, 14277, 27100)} + } + }, + { + { + { AOM_CDF7(2374, 2772, 4583, 7276, 12288, 19706)}, + { AOM_CDF7(497, 810, 1315, 3000, 7004, 15641)} + }, + { + { AOM_CDF7(15050, 17126, 21410, 24886, 28156, 30726)}, + { AOM_CDF7(4034, 6290, 10235, 14982, 21214, 28491)} + } + }, + { + { + { AOM_CDF7(6307, 7541, 12060, 16358, 22553, 27865)}, + { AOM_CDF7(1289, 2320, 3971, 7926, 14153, 24291)} + }, + { + { AOM_CDF7(24212, 25708, 28268, 30035, 31307, 32049)}, + { AOM_CDF7(8726, 12378, 19409, 26450, 30038, 32462)} + } + } +}; + +static const u16 av1_default_eob_multi128_cdfs[TOKEN_CDF_Q_CTXS][PLANE_TYPES][2][8] = { + { + { + { AOM_CDF8(219, 482, 1140, 2091, 3680, 6028, 12586)}, + { AOM_CDF8(371, 699, 1254, 4830, 9479, 12562, 17497)} + }, + { + { AOM_CDF8(5245, 7456, 12880, 15852, 20033, 23932, 27608)}, + { AOM_CDF8(2054, 3472, 5869, 14232, 18242, 20590, 26752)} + } + }, + { + { + { AOM_CDF8(685, 933, 1488, 2714, 4766, 8562, 19254)}, + { AOM_CDF8(217, 352, 618, 2303, 5261, 9969, 17472)} + }, + { + { AOM_CDF8(8045, 11200, 15497, 19595, 23948, 27408, 30938)}, + { AOM_CDF8(2310, 4160, 7471, 14997, 17931, 20768, 30240)} + } + }, + { + { + { AOM_CDF8(1366, 1738, 2527, 5016, 9355, 15797, 24643)}, + { AOM_CDF8(354, 558, 944, 2760, 7287, 14037, 21779)} + }, + { + { AOM_CDF8(13627, 16246, 20173, 24429, 27948, 30415, 31863)}, + { AOM_CDF8(6275, 9889, 14769, 23164, 27988, 30493, 32272)} + } + }, + { + { + { AOM_CDF8(3472, 4885, 7489, 12481, 18517, 24536, 29635)}, + { AOM_CDF8(886, 1731, 3271, 8469, 15569, 22126, 28383)} + }, + { + { AOM_CDF8(24313, 26062, 28385, 30107, 31217, 31898, 32345)}, + { AOM_CDF8(9165, 13282, 21150, 30286, 31894, 32571, 32712)} + } + } +}; + +static const u16 av1_default_eob_multi256_cdfs[TOKEN_CDF_Q_CTXS][PLANE_TYPES][2][8] = { + { + { + { AOM_CDF9(310, 584, 1887, 3589, 6168, 8611, 11352, 15652)}, + { AOM_CDF9(998, 1850, 2998, 5604, 17341, 19888, 22899, 25583)} + }, + { + { AOM_CDF9(2520, 3240, 5952, 8870, 12577, 17558, 19954, 24168)}, + { AOM_CDF9(2203, 4130, 7435, 10739, 20652, 23681, 25609, 27261)} + } + }, + { + { + { AOM_CDF9(1448, 2109, 4151, 6263, 9329, 13260, 17944, 23300)}, + { AOM_CDF9(399, 1019, 1749, 3038, 10444, 15546, 22739, 27294)} + }, + { + { AOM_CDF9(6402, 8148, 12623, 15072, 18728, 22847, 26447, 29377)}, + { AOM_CDF9(1674, 3252, 5734, 10159, 22397, 23802, 24821, 30940)} + } + }, + { + { + { AOM_CDF9(3089, 3920, 6038, 9460, 14266, 19881, 25766, 29176)}, + { AOM_CDF9(1084, 2358, 3488, 5122, 11483, 18103, 26023, 29799)} + }, + { + { AOM_CDF9(11514, 13794, 17480, 20754, 24361, 27378, 29492, 31277)}, + { AOM_CDF9(6571, 9610, 15516, 21826, 29092, 30829, 31842, 32708)} + } + }, + { + { + { AOM_CDF9(5348, 7113, 11820, 15924, 22106, 26777, 30334, 31757)}, + { AOM_CDF9(2453, 4474, 6307, 8777, 16474, 22975, 29000, 31547)} + }, + { + { AOM_CDF9(23110, 24597, 27140, 28894, 30167, 30927, 31392, 32094)}, + { AOM_CDF9(9998, 17661, 25178, 28097, 31308, 32038, 32403, 32695)} + } + } +}; + +static const u16 av1_default_eob_multi512_cdfs[TOKEN_CDF_Q_CTXS][PLANE_TYPES][2][16] = { + { + { + { AOM_CDF10(641, 983, 3707, 5430, 10234, 14958, 18788, 23412, 26061)}, + { AOM_CDF10(3277, 6554, 9830, 13107, 16384, 19661, 22938, 26214, 29491)} + }, + { + { AOM_CDF10(5095, 6446, 9996, 13354, 16017, 17986, 20919, 26129, 29140)}, + { AOM_CDF10(3277, 6554, 9830, 13107, 16384, 19661, 22938, 26214, 29491)} + } + }, + { + { + { AOM_CDF10(1230, 2278, 5035, 7776, 11871, 15346, 19590, 24584, 28749)}, + { AOM_CDF10(3277, 6554, 9830, 13107, 16384, 19661, 22938, 26214, 29491)} + }, + { + { AOM_CDF10(7265, 9979, 15819, 19250, 21780, 23846, 26478, 28396, 31811)}, + { AOM_CDF10(3277, 6554, 9830, 13107, 16384, 19661, 22938, 26214, 29491)} + } + }, + { + { + { AOM_CDF10(2624, 3936, 6480, 9686, 13979, 17726, 23267, 28410, 31078)}, + { AOM_CDF10(3277, 6554, 9830, 13107, 16384, 19661, 22938, 26214, 29491)} + }, + { + { AOM_CDF10(12015, 14769, 19588, 22052, 24222, 25812, 27300, 29219, 32114)}, + { AOM_CDF10(3277, 6554, 9830, 13107, 16384, 19661, 22938, 26214, 29491)} + } + }, + { + { + { AOM_CDF10(5927, 7809, 10923, 14597, 19439, 24135, 28456, 31142, 32060)}, + { AOM_CDF10(3277, 6554, 9830, 13107, 16384, 19661, 22938, 26214, 29491)} + }, + { + { AOM_CDF10(21093, 23043, 25742, 27658, 29097, 29716, 30073, 30820, 31956)}, + { AOM_CDF10(3277, 6554, 9830, 13107, 16384, 19661, 22938, 26214, 29491)} + } + } +}; + +static const u16 av1_default_eob_multi1024_cdfs[TOKEN_CDF_Q_CTXS][PLANE_TYPES][2][16] = { + { + { + { AOM_CDF11(393, 421, 751, 1623, 3160, + 6352, 13345, 18047, 22571, 25830)}, + { AOM_CDF11(2979, 5958, 8937, 11916, 14895, + 17873, 20852, 23831, 26810, 29789)} + }, + { + { AOM_CDF11(1865, 1988, 2930, 4242, 10533, + 16538, 21354, 27255, 28546, 31784)}, + { AOM_CDF11(2979, 5958, 8937, 11916, 14895, + 17873, 20852, 23831, 26810, 29789)} + } + }, + { + { + { AOM_CDF11(696, 948, 3145, 5702, 9706, + 13217, 17851, 21856, 25692, 28034)}, + { AOM_CDF11(2979, 5958, 8937, 11916, 14895, + 17873, 20852, 23831, 26810, 29789)} + }, + { + { AOM_CDF11(2672, 3591, 9330, 17084, 22725, + 24284, 26527, 28027, 28377, 30876)}, + { AOM_CDF11(2979, 5958, 8937, 11916, 14895, + 17873, 20852, 23831, 26810, 29789)} + } + }, + { + { + { AOM_CDF11(2784, 3831, 7041, 10521, 14847, + 18844, 23155, 26682, 29229, 31045)}, + { AOM_CDF11(2979, 5958, 8937, 11916, 14895, + 17873, 20852, 23831, 26810, 29789)} + }, + { + { AOM_CDF11(9577, 12466, 17739, 20750, 22061, + 23215, 24601, 25483, 25843, 32056)}, + { AOM_CDF11(2979, 5958, 8937, 11916, 14895, + 17873, 20852, 23831, 26810, 29789)} + } + }, + { + { + { AOM_CDF11(6698, 8334, 11961, 15762, 20186, + 23862, 27434, 29326, 31082, 32050)}, + { AOM_CDF11(2979, 5958, 8937, 11916, 14895, + 17873, 20852, 23831, 26810, 29789)} + }, + { + { AOM_CDF11(20569, 22426, 25569, 26859, 28053, + 28913, 29486, 29724, 29807, 32570)}, + { AOM_CDF11(2979, 5958, 8937, 11916, 14895, + 17873, 20852, 23831, 26810, 29789)} + } + } +}; + +static const u16 av1_default_coeff_lps_multi_cdfs[TOKEN_CDF_Q_CTXS] + [TX_SIZES][PLANE_TYPES][LEVEL_CONTEXTS][CDF_SIZE(BR_CDF_SIZE) + 1] = { + { + { + { + { AOM_CDF4(14298, 20718, 24174)}, { AOM_CDF4(12536, 19601, 23789)}, + { AOM_CDF4(8712, 15051, 19503)}, { AOM_CDF4(6170, 11327, 15434)}, + { AOM_CDF4(4742, 8926, 12538)}, { AOM_CDF4(3803, 7317, 10546)}, + { AOM_CDF4(1696, 3317, 4871)}, { AOM_CDF4(14392, 19951, 22756)}, + { AOM_CDF4(15978, 23218, 26818)}, { AOM_CDF4(12187, 19474, 23889)}, + { AOM_CDF4(9176, 15640, 20259)}, { AOM_CDF4(7068, 12655, 17028)}, + { AOM_CDF4(5656, 10442, 14472)}, { AOM_CDF4(2580, 4992, 7244)}, + { AOM_CDF4(12136, 18049, 21426)}, { AOM_CDF4(13784, 20721, 24481)}, + { AOM_CDF4(10836, 17621, 21900)}, { AOM_CDF4(8372, 14444, 18847)}, + { AOM_CDF4(6523, 11779, 16000)}, { AOM_CDF4(5337, 9898, 13760)}, + { AOM_CDF4(3034, 5860, 8462)} + }, + { + { AOM_CDF4(15967, 22905, 26286)}, { AOM_CDF4(13534, 20654, 24579)}, + { AOM_CDF4(9504, 16092, 20535)}, { AOM_CDF4(6975, 12568, 16903)}, + { AOM_CDF4(5364, 10091, 14020)}, { AOM_CDF4(4357, 8370, 11857)}, + { AOM_CDF4(2506, 4934, 7218)}, { AOM_CDF4(23032, 28815, 30936)}, + { AOM_CDF4(19540, 26704, 29719)}, { AOM_CDF4(15158, 22969, 27097)}, + { AOM_CDF4(11408, 18865, 23650)}, { AOM_CDF4(8885, 15448, 20250)}, + { AOM_CDF4(7108, 12853, 17416)}, { AOM_CDF4(4231, 8041, 11480)}, + { AOM_CDF4(19823, 26490, 29156)}, { AOM_CDF4(18890, 25929, 28932)}, + { AOM_CDF4(15660, 23491, 27433)}, { AOM_CDF4(12147, 19776, 24488)}, + { AOM_CDF4(9728, 16774, 21649)}, { AOM_CDF4(7919, 14277, 19066)}, + { AOM_CDF4(5440, 10170, 14185)} + } + }, + { + { + { AOM_CDF4(14406, 20862, 24414)}, { AOM_CDF4(11824, 18907, 23109)}, + { AOM_CDF4(8257, 14393, 18803)}, { AOM_CDF4(5860, 10747, 14778)}, + { AOM_CDF4(4475, 8486, 11984)}, { AOM_CDF4(3606, 6954, 10043)}, + { AOM_CDF4(1736, 3410, 5048)}, { AOM_CDF4(14430, 20046, 22882)}, + { AOM_CDF4(15593, 22899, 26709)}, { AOM_CDF4(12102, 19368, 23811)}, + { AOM_CDF4(9059, 15584, 20262)}, { AOM_CDF4(6999, 12603, 17048)}, + { AOM_CDF4(5684, 10497, 14553)}, { AOM_CDF4(2822, 5438, 7862)}, + { AOM_CDF4(15785, 21585, 24359)}, { AOM_CDF4(18347, 25229, 28266)}, + { AOM_CDF4(14974, 22487, 26389)}, { AOM_CDF4(11423, 18681, 23271)}, + { AOM_CDF4(8863, 15350, 20008)}, { AOM_CDF4(7153, 12852, 17278)}, + { AOM_CDF4(3707, 7036, 9982)} + }, + { + { AOM_CDF4(15460, 21696, 25469)}, { AOM_CDF4(12170, 19249, 23191)}, + { AOM_CDF4(8723, 15027, 19332)}, { AOM_CDF4(6428, 11704, 15874)}, + { AOM_CDF4(4922, 9292, 13052)}, { AOM_CDF4(4139, 7695, 11010)}, + { AOM_CDF4(2291, 4508, 6598)}, { AOM_CDF4(19856, 26920, 29828)}, + { AOM_CDF4(17923, 25289, 28792)}, { AOM_CDF4(14278, 21968, 26297)}, + { AOM_CDF4(10910, 18136, 22950)}, { AOM_CDF4(8423, 14815, 19627)}, + { AOM_CDF4(6771, 12283, 16774)}, { AOM_CDF4(4074, 7750, 11081)}, + { AOM_CDF4(19852, 26074, 28672)}, { AOM_CDF4(19371, 26110, 28989)}, + { AOM_CDF4(16265, 23873, 27663)}, { AOM_CDF4(12758, 20378, 24952)}, + { AOM_CDF4(10095, 17098, 21961)}, { AOM_CDF4(8250, 14628, 19451)}, + { AOM_CDF4(5205, 9745, 13622)} + } + }, + { + { + { AOM_CDF4(10563, 16233, 19763)}, { AOM_CDF4(9794, 16022, 19804)}, + { AOM_CDF4(6750, 11945, 15759)}, { AOM_CDF4(4963, 9186, 12752)}, + { AOM_CDF4(3845, 7435, 10627)}, { AOM_CDF4(3051, 6085, 8834)}, + { AOM_CDF4(1311, 2596, 3830)}, { AOM_CDF4(11246, 16404, 19689)}, + { AOM_CDF4(12315, 18911, 22731)}, { AOM_CDF4(10557, 17095, 21289)}, + { AOM_CDF4(8136, 14006, 18249)}, { AOM_CDF4(6348, 11474, 15565)}, + { AOM_CDF4(5196, 9655, 13400)}, { AOM_CDF4(2349, 4526, 6587)}, + { AOM_CDF4(13337, 18730, 21569)}, { AOM_CDF4(19306, 26071, 28882)}, + { AOM_CDF4(15952, 23540, 27254)}, { AOM_CDF4(12409, 19934, 24430)}, + { AOM_CDF4(9760, 16706, 21389)}, { AOM_CDF4(8004, 14220, 18818)}, + { AOM_CDF4(4138, 7794, 10961)} + }, + { + { AOM_CDF4(10870, 16684, 20949)}, { AOM_CDF4(9664, 15230, 18680)}, + { AOM_CDF4(6886, 12109, 15408)}, { AOM_CDF4(4825, 8900, 12305)}, + { AOM_CDF4(3630, 7162, 10314)}, { AOM_CDF4(3036, 6429, 9387)}, + { AOM_CDF4(1671, 3296, 4940)}, { AOM_CDF4(13819, 19159, 23026)}, + { AOM_CDF4(11984, 19108, 23120)}, { AOM_CDF4(10690, 17210, 21663)}, + { AOM_CDF4(7984, 14154, 18333)}, { AOM_CDF4(6868, 12294, 16124)}, + { AOM_CDF4(5274, 8994, 12868)}, { AOM_CDF4(2988, 5771, 8424)}, + { AOM_CDF4(19736, 26647, 29141)}, { AOM_CDF4(18933, 26070, 28984)}, + { AOM_CDF4(15779, 23048, 27200)}, { AOM_CDF4(12638, 20061, 24532)}, + { AOM_CDF4(10692, 17545, 22220)}, { AOM_CDF4(9217, 15251, 20054)}, + { AOM_CDF4(5078, 9284, 12594)} + } + }, + { + { + { AOM_CDF4(2331, 3662, 5244)}, { AOM_CDF4(2891, 4771, 6145)}, + { AOM_CDF4(4598, 7623, 9729)}, { AOM_CDF4(3520, 6845, 9199)}, + { AOM_CDF4(3417, 6119, 9324)}, { AOM_CDF4(2601, 5412, 7385)}, + { AOM_CDF4(600, 1173, 1744)}, { AOM_CDF4(7672, 13286, 17469)}, + { AOM_CDF4(4232, 7792, 10793)}, { AOM_CDF4(2915, 5317, 7397)}, + { AOM_CDF4(2318, 4356, 6152)}, { AOM_CDF4(2127, 4000, 5554)}, + { AOM_CDF4(1850, 3478, 5275)}, { AOM_CDF4(977, 1933, 2843)}, + { AOM_CDF4(18280, 24387, 27989)}, { AOM_CDF4(15852, 22671, 26185)}, + { AOM_CDF4(13845, 20951, 24789)}, { AOM_CDF4(11055, 17966, 22129)}, + { AOM_CDF4(9138, 15422, 19801)}, { AOM_CDF4(7454, 13145, 17456)}, + { AOM_CDF4(3370, 6393, 9013)} + }, + { + { AOM_CDF4(5842, 9229, 10838)}, { AOM_CDF4(2313, 3491, 4276)}, + { AOM_CDF4(2998, 6104, 7496)}, { AOM_CDF4(2420, 7447, 9868)}, + { AOM_CDF4(3034, 8495, 10923)}, { AOM_CDF4(4076, 8937, 10975)}, + { AOM_CDF4(1086, 2370, 3299)}, { AOM_CDF4(9714, 17254, 20444)}, + { AOM_CDF4(8543, 13698, 17123)}, { AOM_CDF4(4918, 9007, 11910)}, + { AOM_CDF4(4129, 7532, 10553)}, { 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AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)} + } + } + }, + { + { + { + { AOM_CDF4(14995, 21341, 24749)}, { AOM_CDF4(13158, 20289, 24601)}, + { AOM_CDF4(8941, 15326, 19876)}, { AOM_CDF4(6297, 11541, 15807)}, + { AOM_CDF4(4817, 9029, 12776)}, { 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24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)} + } + } + }, + { + { + { + { AOM_CDF4(16138, 22223, 25509)}, { AOM_CDF4(15347, 22430, 26332)}, + { AOM_CDF4(9614, 16736, 21332)}, { AOM_CDF4(6600, 12275, 16907)}, + { AOM_CDF4(4811, 9424, 13547)}, { AOM_CDF4(3748, 7809, 11420)}, + { AOM_CDF4(2254, 4587, 6890)}, { AOM_CDF4(15196, 20284, 23177)}, + { AOM_CDF4(18317, 25469, 28451)}, { AOM_CDF4(13918, 21651, 25842)}, + { AOM_CDF4(10052, 17150, 21995)}, { AOM_CDF4(7499, 13630, 18587)}, + { AOM_CDF4(6158, 11417, 16003)}, { AOM_CDF4(4014, 7785, 11252)}, + { AOM_CDF4(15048, 21067, 24384)}, { AOM_CDF4(18202, 25346, 28553)}, + { AOM_CDF4(14302, 22019, 26356)}, { AOM_CDF4(10839, 18139, 23166)}, + { AOM_CDF4(8715, 15744, 20806)}, { AOM_CDF4(7536, 13576, 18544)}, + { AOM_CDF4(5413, 10335, 14498)} + }, + { + { AOM_CDF4(17394, 24501, 27895)}, { AOM_CDF4(15889, 23420, 27185)}, + { AOM_CDF4(11561, 19133, 23870)}, { AOM_CDF4(8285, 14812, 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AOM_CDF4(8297, 14642, 19447)}, + { AOM_CDF4(6746, 12389, 16893)}, { AOM_CDF4(4324, 8251, 11770)}, + { AOM_CDF4(16532, 21631, 24475)}, { AOM_CDF4(20667, 27150, 29668)}, + { AOM_CDF4(16728, 24510, 28175)}, { AOM_CDF4(12861, 20645, 25332)}, + { AOM_CDF4(10076, 17361, 22417)}, { AOM_CDF4(8395, 14940, 19963)}, + { AOM_CDF4(5731, 10683, 14912)} + }, + { + { AOM_CDF4(14433, 21155, 24938)}, { AOM_CDF4(14658, 21716, 25545)}, + { AOM_CDF4(9923, 16824, 21557)}, { AOM_CDF4(6982, 13052, 17721)}, + { AOM_CDF4(5419, 10503, 15050)}, { AOM_CDF4(4852, 9162, 13014)}, + { AOM_CDF4(3271, 6395, 9630)}, { AOM_CDF4(22210, 27833, 30109)}, + { AOM_CDF4(20750, 27368, 29821)}, { AOM_CDF4(16894, 24828, 28573)}, + { AOM_CDF4(13247, 21276, 25757)}, { AOM_CDF4(10038, 17265, 22563)}, + { AOM_CDF4(8587, 14947, 20327)}, { AOM_CDF4(5645, 11371, 15252)}, + { AOM_CDF4(22027, 27526, 29714)}, { AOM_CDF4(23098, 29146, 31221)}, + { AOM_CDF4(19886, 27341, 30272)}, { AOM_CDF4(15609, 23747, 28046)}, + { AOM_CDF4(11993, 20065, 24939)}, { AOM_CDF4(9637, 18267, 23671)}, + { AOM_CDF4(7625, 13801, 19144)} + } + }, + { + { + { AOM_CDF4(14438, 20798, 24089)}, { AOM_CDF4(12621, 19203, 23097)}, + { AOM_CDF4(8177, 14125, 18402)}, { AOM_CDF4(5674, 10501, 14456)}, + { AOM_CDF4(4236, 8239, 11733)}, { AOM_CDF4(3447, 6750, 9806)}, + { AOM_CDF4(1986, 3950, 5864)}, { AOM_CDF4(16208, 22099, 24930)}, + { AOM_CDF4(16537, 24025, 27585)}, { AOM_CDF4(12780, 20381, 24867)}, + { AOM_CDF4(9767, 16612, 21416)}, { AOM_CDF4(7686, 13738, 18398)}, + { AOM_CDF4(6333, 11614, 15964)}, { AOM_CDF4(3941, 7571, 10836)}, + { AOM_CDF4(22819, 27422, 29202)}, { AOM_CDF4(22224, 28514, 30721)}, + { AOM_CDF4(17660, 25433, 28913)}, { AOM_CDF4(13574, 21482, 26002)}, + { AOM_CDF4(10629, 17977, 22938)}, { AOM_CDF4(8612, 15298, 20265)}, + { AOM_CDF4(5607, 10491, 14596)} + }, + { + { AOM_CDF4(13569, 19800, 23206)}, { AOM_CDF4(13128, 19924, 23869)}, + { AOM_CDF4(8329, 14841, 19403)}, { AOM_CDF4(6130, 10976, 15057)}, + { AOM_CDF4(4682, 8839, 12518)}, { AOM_CDF4(3656, 7409, 10588)}, + { AOM_CDF4(2577, 5099, 7412)}, { AOM_CDF4(22427, 28684, 30585)}, + { AOM_CDF4(20913, 27750, 30139)}, { AOM_CDF4(15840, 24109, 27834)}, + { AOM_CDF4(12308, 20029, 24569)}, { AOM_CDF4(10216, 16785, 21458)}, + { AOM_CDF4(8309, 14203, 19113)}, { AOM_CDF4(6043, 11168, 15307)}, + { AOM_CDF4(23166, 28901, 30998)}, { AOM_CDF4(21899, 28405, 30751)}, + { AOM_CDF4(18413, 26091, 29443)}, { AOM_CDF4(15233, 23114, 27352)}, + { AOM_CDF4(12683, 20472, 25288)}, { AOM_CDF4(10702, 18259, 23409)}, + { AOM_CDF4(8125, 14464, 19226)} + } + }, + { + { + { AOM_CDF4(9040, 14786, 18360)}, { AOM_CDF4(9979, 15718, 19415)}, + { AOM_CDF4(7913, 13918, 18311)}, { AOM_CDF4(5859, 10889, 15184)}, + { AOM_CDF4(4593, 8677, 12510)}, { AOM_CDF4(3820, 7396, 10791)}, + { AOM_CDF4(1730, 3471, 5192)}, { AOM_CDF4(11803, 18365, 22709)}, + { AOM_CDF4(11419, 18058, 22225)}, { AOM_CDF4(9418, 15774, 20243)}, + { AOM_CDF4(7539, 13325, 17657)}, { AOM_CDF4(6233, 11317, 15384)}, + { AOM_CDF4(5137, 9656, 13545)}, { AOM_CDF4(2977, 5774, 8349)}, + { AOM_CDF4(21207, 27246, 29640)}, { AOM_CDF4(19547, 26578, 29497)}, + { AOM_CDF4(16169, 23871, 27690)}, { AOM_CDF4(12820, 20458, 25018)}, + { AOM_CDF4(10224, 17332, 22214)}, { AOM_CDF4(8526, 15048, 19884)}, + { AOM_CDF4(5037, 9410, 13118)} + }, + { + { AOM_CDF4(12339, 17329, 20140)}, { AOM_CDF4(13505, 19895, 23225)}, + { AOM_CDF4(9847, 16944, 21564)}, { AOM_CDF4(7280, 13256, 18348)}, + { AOM_CDF4(4712, 10009, 14454)}, { AOM_CDF4(4361, 7914, 12477)}, + { AOM_CDF4(2870, 5628, 7995)}, { AOM_CDF4(20061, 25504, 28526)}, + { AOM_CDF4(15235, 22878, 26145)}, { AOM_CDF4(12985, 19958, 24155)}, + { AOM_CDF4(9782, 16641, 21403)}, { AOM_CDF4(9456, 16360, 20760)}, + { AOM_CDF4(6855, 12940, 18557)}, { AOM_CDF4(5661, 10564, 15002)}, + { AOM_CDF4(25656, 30602, 31894)}, { AOM_CDF4(22570, 29107, 31092)}, + { AOM_CDF4(18917, 26423, 29541)}, { AOM_CDF4(15940, 23649, 27754)}, + { AOM_CDF4(12803, 20581, 25219)}, { AOM_CDF4(11082, 18695, 23376)}, + { AOM_CDF4(7939, 14373, 19005)} + } + }, + { + { + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)} + } + } + }, + { + { + { + { AOM_CDF4(18315, 24289, 27551)}, { AOM_CDF4(16854, 24068, 27835)}, + { AOM_CDF4(10140, 17927, 23173)}, { AOM_CDF4(6722, 12982, 18267)}, + { AOM_CDF4(4661, 9826, 14706)}, { AOM_CDF4(3832, 8165, 12294)}, + { AOM_CDF4(2795, 6098, 9245)}, { AOM_CDF4(17145, 23326, 26672)}, + { AOM_CDF4(20733, 27680, 30308)}, { AOM_CDF4(16032, 24461, 28546)}, + { AOM_CDF4(11653, 20093, 25081)}, { AOM_CDF4(9290, 16429, 22086)}, + { AOM_CDF4(7796, 14598, 19982)}, { AOM_CDF4(6502, 12378, 17441)}, + { AOM_CDF4(21681, 27732, 30320)}, { AOM_CDF4(22389, 29044, 31261)}, + { AOM_CDF4(19027, 26731, 30087)}, { AOM_CDF4(14739, 23755, 28624)}, + { AOM_CDF4(11358, 20778, 25511)}, { AOM_CDF4(10995, 18073, 24190)}, + { AOM_CDF4(9162, 14990, 20617)} + }, + { + { AOM_CDF4(21425, 27952, 30388)}, { AOM_CDF4(18062, 25838, 29034)}, + { AOM_CDF4(11956, 19881, 24808)}, { AOM_CDF4(7718, 15000, 20980)}, + { AOM_CDF4(5702, 11254, 16143)}, { AOM_CDF4(4898, 9088, 16864)}, + { AOM_CDF4(3679, 6776, 11907)}, { AOM_CDF4(23294, 30160, 31663)}, + { AOM_CDF4(24397, 29896, 31836)}, { AOM_CDF4(19245, 27128, 30593)}, + { AOM_CDF4(13202, 19825, 26404)}, { AOM_CDF4(11578, 19297, 23957)}, + { AOM_CDF4(8073, 13297, 21370)}, { AOM_CDF4(5461, 10923, 19745)}, + { AOM_CDF4(27367, 30521, 31934)}, { AOM_CDF4(24904, 30671, 31940)}, + { AOM_CDF4(23075, 28460, 31299)}, { AOM_CDF4(14400, 23658, 30417)}, + { AOM_CDF4(13885, 23882, 28325)}, { AOM_CDF4(14746, 22938, 27853)}, + { AOM_CDF4(5461, 16384, 27307)} + } + }, + { + { + { AOM_CDF4(18274, 24813, 27890)}, { AOM_CDF4(15537, 23149, 27003)}, + { AOM_CDF4(9449, 16740, 21827)}, { AOM_CDF4(6700, 12498, 17261)}, + { AOM_CDF4(4988, 9866, 14198)}, { AOM_CDF4(4236, 8147, 11902)}, + { AOM_CDF4(2867, 5860, 8654)}, { AOM_CDF4(17124, 23171, 26101)}, + { AOM_CDF4(20396, 27477, 30148)}, { AOM_CDF4(16573, 24629, 28492)}, + { AOM_CDF4(12749, 20846, 25674)}, { AOM_CDF4(10233, 17878, 22818)}, + { AOM_CDF4(8525, 15332, 20363)}, { AOM_CDF4(6283, 11632, 16255)}, + { AOM_CDF4(20466, 26511, 29286)}, { AOM_CDF4(23059, 29174, 31191)}, + { AOM_CDF4(19481, 27263, 30241)}, { AOM_CDF4(15458, 23631, 28137)}, + { AOM_CDF4(12416, 20608, 25693)}, { AOM_CDF4(10261, 18011, 23261)}, + { AOM_CDF4(8016, 14655, 19666)} + }, + { + { AOM_CDF4(17616, 24586, 28112)}, { AOM_CDF4(15809, 23299, 27155)}, + { AOM_CDF4(10767, 18890, 23793)}, { AOM_CDF4(7727, 14255, 18865)}, + { AOM_CDF4(6129, 11926, 16882)}, { AOM_CDF4(4482, 9704, 14861)}, + { AOM_CDF4(3277, 7452, 11522)}, { AOM_CDF4(22956, 28551, 30730)}, + { AOM_CDF4(22724, 28937, 30961)}, { AOM_CDF4(18467, 26324, 29580)}, + { AOM_CDF4(13234, 20713, 25649)}, { AOM_CDF4(11181, 17592, 22481)}, + { AOM_CDF4(8291, 18358, 24576)}, { AOM_CDF4(7568, 11881, 14984)}, + { AOM_CDF4(24948, 29001, 31147)}, { AOM_CDF4(25674, 30619, 32151)}, + { AOM_CDF4(20841, 26793, 29603)}, { AOM_CDF4(14669, 24356, 28666)}, + { AOM_CDF4(11334, 23593, 28219)}, { AOM_CDF4(8922, 14762, 22873)}, + { AOM_CDF4(8301, 13544, 20535)} + } + }, + { + { + { AOM_CDF4(17113, 23733, 27081)}, { AOM_CDF4(14139, 21406, 25452)}, + { AOM_CDF4(8552, 15002, 19776)}, { AOM_CDF4(5871, 11120, 15378)}, + { AOM_CDF4(4455, 8616, 12253)}, { AOM_CDF4(3469, 6910, 10386)}, + { AOM_CDF4(2255, 4553, 6782)}, { AOM_CDF4(18224, 24376, 27053)}, + { AOM_CDF4(19290, 26710, 29614)}, { AOM_CDF4(14936, 22991, 27184)}, + { AOM_CDF4(11238, 18951, 23762)}, { AOM_CDF4(8786, 15617, 20588)}, + { AOM_CDF4(7317, 13228, 18003)}, { AOM_CDF4(5101, 9512, 13493)}, + { AOM_CDF4(22639, 28222, 30210)}, { AOM_CDF4(23216, 29331, 31307)}, + { AOM_CDF4(19075, 26762, 29895)}, { AOM_CDF4(15014, 23113, 27457)}, + { AOM_CDF4(11938, 19857, 24752)}, { AOM_CDF4(9942, 17280, 22282)}, + { AOM_CDF4(7167, 13144, 17752)} + }, + { + { AOM_CDF4(15820, 22738, 26488)}, { AOM_CDF4(13530, 20885, 25216)}, + { AOM_CDF4(8395, 15530, 20452)}, { AOM_CDF4(6574, 12321, 16380)}, + { AOM_CDF4(5353, 10419, 14568)}, { AOM_CDF4(4613, 8446, 12381)}, + { AOM_CDF4(3440, 7158, 9903)}, { AOM_CDF4(24247, 29051, 31224)}, + { AOM_CDF4(22118, 28058, 30369)}, { AOM_CDF4(16498, 24768, 28389)}, + { AOM_CDF4(12920, 21175, 26137)}, { AOM_CDF4(10730, 18619, 25352)}, + { AOM_CDF4(10187, 16279, 22791)}, { AOM_CDF4(9310, 14631, 22127)}, + { AOM_CDF4(24970, 30558, 32057)}, { AOM_CDF4(24801, 29942, 31698)}, + { AOM_CDF4(22432, 28453, 30855)}, { AOM_CDF4(19054, 25680, 29580)}, + { AOM_CDF4(14392, 23036, 28109)}, { AOM_CDF4(12495, 20947, 26650)}, + { AOM_CDF4(12442, 20326, 26214)} + } + }, + { + { + { AOM_CDF4(12162, 18785, 22648)}, { AOM_CDF4(12749, 19697, 23806)}, + { AOM_CDF4(8580, 15297, 20346)}, { AOM_CDF4(6169, 11749, 16543)}, + { AOM_CDF4(4836, 9391, 13448)}, { AOM_CDF4(3821, 7711, 11613)}, + { AOM_CDF4(2228, 4601, 7070)}, { AOM_CDF4(16319, 24725, 28280)}, + { AOM_CDF4(15698, 23277, 27168)}, { AOM_CDF4(12726, 20368, 25047)}, + { AOM_CDF4(9912, 17015, 21976)}, { AOM_CDF4(7888, 14220, 19179)}, + { AOM_CDF4(6777, 12284, 17018)}, { AOM_CDF4(4492, 8590, 12252)}, + { AOM_CDF4(23249, 28904, 30947)}, { AOM_CDF4(21050, 27908, 30512)}, + { AOM_CDF4(17440, 25340, 28949)}, { AOM_CDF4(14059, 22018, 26541)}, + { AOM_CDF4(11288, 18903, 23898)}, { AOM_CDF4(9411, 16342, 21428)}, + { AOM_CDF4(6278, 11588, 15944)} + }, + { + { AOM_CDF4(13981, 20067, 23226)}, { AOM_CDF4(16922, 23580, 26783)}, + { AOM_CDF4(11005, 19039, 24487)}, { AOM_CDF4(7389, 14218, 19798)}, + { AOM_CDF4(5598, 11505, 17206)}, { AOM_CDF4(6090, 11213, 15659)}, + { AOM_CDF4(3820, 7371, 10119)}, { AOM_CDF4(21082, 26925, 29675)}, + { AOM_CDF4(21262, 28627, 31128)}, { AOM_CDF4(18392, 26454, 30437)}, + { AOM_CDF4(14870, 22910, 27096)}, { AOM_CDF4(12620, 19484, 24908)}, + { AOM_CDF4(9290, 16553, 22802)}, { AOM_CDF4(6668, 14288, 20004)}, + { AOM_CDF4(27704, 31055, 31949)}, { AOM_CDF4(24709, 29978, 31788)}, + { AOM_CDF4(21668, 29264, 31657)}, { AOM_CDF4(18295, 26968, 30074)}, + { AOM_CDF4(16399, 24422, 29313)}, { AOM_CDF4(14347, 23026, 28104)}, + { AOM_CDF4(12370, 19806, 24477)} + } + }, + { + { + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)} + } + } + } +}; + +static const u16 av1_default_coeff_base_multi_cdfs + [TOKEN_CDF_Q_CTXS][TX_SIZES][PLANE_TYPES] + [SIG_COEF_CONTEXTS][CDF_SIZE(NUM_BASE_LEVELS + 2) + 1] = { + { + { + { + { AOM_CDF4(4034, 8930, 12727)}, { AOM_CDF4(18082, 29741, 31877)}, + { AOM_CDF4(12596, 26124, 30493)}, { AOM_CDF4(9446, 21118, 27005)}, + { AOM_CDF4(6308, 15141, 21279)}, { AOM_CDF4(2463, 6357, 9783)}, + { AOM_CDF4(20667, 30546, 31929)}, { AOM_CDF4(13043, 26123, 30134)}, + { AOM_CDF4(8151, 18757, 24778)}, { AOM_CDF4(5255, 12839, 18632)}, + { AOM_CDF4(2820, 7206, 11161)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(15736, 27553, 30604)}, + { AOM_CDF4(11210, 23794, 28787)}, { AOM_CDF4(5947, 13874, 19701)}, + { AOM_CDF4(4215, 9323, 13891)}, { AOM_CDF4(2833, 6462, 10059)}, + { AOM_CDF4(19605, 30393, 31582)}, { AOM_CDF4(13523, 26252, 30248)}, + { AOM_CDF4(8446, 18622, 24512)}, { AOM_CDF4(3818, 10343, 15974)}, + { AOM_CDF4(1481, 4117, 6796)}, { AOM_CDF4(22649, 31302, 32190)}, + { AOM_CDF4(14829, 27127, 30449)}, { AOM_CDF4(8313, 17702, 23304)}, + { AOM_CDF4(3022, 8301, 12786)}, { AOM_CDF4(1536, 4412, 7184)}, + { AOM_CDF4(22354, 29774, 31372)}, { AOM_CDF4(14723, 25472, 29214)}, + { AOM_CDF4(6673, 13745, 18662)}, { AOM_CDF4(2068, 5766, 9322)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(6302, 16444, 21761)}, { AOM_CDF4(23040, 31538, 32475)}, + { AOM_CDF4(15196, 28452, 31496)}, { AOM_CDF4(10020, 22946, 28514)}, + { AOM_CDF4(6533, 16862, 23501)}, { AOM_CDF4(3538, 9816, 15076)}, + { AOM_CDF4(24444, 31875, 32525)}, { AOM_CDF4(15881, 28924, 31635)}, + { AOM_CDF4(9922, 22873, 28466)}, { AOM_CDF4(6527, 16966, 23691)}, + { AOM_CDF4(4114, 11303, 17220)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(20201, 30770, 32209)}, + { AOM_CDF4(14754, 28071, 31258)}, { AOM_CDF4(8378, 20186, 26517)}, + { AOM_CDF4(5916, 15299, 21978)}, { AOM_CDF4(4268, 11583, 17901)}, + { AOM_CDF4(24361, 32025, 32581)}, { AOM_CDF4(18673, 30105, 31943)}, + { AOM_CDF4(10196, 22244, 27576)}, { AOM_CDF4(5495, 14349, 20417)}, + { AOM_CDF4(2676, 7415, 11498)}, { AOM_CDF4(24678, 31958, 32585)}, + { AOM_CDF4(18629, 29906, 31831)}, { AOM_CDF4(9364, 20724, 26315)}, + { AOM_CDF4(4641, 12318, 18094)}, { AOM_CDF4(2758, 7387, 11579)}, + { AOM_CDF4(25433, 31842, 32469)}, { AOM_CDF4(18795, 29289, 31411)}, + { AOM_CDF4(7644, 17584, 23592)}, { AOM_CDF4(3408, 9014, 15047)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(4536, 10072, 14001)}, { AOM_CDF4(25459, 31416, 32206)}, + { AOM_CDF4(16605, 28048, 30818)}, { AOM_CDF4(11008, 22857, 27719)}, + { AOM_CDF4(6915, 16268, 22315)}, { AOM_CDF4(2625, 6812, 10537)}, + { AOM_CDF4(24257, 31788, 32499)}, { AOM_CDF4(16880, 29454, 31879)}, + { AOM_CDF4(11958, 25054, 29778)}, { AOM_CDF4(7916, 18718, 25084)}, + { AOM_CDF4(3383, 8777, 13446)}, { AOM_CDF4(22720, 31603, 32393)}, + { AOM_CDF4(14960, 28125, 31335)}, { AOM_CDF4(9731, 22210, 27928)}, + { AOM_CDF4(6304, 15832, 22277)}, { AOM_CDF4(2910, 7818, 12166)}, + { AOM_CDF4(20375, 30627, 32131)}, { AOM_CDF4(13904, 27284, 30887)}, + { AOM_CDF4(9368, 21558, 27144)}, { AOM_CDF4(5937, 14966, 21119)}, + { AOM_CDF4(2667, 7225, 11319)}, { AOM_CDF4(23970, 31470, 32378)}, + { AOM_CDF4(17173, 29734, 32018)}, { AOM_CDF4(12795, 25441, 29965)}, + { AOM_CDF4(8981, 19680, 25893)}, { AOM_CDF4(4728, 11372, 16902)}, + { AOM_CDF4(24287, 31797, 32439)}, { AOM_CDF4(16703, 29145, 31696)}, + { AOM_CDF4(10833, 23554, 28725)}, { AOM_CDF4(6468, 16566, 23057)}, + { AOM_CDF4(2415, 6562, 10278)}, { AOM_CDF4(26610, 32395, 32659)}, + { AOM_CDF4(18590, 30498, 32117)}, { AOM_CDF4(12420, 25756, 29950)}, + { AOM_CDF4(7639, 18746, 24710)}, { AOM_CDF4(3001, 8086, 12347)}, + { AOM_CDF4(25076, 32064, 32580)}, { AOM_CDF4(17946, 30128, 32028)}, + { AOM_CDF4(12024, 24985, 29378)}, { AOM_CDF4(7517, 18390, 24304)}, + { AOM_CDF4(3243, 8781, 13331)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(6037, 16771, 21957)}, { AOM_CDF4(24774, 31704, 32426)}, + { AOM_CDF4(16830, 28589, 31056)}, { AOM_CDF4(10602, 22828, 27760)}, + { AOM_CDF4(6733, 16829, 23071)}, { AOM_CDF4(3250, 8914, 13556)}, + { AOM_CDF4(25582, 32220, 32668)}, { AOM_CDF4(18659, 30342, 32223)}, + { AOM_CDF4(12546, 26149, 30515)}, { AOM_CDF4(8420, 20451, 26801)}, + { AOM_CDF4(4636, 12420, 18344)}, { AOM_CDF4(27581, 32362, 32639)}, + { AOM_CDF4(18987, 30083, 31978)}, { AOM_CDF4(11327, 24248, 29084)}, + { AOM_CDF4(7264, 17719, 24120)}, { AOM_CDF4(3995, 10768, 16169)}, + { AOM_CDF4(25893, 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{ AOM_CDF4(8147, 17962, 22952)}, + { AOM_CDF4(5242, 13061, 18532)}, { AOM_CDF4(1889, 5208, 8182)}, + { AOM_CDF4(26774, 32133, 32590)}, { AOM_CDF4(17844, 29564, 31767)}, + { AOM_CDF4(11690, 24438, 29171)}, { AOM_CDF4(7542, 18215, 24459)}, + { AOM_CDF4(2993, 8050, 12319)}, { AOM_CDF4(28023, 32328, 32591)}, + { AOM_CDF4(18651, 30126, 31954)}, { AOM_CDF4(12164, 25146, 29589)}, + { AOM_CDF4(7762, 18530, 24771)}, { AOM_CDF4(3492, 9183, 13920)}, + { AOM_CDF4(27591, 32008, 32491)}, { AOM_CDF4(17149, 28853, 31510)}, + { AOM_CDF4(11485, 24003, 28860)}, { AOM_CDF4(7697, 18086, 24210)}, + { AOM_CDF4(3075, 7999, 12218)}, { AOM_CDF4(28268, 32482, 32654)}, + { AOM_CDF4(19631, 31051, 32404)}, { AOM_CDF4(13860, 27260, 31020)}, + { AOM_CDF4(9605, 21613, 27594)}, { AOM_CDF4(4876, 12162, 17908)}, + { AOM_CDF4(27248, 32316, 32576)}, { AOM_CDF4(18955, 30457, 32075)}, + { AOM_CDF4(11824, 23997, 28795)}, { AOM_CDF4(7346, 18196, 24647)}, + { AOM_CDF4(3403, 9247, 14111)}, { AOM_CDF4(29711, 32655, 32735)}, + { AOM_CDF4(21169, 31394, 32417)}, { AOM_CDF4(13487, 27198, 30957)}, + { AOM_CDF4(8828, 21683, 27614)}, { AOM_CDF4(4270, 11451, 17038)}, + { AOM_CDF4(28708, 32578, 32731)}, { AOM_CDF4(20120, 31241, 32482)}, + { AOM_CDF4(13692, 27550, 31321)}, { AOM_CDF4(9418, 22514, 28439)}, + { AOM_CDF4(4999, 13283, 19462)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(5673, 14302, 19711)}, { AOM_CDF4(26251, 30701, 31834)}, + { AOM_CDF4(12782, 23783, 27803)}, { AOM_CDF4(9127, 20657, 25808)}, + { AOM_CDF4(6368, 16208, 21462)}, { AOM_CDF4(2465, 7177, 10822)}, + { AOM_CDF4(29961, 32563, 32719)}, { AOM_CDF4(18318, 29891, 31949)}, + { AOM_CDF4(11361, 24514, 29357)}, { AOM_CDF4(7900, 19603, 25607)}, + { AOM_CDF4(4002, 10590, 15546)}, { AOM_CDF4(29637, 32310, 32595)}, + { AOM_CDF4(18296, 29913, 31809)}, { AOM_CDF4(10144, 21515, 26871)}, + { AOM_CDF4(5358, 14322, 20394)}, { AOM_CDF4(3067, 8362, 13346)}, + { AOM_CDF4(28652, 32470, 32676)}, { AOM_CDF4(17538, 30771, 32209)}, + { AOM_CDF4(13924, 26882, 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AOM_CDF4(443, 1361, 2254)}, + { AOM_CDF4(26083, 31153, 32436)}, { AOM_CDF4(13486, 24603, 28483)}, + { AOM_CDF4(6508, 14840, 19910)}, { AOM_CDF4(3386, 8800, 13286)}, + { AOM_CDF4(1530, 4322, 7054)}, { AOM_CDF4(29639, 32080, 32548)}, + { AOM_CDF4(15897, 27552, 30290)}, { AOM_CDF4(8588, 20047, 25383)}, + { AOM_CDF4(4889, 13339, 19269)}, { AOM_CDF4(2240, 6871, 10498)}, + { AOM_CDF4(28165, 32197, 32517)}, { AOM_CDF4(20735, 30427, 31568)}, + { AOM_CDF4(14325, 24671, 27692)}, { AOM_CDF4(5119, 12554, 17805)}, + { AOM_CDF4(1810, 5441, 8261)}, { AOM_CDF4(31212, 32724, 32748)}, + { AOM_CDF4(23352, 31766, 32545)}, { AOM_CDF4(14669, 27570, 31059)}, + { AOM_CDF4(8492, 20894, 27272)}, { AOM_CDF4(3644, 10194, 15204)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(2461, 7013, 9371)}, { AOM_CDF4(24749, 29600, 30986)}, + { AOM_CDF4(9466, 19037, 22417)}, { AOM_CDF4(3584, 9280, 14400)}, + { AOM_CDF4(1505, 3929, 5433)}, { AOM_CDF4(677, 1500, 2736)}, + { AOM_CDF4(23987, 30702, 32117)}, { AOM_CDF4(13554, 24571, 29263)}, + { AOM_CDF4(6211, 14556, 21155)}, { AOM_CDF4(3135, 10972, 15625)}, + { AOM_CDF4(2435, 7127, 11427)}, { AOM_CDF4(31300, 32532, 32550)}, + { AOM_CDF4(14757, 30365, 31954)}, { AOM_CDF4(4405, 11612, 18553)}, + { AOM_CDF4(580, 4132, 7322)}, { AOM_CDF4(1695, 10169, 14124)}, + { AOM_CDF4(30008, 32282, 32591)}, { AOM_CDF4(19244, 30108, 31748)}, + { AOM_CDF4(11180, 24158, 29555)}, { AOM_CDF4(5650, 14972, 19209)}, + { AOM_CDF4(2114, 5109, 8456)}, { AOM_CDF4(31856, 32716, 32748)}, + { AOM_CDF4(23012, 31664, 32572)}, { AOM_CDF4(13694, 26656, 30636)}, + { AOM_CDF4(8142, 19508, 26093)}, { AOM_CDF4(4253, 10955, 16724)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(601, 983, 1311)}, { AOM_CDF4(18725, 23406, 28087)}, + { AOM_CDF4(5461, 8192, 10923)}, { AOM_CDF4(3781, 15124, 21425)}, + { AOM_CDF4(2587, 7761, 12072)}, { AOM_CDF4(106, 458, 810)}, + { AOM_CDF4(22282, 29710, 31894)}, { AOM_CDF4(8508, 20926, 25984)}, + { AOM_CDF4(3726, 12713, 18083)}, { AOM_CDF4(1620, 7112, 10893)}, + { AOM_CDF4(729, 2236, 3495)}, { AOM_CDF4(30163, 32474, 32684)}, + { AOM_CDF4(18304, 30464, 32000)}, { AOM_CDF4(11443, 26526, 29647)}, + { AOM_CDF4(6007, 15292, 21299)}, { AOM_CDF4(2234, 6703, 8937)}, + { AOM_CDF4(30954, 32177, 32571)}, { AOM_CDF4(17363, 29562, 31076)}, + { AOM_CDF4(9686, 22464, 27410)}, { AOM_CDF4(8192, 16384, 21390)}, + { AOM_CDF4(1755, 8046, 11264)}, { AOM_CDF4(31168, 32734, 32748)}, + { AOM_CDF4(22486, 31441, 32471)}, { AOM_CDF4(12833, 25627, 29738)}, + { AOM_CDF4(6980, 17379, 23122)}, { AOM_CDF4(3111, 8887, 13479)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + } + }, + { + { + { + { AOM_CDF4(6041, 11854, 15927)}, { AOM_CDF4(20326, 30905, 32251)}, + { AOM_CDF4(14164, 26831, 30725)}, { AOM_CDF4(9760, 20647, 26585)}, + { AOM_CDF4(6416, 14953, 21219)}, { AOM_CDF4(2966, 7151, 10891)}, + { AOM_CDF4(23567, 31374, 32254)}, { AOM_CDF4(14978, 27416, 30946)}, + { AOM_CDF4(9434, 20225, 26254)}, { AOM_CDF4(6658, 14558, 20535)}, + { AOM_CDF4(3916, 8677, 12989)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(18088, 29545, 31587)}, + { AOM_CDF4(13062, 25843, 30073)}, { AOM_CDF4(8940, 16827, 22251)}, + { AOM_CDF4(7654, 13220, 17973)}, { AOM_CDF4(5733, 10316, 14456)}, + { AOM_CDF4(22879, 31388, 32114)}, { AOM_CDF4(15215, 27993, 30955)}, + { AOM_CDF4(9397, 19445, 24978)}, { AOM_CDF4(3442, 9813, 15344)}, + { AOM_CDF4(1368, 3936, 6532)}, { AOM_CDF4(25494, 32033, 32406)}, + { AOM_CDF4(16772, 27963, 30718)}, { AOM_CDF4(9419, 18165, 23260)}, + { AOM_CDF4(2677, 7501, 11797)}, { AOM_CDF4(1516, 4344, 7170)}, + { AOM_CDF4(26556, 31454, 32101)}, { AOM_CDF4(17128, 27035, 30108)}, + { AOM_CDF4(8324, 15344, 20249)}, { AOM_CDF4(1903, 5696, 9469)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(8455, 19003, 24368)}, { AOM_CDF4(23563, 32021, 32604)}, + { AOM_CDF4(16237, 29446, 31935)}, { AOM_CDF4(10724, 23999, 29358)}, + { AOM_CDF4(6725, 17528, 24416)}, { AOM_CDF4(3927, 10927, 16825)}, + { AOM_CDF4(26313, 32288, 32634)}, { AOM_CDF4(17430, 30095, 32095)}, + { AOM_CDF4(11116, 24606, 29679)}, { AOM_CDF4(7195, 18384, 25269)}, + { AOM_CDF4(4726, 12852, 19315)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(22822, 31648, 32483)}, + { AOM_CDF4(16724, 29633, 31929)}, { AOM_CDF4(10261, 23033, 28725)}, + { AOM_CDF4(7029, 17840, 24528)}, { AOM_CDF4(4867, 13886, 21502)}, + { AOM_CDF4(25298, 31892, 32491)}, { AOM_CDF4(17809, 29330, 31512)}, + { AOM_CDF4(9668, 21329, 26579)}, { AOM_CDF4(4774, 12956, 18976)}, + { AOM_CDF4(2322, 7030, 11540)}, { AOM_CDF4(25472, 31920, 32543)}, + { AOM_CDF4(17957, 29387, 31632)}, { AOM_CDF4(9196, 20593, 26400)}, + { AOM_CDF4(4680, 12705, 19202)}, { AOM_CDF4(2917, 8456, 13436)}, + { AOM_CDF4(26471, 32059, 32574)}, { AOM_CDF4(18458, 29783, 31909)}, + { AOM_CDF4(8400, 19464, 25956)}, { AOM_CDF4(3812, 10973, 17206)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(6779, 13743, 17678)}, { AOM_CDF4(24806, 31797, 32457)}, + { AOM_CDF4(17616, 29047, 31372)}, { AOM_CDF4(11063, 23175, 28003)}, + { AOM_CDF4(6521, 16110, 22324)}, { AOM_CDF4(2764, 7504, 11654)}, + { AOM_CDF4(25266, 32367, 32637)}, { AOM_CDF4(19054, 30553, 32175)}, + { AOM_CDF4(12139, 25212, 29807)}, { AOM_CDF4(7311, 18162, 24704)}, + { AOM_CDF4(3397, 9164, 14074)}, { AOM_CDF4(25988, 32208, 32522)}, + { AOM_CDF4(16253, 28912, 31526)}, { AOM_CDF4(9151, 21387, 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19339, 24429)}, { AOM_CDF4(24404, 31837, 32525)}, + { AOM_CDF4(16997, 29425, 31784)}, { AOM_CDF4(11253, 24234, 29149)}, + { AOM_CDF4(6751, 17394, 24028)}, { AOM_CDF4(3490, 9830, 15191)}, + { AOM_CDF4(26283, 32471, 32714)}, { AOM_CDF4(19599, 31168, 32442)}, + { AOM_CDF4(13146, 26954, 30893)}, { AOM_CDF4(8214, 20588, 26890)}, + { AOM_CDF4(4699, 13081, 19300)}, { AOM_CDF4(28212, 32458, 32669)}, + { AOM_CDF4(18594, 30316, 32100)}, { AOM_CDF4(11219, 24408, 29234)}, + { AOM_CDF4(6865, 17656, 24149)}, { AOM_CDF4(3678, 10362, 16006)}, + { AOM_CDF4(25825, 32136, 32616)}, { AOM_CDF4(17313, 29853, 32021)}, + { AOM_CDF4(11197, 24471, 29472)}, { AOM_CDF4(6947, 17781, 24405)}, + { AOM_CDF4(3768, 10660, 16261)}, { AOM_CDF4(27352, 32500, 32706)}, + { AOM_CDF4(20850, 31468, 32469)}, { AOM_CDF4(14021, 27707, 31133)}, + { AOM_CDF4(8964, 21748, 27838)}, { AOM_CDF4(5437, 14665, 21187)}, + { AOM_CDF4(26304, 32492, 32698)}, { AOM_CDF4(20409, 31380, 32385)}, + { AOM_CDF4(13682, 27222, 30632)}, { AOM_CDF4(8974, 21236, 26685)}, + { AOM_CDF4(4234, 11665, 16934)}, { AOM_CDF4(26273, 32357, 32711)}, + { AOM_CDF4(20672, 31242, 32441)}, { AOM_CDF4(14172, 27254, 30902)}, + { AOM_CDF4(9870, 21898, 27275)}, { AOM_CDF4(5164, 13506, 19270)}, + { AOM_CDF4(26725, 32459, 32728)}, { AOM_CDF4(20991, 31442, 32527)}, + { AOM_CDF4(13071, 26434, 30811)}, { AOM_CDF4(8184, 20090, 26742)}, + { AOM_CDF4(4803, 13255, 19895)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(7555, 14942, 18501)}, { AOM_CDF4(24410, 31178, 32287)}, + { AOM_CDF4(14394, 26738, 30253)}, { AOM_CDF4(8413, 19554, 25195)}, + { AOM_CDF4(4766, 12924, 18785)}, { AOM_CDF4(2029, 5806, 9207)}, + { AOM_CDF4(26776, 32364, 32663)}, { AOM_CDF4(18732, 29967, 31931)}, + { AOM_CDF4(11005, 23786, 28852)}, { AOM_CDF4(6466, 16909, 23510)}, + { AOM_CDF4(3044, 8638, 13419)}, { AOM_CDF4(29208, 32582, 32704)}, + { AOM_CDF4(20068, 30857, 32208)}, { AOM_CDF4(12003, 25085, 29595)}, + { AOM_CDF4(6947, 17750, 24189)}, { AOM_CDF4(3245, 9103, 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AOM_CDF4(14774, 27149, 30607)}, { AOM_CDF4(9257, 21438, 26972)}, + { AOM_CDF4(5723, 15183, 21882)}, { AOM_CDF4(3150, 8879, 13731)}, + { AOM_CDF4(26989, 32262, 32682)}, { AOM_CDF4(17396, 29937, 32085)}, + { AOM_CDF4(11387, 24901, 29784)}, { AOM_CDF4(7289, 18821, 25548)}, + { AOM_CDF4(3734, 10577, 16086)}, { AOM_CDF4(29728, 32501, 32695)}, + { AOM_CDF4(17431, 29701, 31903)}, { AOM_CDF4(9921, 22826, 28300)}, + { AOM_CDF4(5896, 15434, 22068)}, { AOM_CDF4(3430, 9646, 14757)}, + { AOM_CDF4(28614, 32511, 32705)}, { AOM_CDF4(19364, 30638, 32263)}, + { AOM_CDF4(13129, 26254, 30402)}, { AOM_CDF4(8754, 20484, 26440)}, + { AOM_CDF4(4378, 11607, 17110)}, { AOM_CDF4(30292, 32671, 32744)}, + { AOM_CDF4(21780, 31603, 32501)}, { AOM_CDF4(14314, 27829, 31291)}, + { AOM_CDF4(9611, 22327, 28263)}, { AOM_CDF4(4890, 13087, 19065)}, + { AOM_CDF4(25862, 32567, 32733)}, { AOM_CDF4(20794, 32050, 32567)}, + { AOM_CDF4(17243, 30625, 32254)}, { AOM_CDF4(13283, 27628, 31474)}, + { AOM_CDF4(9669, 22532, 28918)}, { AOM_CDF4(27435, 32697, 32748)}, + { AOM_CDF4(24922, 32390, 32714)}, { AOM_CDF4(21449, 31504, 32536)}, + { AOM_CDF4(16392, 29729, 31832)}, { AOM_CDF4(11692, 24884, 29076)}, + { AOM_CDF4(24193, 32290, 32735)}, { AOM_CDF4(18909, 31104, 32563)}, + { AOM_CDF4(12236, 26841, 31403)}, { AOM_CDF4(8171, 21840, 29082)}, + { AOM_CDF4(7224, 17280, 25275)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(3078, 6839, 9890)}, { AOM_CDF4(13837, 20450, 24479)}, + { AOM_CDF4(5914, 14222, 19328)}, { AOM_CDF4(3866, 10267, 14762)}, + { AOM_CDF4(2612, 7208, 11042)}, { AOM_CDF4(1067, 2991, 4776)}, + { AOM_CDF4(25817, 31646, 32529)}, { AOM_CDF4(13708, 26338, 30385)}, + { AOM_CDF4(7328, 18585, 24870)}, { AOM_CDF4(4691, 13080, 19276)}, + { AOM_CDF4(1825, 5253, 8352)}, { AOM_CDF4(29386, 32315, 32624)}, + { AOM_CDF4(17160, 29001, 31360)}, { AOM_CDF4(9602, 21862, 27396)}, + { AOM_CDF4(5915, 15772, 22148)}, { AOM_CDF4(2786, 7779, 12047)}, + { AOM_CDF4(29246, 32450, 32663)}, { AOM_CDF4(18696, 29929, 31818)}, + { AOM_CDF4(10510, 23369, 28560)}, { AOM_CDF4(6229, 16499, 23125)}, + { AOM_CDF4(2608, 7448, 11705)}, { AOM_CDF4(30753, 32710, 32748)}, + { AOM_CDF4(21638, 31487, 32503)}, { AOM_CDF4(12937, 26854, 30870)}, + { AOM_CDF4(8182, 20596, 26970)}, { AOM_CDF4(3637, 10269, 15497)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(5244, 12150, 16906)}, { AOM_CDF4(20486, 26858, 29701)}, + { AOM_CDF4(7756, 18317, 23735)}, { AOM_CDF4(3452, 9256, 13146)}, + { AOM_CDF4(2020, 5206, 8229)}, { AOM_CDF4(1801, 4993, 7903)}, + { AOM_CDF4(27051, 31858, 32531)}, { AOM_CDF4(15988, 27531, 30619)}, + { AOM_CDF4(9188, 21484, 26719)}, { AOM_CDF4(6273, 17186, 23800)}, + { AOM_CDF4(3108, 9355, 14764)}, { AOM_CDF4(31076, 32520, 32680)}, + { AOM_CDF4(18119, 30037, 31850)}, { AOM_CDF4(10244, 22969, 27472)}, + { AOM_CDF4(4692, 14077, 19273)}, { AOM_CDF4(3694, 11677, 17556)}, + { AOM_CDF4(30060, 32581, 32720)}, { AOM_CDF4(21011, 30775, 32120)}, + { AOM_CDF4(11931, 24820, 29289)}, { AOM_CDF4(7119, 17662, 24356)}, + { AOM_CDF4(3833, 10706, 16304)}, { AOM_CDF4(31954, 32731, 32748)}, + { AOM_CDF4(23913, 31724, 32489)}, { AOM_CDF4(15520, 28060, 31286)}, + { AOM_CDF4(11517, 23008, 28571)}, { AOM_CDF4(6193, 14508, 20629)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(1035, 2807, 4156)}, { AOM_CDF4(13162, 18138, 20939)}, + { AOM_CDF4(2696, 6633, 8755)}, { AOM_CDF4(1373, 4161, 6853)}, + { AOM_CDF4(1099, 2746, 4716)}, { AOM_CDF4(340, 1021, 1599)}, + { AOM_CDF4(22826, 30419, 32135)}, { AOM_CDF4(10395, 21762, 26942)}, + { AOM_CDF4(4726, 12407, 17361)}, { AOM_CDF4(2447, 7080, 10593)}, + { AOM_CDF4(1227, 3717, 6011)}, { AOM_CDF4(28156, 31424, 31934)}, + { AOM_CDF4(16915, 27754, 30373)}, { AOM_CDF4(9148, 20990, 26431)}, + { AOM_CDF4(5950, 15515, 21148)}, { AOM_CDF4(2492, 7327, 11526)}, + { AOM_CDF4(30602, 32477, 32670)}, { AOM_CDF4(20026, 29955, 31568)}, + { AOM_CDF4(11220, 23628, 28105)}, { AOM_CDF4(6652, 17019, 22973)}, + { AOM_CDF4(3064, 8536, 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24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + } + }, + { + { + { + { AOM_CDF4(8896, 16227, 20630)}, { AOM_CDF4(23629, 31782, 32527)}, + { AOM_CDF4(15173, 27755, 31321)}, { AOM_CDF4(10158, 21233, 27382)}, + { AOM_CDF4(6420, 14857, 21558)}, { AOM_CDF4(3269, 8155, 12646)}, + { AOM_CDF4(24835, 32009, 32496)}, { AOM_CDF4(16509, 28421, 31579)}, + { AOM_CDF4(10957, 21514, 27418)}, { AOM_CDF4(7881, 15930, 22096)}, + { AOM_CDF4(5388, 10960, 15918)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(20745, 30773, 32093)}, + { AOM_CDF4(15200, 27221, 30861)}, { AOM_CDF4(13032, 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AOM_CDF4(5674, 14657, 21674)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(25742, 32319, 32671)}, + { AOM_CDF4(19557, 31164, 32454)}, { AOM_CDF4(13381, 26381, 30755)}, + { AOM_CDF4(10101, 21466, 26722)}, { AOM_CDF4(9209, 19650, 26825)}, + { AOM_CDF4(27107, 31917, 32432)}, { AOM_CDF4(18056, 28893, 31203)}, + { AOM_CDF4(10200, 21434, 26764)}, { AOM_CDF4(4660, 12913, 19502)}, + { AOM_CDF4(2368, 6930, 12504)}, { AOM_CDF4(26960, 32158, 32613)}, + { AOM_CDF4(18628, 30005, 32031)}, { AOM_CDF4(10233, 22442, 28232)}, + { AOM_CDF4(5471, 14630, 21516)}, { AOM_CDF4(3235, 10767, 17109)}, + { AOM_CDF4(27696, 32440, 32692)}, { AOM_CDF4(20032, 31167, 32438)}, + { AOM_CDF4(8700, 21341, 28442)}, { AOM_CDF4(5662, 14831, 21795)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(9704, 17294, 21132)}, { AOM_CDF4(26762, 32278, 32633)}, + { AOM_CDF4(18382, 29620, 31819)}, { AOM_CDF4(10891, 23475, 28723)}, + { AOM_CDF4(6358, 16583, 23309)}, { AOM_CDF4(3248, 9118, 14141)}, + { AOM_CDF4(27204, 32573, 32699)}, { AOM_CDF4(19818, 30824, 32329)}, + { AOM_CDF4(11772, 25120, 30041)}, { AOM_CDF4(6995, 18033, 25039)}, + { AOM_CDF4(3752, 10442, 16098)}, { AOM_CDF4(27222, 32256, 32559)}, + { AOM_CDF4(15356, 28399, 31475)}, { AOM_CDF4(8821, 20635, 27057)}, + { AOM_CDF4(5511, 14404, 21239)}, { AOM_CDF4(2935, 8222, 13051)}, + { AOM_CDF4(24875, 32120, 32529)}, { AOM_CDF4(15233, 28265, 31445)}, + { AOM_CDF4(8605, 20570, 26932)}, { AOM_CDF4(5431, 14413, 21196)}, + { AOM_CDF4(2994, 8341, 13223)}, { AOM_CDF4(28201, 32604, 32700)}, + { AOM_CDF4(21041, 31446, 32456)}, { AOM_CDF4(13221, 26213, 30475)}, + { AOM_CDF4(8255, 19385, 26037)}, { AOM_CDF4(4930, 12585, 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{ AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(9800, 17635, 21073)}, { AOM_CDF4(26153, 31885, 32527)}, + { AOM_CDF4(15038, 27852, 31006)}, { AOM_CDF4(8718, 20564, 26486)}, + { AOM_CDF4(5128, 14076, 20514)}, { AOM_CDF4(2636, 7566, 11925)}, + { AOM_CDF4(27551, 32504, 32701)}, { AOM_CDF4(18310, 30054, 32100)}, + { AOM_CDF4(10211, 23420, 29082)}, { AOM_CDF4(6222, 16876, 23916)}, + { AOM_CDF4(3462, 9954, 15498)}, { AOM_CDF4(29991, 32633, 32721)}, + { AOM_CDF4(19883, 30751, 32201)}, { AOM_CDF4(11141, 24184, 29285)}, + { AOM_CDF4(6420, 16940, 23774)}, { AOM_CDF4(3392, 9753, 15118)}, + { AOM_CDF4(28465, 32616, 32712)}, { AOM_CDF4(19850, 30702, 32244)}, + { AOM_CDF4(10983, 24024, 29223)}, { AOM_CDF4(6294, 16770, 23582)}, + { AOM_CDF4(3244, 9283, 14509)}, { AOM_CDF4(30023, 32717, 32748)}, + { AOM_CDF4(22940, 32032, 32626)}, { AOM_CDF4(14282, 27928, 31473)}, + { AOM_CDF4(8562, 21327, 27914)}, { AOM_CDF4(4846, 13393, 19919)}, + { AOM_CDF4(29981, 32590, 32695)}, { AOM_CDF4(20465, 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AOM_CDF4(6243, 16236, 22407)}, { AOM_CDF4(3976, 10389, 16017)}, + { AOM_CDF4(28377, 32561, 32738)}, { AOM_CDF4(19366, 31175, 32482)}, + { AOM_CDF4(13327, 27175, 31094)}, { AOM_CDF4(8258, 20769, 27143)}, + { AOM_CDF4(4703, 13198, 19527)}, { AOM_CDF4(31086, 32706, 32748)}, + { AOM_CDF4(22853, 31902, 32583)}, { AOM_CDF4(14759, 28186, 31419)}, + { AOM_CDF4(9284, 22382, 28348)}, { AOM_CDF4(5585, 15192, 21868)}, + { AOM_CDF4(28291, 32652, 32746)}, { AOM_CDF4(19849, 32107, 32571)}, + { AOM_CDF4(14834, 26818, 29214)}, { AOM_CDF4(10306, 22594, 28672)}, + { AOM_CDF4(6615, 17384, 23384)}, { AOM_CDF4(28947, 32604, 32745)}, + { AOM_CDF4(25625, 32289, 32646)}, { AOM_CDF4(18758, 28672, 31403)}, + { AOM_CDF4(10017, 23430, 28523)}, { AOM_CDF4(6862, 15269, 22131)}, + { AOM_CDF4(23933, 32509, 32739)}, { AOM_CDF4(19927, 31495, 32631)}, + { AOM_CDF4(11903, 26023, 30621)}, { AOM_CDF4(7026, 20094, 27252)}, + { AOM_CDF4(5998, 18106, 24437)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(4456, 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24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(10202, 20633, 25484)}, { AOM_CDF4(27336, 31445, 32352)}, + { AOM_CDF4(12420, 24384, 28552)}, { AOM_CDF4(7648, 18115, 23856)}, + { AOM_CDF4(5662, 14341, 19902)}, { AOM_CDF4(3611, 10328, 15390)}, + { AOM_CDF4(30945, 32616, 32736)}, { AOM_CDF4(18682, 30505, 32253)}, + { AOM_CDF4(11513, 25336, 30203)}, { AOM_CDF4(7449, 19452, 26148)}, + { AOM_CDF4(4482, 13051, 18886)}, { AOM_CDF4(32022, 32690, 32747)}, + { AOM_CDF4(18578, 30501, 32146)}, { AOM_CDF4(11249, 23368, 28631)}, + { AOM_CDF4(5645, 16958, 22158)}, { AOM_CDF4(5009, 11444, 16637)}, + { AOM_CDF4(31357, 32710, 32748)}, { AOM_CDF4(21552, 31494, 32504)}, + { AOM_CDF4(13891, 27677, 31340)}, { AOM_CDF4(9051, 22098, 28172)}, + { AOM_CDF4(5190, 13377, 19486)}, { AOM_CDF4(32364, 32740, 32748)}, + { AOM_CDF4(24839, 31907, 32551)}, { AOM_CDF4(17160, 28779, 31696)}, + { AOM_CDF4(12452, 24137, 29602)}, { AOM_CDF4(6165, 15389, 22477)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(2575, 7281, 11077)}, { AOM_CDF4(14002, 20866, 25402)}, + { AOM_CDF4(6343, 15056, 19658)}, { AOM_CDF4(4474, 11858, 17041)}, + { AOM_CDF4(2865, 8299, 12534)}, { AOM_CDF4(1344, 3949, 6391)}, + { AOM_CDF4(24720, 31239, 32459)}, { AOM_CDF4(12585, 25356, 29968)}, + { AOM_CDF4(7181, 18246, 24444)}, { AOM_CDF4(5025, 13667, 19885)}, + { AOM_CDF4(2521, 7304, 11605)}, { AOM_CDF4(29908, 32252, 32584)}, + { AOM_CDF4(17421, 29156, 31575)}, { AOM_CDF4(9889, 22188, 27782)}, + { AOM_CDF4(5878, 15647, 22123)}, { AOM_CDF4(2814, 8665, 13323)}, + { AOM_CDF4(30183, 32568, 32713)}, { AOM_CDF4(18528, 30195, 32049)}, + { AOM_CDF4(10982, 24606, 29657)}, { AOM_CDF4(6957, 18165, 25231)}, + { AOM_CDF4(3508, 10118, 15468)}, { AOM_CDF4(31761, 32736, 32748)}, + { AOM_CDF4(21041, 31328, 32546)}, { AOM_CDF4(12568, 26732, 31166)}, + { AOM_CDF4(8052, 20720, 27733)}, { AOM_CDF4(4336, 12192, 18396)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + } + }, + { + { + { + { AOM_CDF4(7062, 16472, 22319)}, { AOM_CDF4(24538, 32261, 32674)}, + { AOM_CDF4(13675, 28041, 31779)}, { AOM_CDF4(8590, 20674, 27631)}, + { AOM_CDF4(5685, 14675, 22013)}, { AOM_CDF4(3655, 9898, 15731)}, + { AOM_CDF4(26493, 32418, 32658)}, { AOM_CDF4(16376, 29342, 32090)}, + { AOM_CDF4(10594, 22649, 28970)}, { AOM_CDF4(8176, 17170, 24303)}, + { AOM_CDF4(5605, 12694, 19139)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(23888, 31902, 32542)}, + { AOM_CDF4(18612, 29687, 31987)}, { AOM_CDF4(16245, 24852, 29249)}, + { AOM_CDF4(15765, 22608, 27559)}, { AOM_CDF4(19895, 24699, 27510)}, + { AOM_CDF4(28401, 32212, 32457)}, { AOM_CDF4(15274, 27825, 30980)}, + { AOM_CDF4(9364, 18128, 24332)}, { AOM_CDF4(2283, 8193, 15082)}, + { AOM_CDF4(1228, 3972, 7881)}, { AOM_CDF4(29455, 32469, 32620)}, + { AOM_CDF4(17981, 28245, 31388)}, { AOM_CDF4(10921, 20098, 26240)}, + { AOM_CDF4(3743, 11829, 18657)}, { AOM_CDF4(2374, 9593, 15715)}, + { AOM_CDF4(31068, 32466, 32635)}, { AOM_CDF4(20321, 29572, 31971)}, + { AOM_CDF4(10771, 20255, 27119)}, { AOM_CDF4(2795, 10410, 17361)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(9320, 22102, 27840)}, { AOM_CDF4(27057, 32464, 32724)}, + { AOM_CDF4(16331, 30268, 32309)}, { AOM_CDF4(10319, 23935, 29720)}, + { AOM_CDF4(6189, 16448, 24106)}, { AOM_CDF4(3589, 10884, 18808)}, + { AOM_CDF4(29026, 32624, 32748)}, { AOM_CDF4(19226, 31507, 32587)}, + { AOM_CDF4(12692, 26921, 31203)}, { AOM_CDF4(7049, 19532, 27635)}, + { AOM_CDF4(7727, 15669, 23252)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(28056, 32625, 32748)}, + { AOM_CDF4(22383, 32075, 32669)}, { AOM_CDF4(15417, 27098, 31749)}, + { AOM_CDF4(18127, 26493, 27190)}, { AOM_CDF4(5461, 16384, 21845)}, + { AOM_CDF4(27982, 32091, 32584)}, { AOM_CDF4(19045, 29868, 31972)}, + { AOM_CDF4(10397, 22266, 27932)}, { AOM_CDF4(5990, 13697, 21500)}, + { AOM_CDF4(1792, 6912, 15104)}, { AOM_CDF4(28198, 32501, 32718)}, + { AOM_CDF4(21534, 31521, 32569)}, { AOM_CDF4(11109, 25217, 30017)}, + { AOM_CDF4(5671, 15124, 26151)}, { AOM_CDF4(4681, 14043, 18725)}, + { AOM_CDF4(28688, 32580, 32741)}, { AOM_CDF4(22576, 32079, 32661)}, + { AOM_CDF4(10627, 22141, 28340)}, { AOM_CDF4(9362, 14043, 28087)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(7754, 16948, 22142)}, { AOM_CDF4(25670, 32330, 32691)}, + { AOM_CDF4(15663, 29225, 31994)}, { AOM_CDF4(9878, 23288, 29158)}, + { AOM_CDF4(6419, 17088, 24336)}, { AOM_CDF4(3859, 11003, 17039)}, + { AOM_CDF4(27562, 32595, 32725)}, { AOM_CDF4(17575, 30588, 32399)}, + { AOM_CDF4(10819, 24838, 30309)}, { AOM_CDF4(7124, 18686, 25916)}, + { AOM_CDF4(4479, 12688, 19340)}, { AOM_CDF4(28385, 32476, 32673)}, + { AOM_CDF4(15306, 29005, 31938)}, { AOM_CDF4(8937, 21615, 28322)}, + { AOM_CDF4(5982, 15603, 22786)}, { AOM_CDF4(3620, 10267, 16136)}, + { AOM_CDF4(27280, 32464, 32667)}, { AOM_CDF4(15607, 29160, 32004)}, + { AOM_CDF4(9091, 22135, 28740)}, { AOM_CDF4(6232, 16632, 24020)}, + { AOM_CDF4(4047, 11377, 17672)}, { AOM_CDF4(29220, 32630, 32718)}, + { AOM_CDF4(19650, 31220, 32462)}, { AOM_CDF4(13050, 26312, 30827)}, + { AOM_CDF4(9228, 20870, 27468)}, { AOM_CDF4(6146, 15149, 21971)}, + { AOM_CDF4(30169, 32481, 32623)}, { AOM_CDF4(17212, 29311, 31554)}, + { AOM_CDF4(9911, 21311, 26882)}, { AOM_CDF4(4487, 13314, 20372)}, + { AOM_CDF4(2570, 7772, 12889)}, { AOM_CDF4(30924, 32613, 32708)}, + { AOM_CDF4(19490, 30206, 32107)}, { AOM_CDF4(11232, 23998, 29276)}, + { AOM_CDF4(6769, 17955, 25035)}, { AOM_CDF4(4398, 12623, 19214)}, + { AOM_CDF4(30609, 32627, 32722)}, { AOM_CDF4(19370, 30582, 32287)}, + { AOM_CDF4(10457, 23619, 29409)}, { AOM_CDF4(6443, 17637, 24834)}, + { AOM_CDF4(4645, 13236, 20106)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(8626, 20271, 26216)}, { AOM_CDF4(26707, 32406, 32711)}, + { AOM_CDF4(16999, 30329, 32286)}, { AOM_CDF4(11445, 25123, 30286)}, + { AOM_CDF4(6411, 18828, 25601)}, { AOM_CDF4(6801, 12458, 20248)}, + { AOM_CDF4(29918, 32682, 32748)}, { AOM_CDF4(20649, 31739, 32618)}, + { AOM_CDF4(12879, 27773, 31581)}, { AOM_CDF4(7896, 21751, 28244)}, + { AOM_CDF4(5260, 14870, 23698)}, { AOM_CDF4(29252, 32593, 32731)}, + { AOM_CDF4(17072, 30460, 32294)}, { AOM_CDF4(10653, 24143, 29365)}, + { AOM_CDF4(6536, 17490, 23983)}, { AOM_CDF4(4929, 13170, 20085)}, + { AOM_CDF4(28137, 32518, 32715)}, { AOM_CDF4(18171, 30784, 32407)}, + { AOM_CDF4(11437, 25436, 30459)}, { AOM_CDF4(7252, 18534, 26176)}, + { AOM_CDF4(4126, 13353, 20978)}, { AOM_CDF4(31162, 32726, 32748)}, + { AOM_CDF4(23017, 32222, 32701)}, { AOM_CDF4(15629, 29233, 32046)}, + { AOM_CDF4(9387, 22621, 29480)}, { AOM_CDF4(6922, 17616, 25010)}, + { AOM_CDF4(28838, 32265, 32614)}, { AOM_CDF4(19701, 30206, 31920)}, + { AOM_CDF4(11214, 22410, 27933)}, { AOM_CDF4(5320, 14177, 23034)}, + { AOM_CDF4(5049, 12881, 17827)}, { AOM_CDF4(27484, 32471, 32734)}, + { AOM_CDF4(21076, 31526, 32561)}, { AOM_CDF4(12707, 26303, 31211)}, + { AOM_CDF4(8169, 21722, 28219)}, { AOM_CDF4(6045, 19406, 27042)}, + { AOM_CDF4(27753, 32572, 32745)}, { AOM_CDF4(20832, 31878, 32653)}, + { AOM_CDF4(13250, 27356, 31674)}, { AOM_CDF4(7718, 21508, 29858)}, + { AOM_CDF4(7209, 18350, 25559)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(7876, 16901, 21741)}, { AOM_CDF4(24001, 31898, 32625)}, + { AOM_CDF4(14529, 27959, 31451)}, { AOM_CDF4(8273, 20818, 27258)}, + { AOM_CDF4(5278, 14673, 21510)}, { AOM_CDF4(2983, 8843, 14039)}, + { AOM_CDF4(28016, 32574, 32732)}, { AOM_CDF4(17471, 30306, 32301)}, + { AOM_CDF4(10224, 24063, 29728)}, { AOM_CDF4(6602, 17954, 25052)}, + { AOM_CDF4(4002, 11585, 17759)}, { AOM_CDF4(30190, 32634, 32739)}, + { AOM_CDF4(17497, 30282, 32270)}, { AOM_CDF4(10229, 23729, 29538)}, + { AOM_CDF4(6344, 17211, 24440)}, { AOM_CDF4(3849, 11189, 17108)}, + { AOM_CDF4(28570, 32583, 32726)}, { AOM_CDF4(17521, 30161, 32238)}, + { AOM_CDF4(10153, 23565, 29378)}, { AOM_CDF4(6455, 17341, 24443)}, + { AOM_CDF4(3907, 11042, 17024)}, { AOM_CDF4(30689, 32715, 32748)}, + { AOM_CDF4(21546, 31840, 32610)}, { AOM_CDF4(13547, 27581, 31459)}, + { AOM_CDF4(8912, 21757, 28309)}, { AOM_CDF4(5548, 15080, 22046)}, + { AOM_CDF4(30783, 32540, 32685)}, { AOM_CDF4(17540, 29528, 31668)}, + { AOM_CDF4(10160, 21468, 26783)}, { AOM_CDF4(4724, 13393, 20054)}, + { AOM_CDF4(2702, 8174, 13102)}, { AOM_CDF4(31648, 32686, 32742)}, + { AOM_CDF4(20954, 31094, 32337)}, { AOM_CDF4(12420, 25698, 30179)}, + { AOM_CDF4(7304, 19320, 26248)}, { AOM_CDF4(4366, 12261, 18864)}, + { AOM_CDF4(31581, 32723, 32748)}, { AOM_CDF4(21373, 31586, 32525)}, + { AOM_CDF4(12744, 26625, 30885)}, { AOM_CDF4(7431, 20322, 26950)}, + { AOM_CDF4(4692, 13323, 20111)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(7833, 18369, 24095)}, { AOM_CDF4(26650, 32273, 32702)}, + { AOM_CDF4(16371, 29961, 32191)}, { AOM_CDF4(11055, 24082, 29629)}, + { AOM_CDF4(6892, 18644, 25400)}, { AOM_CDF4(5006, 13057, 19240)}, + { AOM_CDF4(29834, 32666, 32748)}, { AOM_CDF4(19577, 31335, 32570)}, + { AOM_CDF4(12253, 26509, 31122)}, { AOM_CDF4(7991, 20772, 27711)}, + { AOM_CDF4(5677, 15910, 23059)}, { AOM_CDF4(30109, 32532, 32720)}, + { AOM_CDF4(16747, 30166, 32252)}, { AOM_CDF4(10134, 23542, 29184)}, + { AOM_CDF4(5791, 16176, 23556)}, { AOM_CDF4(4362, 10414, 17284)}, + { AOM_CDF4(29492, 32626, 32748)}, { AOM_CDF4(19894, 31402, 32525)}, + { AOM_CDF4(12942, 27071, 30869)}, { AOM_CDF4(8346, 21216, 27405)}, + { AOM_CDF4(6572, 17087, 23859)}, { AOM_CDF4(32035, 32735, 32748)}, + { AOM_CDF4(22957, 31838, 32618)}, { AOM_CDF4(14724, 28572, 31772)}, + { AOM_CDF4(10364, 23999, 29553)}, { AOM_CDF4(7004, 18433, 25655)}, + { AOM_CDF4(27528, 32277, 32681)}, { AOM_CDF4(16959, 31171, 32096)}, + { AOM_CDF4(10486, 23593, 27962)}, { AOM_CDF4(8192, 16384, 23211)}, + { AOM_CDF4(8937, 17873, 20852)}, { AOM_CDF4(27715, 32002, 32615)}, + { AOM_CDF4(15073, 29491, 31676)}, { AOM_CDF4(11264, 24576, 28672)}, + { AOM_CDF4(2341, 18725, 23406)}, { AOM_CDF4(7282, 18204, 25486)}, + { AOM_CDF4(28547, 32213, 32657)}, { AOM_CDF4(20788, 29773, 32239)}, + { AOM_CDF4(6780, 21469, 30508)}, { AOM_CDF4(5958, 14895, 23831)}, + { AOM_CDF4(16384, 21845, 27307)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(5992, 14304, 19765)}, { AOM_CDF4(22612, 31238, 32456)}, + { AOM_CDF4(13456, 27162, 31087)}, { AOM_CDF4(8001, 20062, 26504)}, + { AOM_CDF4(5168, 14105, 20764)}, { AOM_CDF4(2632, 7771, 12385)}, + { AOM_CDF4(27034, 32344, 32709)}, { AOM_CDF4(15850, 29415, 31997)}, + { AOM_CDF4(9494, 22776, 28841)}, { AOM_CDF4(6151, 16830, 23969)}, + { AOM_CDF4(3461, 10039, 15722)}, { AOM_CDF4(30134, 32569, 32731)}, + { AOM_CDF4(15638, 29422, 31945)}, { AOM_CDF4(9150, 21865, 28218)}, + { AOM_CDF4(5647, 15719, 22676)}, { AOM_CDF4(3402, 9772, 15477)}, + { AOM_CDF4(28530, 32586, 32735)}, { AOM_CDF4(17139, 30298, 32292)}, + { AOM_CDF4(10200, 24039, 29685)}, { AOM_CDF4(6419, 17674, 24786)}, + { AOM_CDF4(3544, 10225, 15824)}, { AOM_CDF4(31333, 32726, 32748)}, + { AOM_CDF4(20618, 31487, 32544)}, { AOM_CDF4(12901, 27217, 31232)}, + { AOM_CDF4(8624, 21734, 28171)}, { AOM_CDF4(5104, 14191, 20748)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(11206, 21090, 26561)}, { AOM_CDF4(28759, 32279, 32671)}, + { AOM_CDF4(14171, 27952, 31569)}, { AOM_CDF4(9743, 22907, 29141)}, + { AOM_CDF4(6871, 17886, 24868)}, { AOM_CDF4(4960, 13152, 19315)}, + { AOM_CDF4(31077, 32661, 32748)}, { AOM_CDF4(19400, 31195, 32515)}, + { AOM_CDF4(12752, 26858, 31040)}, { AOM_CDF4(8370, 22098, 28591)}, + { AOM_CDF4(5457, 15373, 22298)}, { AOM_CDF4(31697, 32706, 32748)}, + { AOM_CDF4(17860, 30657, 32333)}, { AOM_CDF4(12510, 24812, 29261)}, + { AOM_CDF4(6180, 19124, 24722)}, { AOM_CDF4(5041, 13548, 17959)}, + { AOM_CDF4(31552, 32716, 32748)}, { AOM_CDF4(21908, 31769, 32623)}, + { AOM_CDF4(14470, 28201, 31565)}, { AOM_CDF4(9493, 22982, 28608)}, + { AOM_CDF4(6858, 17240, 24137)}, { AOM_CDF4(32543, 32752, 32756)}, + { AOM_CDF4(24286, 32097, 32666)}, { AOM_CDF4(15958, 29217, 32024)}, + { AOM_CDF4(10207, 24234, 29958)}, { AOM_CDF4(6929, 18305, 25652)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + }, + { + { + { AOM_CDF4(4137, 10847, 15682)}, { AOM_CDF4(17824, 27001, 30058)}, + { AOM_CDF4(10204, 22796, 28291)}, { AOM_CDF4(6076, 15935, 22125)}, + { AOM_CDF4(3852, 10937, 16816)}, { AOM_CDF4(2252, 6324, 10131)}, + { AOM_CDF4(25840, 32016, 32662)}, { AOM_CDF4(15109, 28268, 31531)}, + { AOM_CDF4(9385, 22231, 28340)}, { AOM_CDF4(6082, 16672, 23479)}, + { AOM_CDF4(3318, 9427, 14681)}, { AOM_CDF4(30594, 32574, 32718)}, + { AOM_CDF4(16836, 29552, 31859)}, { AOM_CDF4(9556, 22542, 28356)}, + { AOM_CDF4(6305, 16725, 23540)}, { AOM_CDF4(3376, 9895, 15184)}, + { AOM_CDF4(29383, 32617, 32745)}, { AOM_CDF4(18891, 30809, 32401)}, + { AOM_CDF4(11688, 25942, 30687)}, { AOM_CDF4(7468, 19469, 26651)}, + { AOM_CDF4(3909, 11358, 17012)}, { AOM_CDF4(31564, 32736, 32748)}, + { AOM_CDF4(20906, 31611, 32600)}, { AOM_CDF4(13191, 27621, 31537)}, + { AOM_CDF4(8768, 22029, 28676)}, { AOM_CDF4(5079, 14109, 20906)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + }, + { + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)}, + { AOM_CDF4(8192, 16384, 24576)}, { AOM_CDF4(8192, 16384, 24576)} + } + } + } +}; + +static const u16 av1_default_coeff_base_eob_multi_cdfs[TOKEN_CDF_Q_CTXS][TX_SIZES] + [PLANE_TYPES][SIG_COEF_CONTEXTS_EOB][CDF_SIZE(NUM_BASE_LEVELS + 1)] = { + { + { + { + { AOM_CDF3(17837, 29055)}, + { AOM_CDF3(29600, 31446)}, + { AOM_CDF3(30844, 31878)}, + { AOM_CDF3(24926, 28948)} + }, + { + { AOM_CDF3(21365, 30026)}, + { AOM_CDF3(30512, 32423)}, + { AOM_CDF3(31658, 32621)}, + { AOM_CDF3(29630, 31881)} + } + }, + { + { + { AOM_CDF3(5717, 26477)}, + { AOM_CDF3(30491, 31703)}, + { AOM_CDF3(31550, 32158)}, + { AOM_CDF3(29648, 31491)} + }, + { + { AOM_CDF3(12608, 27820)}, + { AOM_CDF3(30680, 32225)}, + { AOM_CDF3(30809, 32335)}, + { AOM_CDF3(31299, 32423)} + } + }, + { + { + { AOM_CDF3(1786, 12612)}, + { AOM_CDF3(30663, 31625)}, + { AOM_CDF3(32339, 32468)}, + { AOM_CDF3(31148, 31833)} + }, + { + { AOM_CDF3(18857, 23865)}, + { AOM_CDF3(31428, 32428)}, + { AOM_CDF3(31744, 32373)}, + { AOM_CDF3(31775, 32526)} + } + }, + { + { + { AOM_CDF3(1787, 2532)}, + { AOM_CDF3(30832, 31662)}, + { AOM_CDF3(31824, 32682)}, + { AOM_CDF3(32133, 32569)} + }, + { + { AOM_CDF3(13751, 22235)}, + { AOM_CDF3(32089, 32409)}, + { AOM_CDF3(27084, 27920)}, + { AOM_CDF3(29291, 32594)} + } + }, + { + { + { AOM_CDF3(1725, 3449)}, + { AOM_CDF3(31102, 31935)}, + { AOM_CDF3(32457, 32613)}, + { AOM_CDF3(32412, 32649)} + }, + { + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)} + } + } + }, + { + { + { + { AOM_CDF3(17560, 29888)}, + { AOM_CDF3(29671, 31549)}, + { AOM_CDF3(31007, 32056)}, + { AOM_CDF3(27286, 30006)} + }, + { + { AOM_CDF3(26594, 31212)}, + { AOM_CDF3(31208, 32582)}, + { AOM_CDF3(31835, 32637)}, + { AOM_CDF3(30595, 32206)} + } + }, + { + { + { AOM_CDF3(15239, 29932)}, + { AOM_CDF3(31315, 32095)}, + { AOM_CDF3(32130, 32434)}, + { AOM_CDF3(30864, 31996)} + }, + { + { AOM_CDF3(26279, 30968)}, + { AOM_CDF3(31142, 32495)}, + { AOM_CDF3(31713, 32540)}, + { AOM_CDF3(31929, 32594)} + } + }, + { + { + { AOM_CDF3(2644, 25198)}, + { AOM_CDF3(32038, 32451)}, + { AOM_CDF3(32639, 32695)}, + { AOM_CDF3(32166, 32518)} + }, + { + { AOM_CDF3(17187, 27668)}, + { AOM_CDF3(31714, 32550)}, + { AOM_CDF3(32283, 32678)}, + { AOM_CDF3(31930, 32563)} + } + }, + { + { + { AOM_CDF3(1044, 2257)}, + { AOM_CDF3(30755, 31923)}, + { AOM_CDF3(32208, 32693)}, + { AOM_CDF3(32244, 32615)} + }, + { + { AOM_CDF3(21317, 26207)}, + { AOM_CDF3(29133, 30868)}, + { AOM_CDF3(29311, 31231)}, + { AOM_CDF3(29657, 31087)} + } + }, + { + { + { AOM_CDF3(478, 1834)}, + { AOM_CDF3(31005, 31987)}, + { AOM_CDF3(32317, 32724)}, + { AOM_CDF3(30865, 32648)} + }, + { + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)} + } + } + }, + { + { + { + { AOM_CDF3(20092, 30774)}, + { AOM_CDF3(30695, 32020)}, + { AOM_CDF3(31131, 32103)}, + { AOM_CDF3(28666, 30870)} + }, + { + { AOM_CDF3(27258, 31095)}, + { AOM_CDF3(31804, 32623)}, + { AOM_CDF3(31763, 32528)}, + { AOM_CDF3(31438, 32506)} + } + }, + { + { + { AOM_CDF3(18049, 30489)}, + { AOM_CDF3(31706, 32286)}, + { AOM_CDF3(32163, 32473)}, + { AOM_CDF3(31550, 32184)} + }, + { + { AOM_CDF3(27116, 30842)}, + { AOM_CDF3(31971, 32598)}, + { AOM_CDF3(32088, 32576)}, + { AOM_CDF3(32067, 32664)} + } + }, + { + { + { AOM_CDF3(12854, 29093)}, + { AOM_CDF3(32272, 32558)}, + { AOM_CDF3(32667, 32729)}, + { AOM_CDF3(32306, 32585)} + }, + { + { AOM_CDF3(25476, 30366)}, + { AOM_CDF3(32169, 32687)}, + { AOM_CDF3(32479, 32689)}, + { AOM_CDF3(31673, 32634)} + } + }, + { + { + { AOM_CDF3(2809, 19301)}, + { AOM_CDF3(32205, 32622)}, + { AOM_CDF3(32338, 32730)}, + { AOM_CDF3(31786, 32616)} + }, + { + { AOM_CDF3(22737, 29105)}, + { AOM_CDF3(30810, 32362)}, + { AOM_CDF3(30014, 32627)}, + { AOM_CDF3(30528, 32574)} + } + }, + { + { + { AOM_CDF3(935, 3382)}, + { AOM_CDF3(30789, 31909)}, + { AOM_CDF3(32466, 32756)}, + { AOM_CDF3(30860, 32513)} + }, + { + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)} + } + } + }, + { + { + { + { AOM_CDF3(22497, 31198)}, + { AOM_CDF3(31715, 32495)}, + { AOM_CDF3(31606, 32337)}, + { AOM_CDF3(30388, 31990)} + }, + { + { AOM_CDF3(27877, 31584)}, + { AOM_CDF3(32170, 32728)}, + { AOM_CDF3(32155, 32688)}, + { AOM_CDF3(32219, 32702)} + } + }, + { + { + { AOM_CDF3(21457, 31043)}, + { AOM_CDF3(31951, 32483)}, + { AOM_CDF3(32153, 32562)}, + { AOM_CDF3(31473, 32215)} + }, + { + { AOM_CDF3(27558, 31151)}, + { AOM_CDF3(32020, 32640)}, + { AOM_CDF3(32097, 32575)}, + { AOM_CDF3(32242, 32719)} + } + }, + { + { + { AOM_CDF3(19980, 30591)}, + { AOM_CDF3(32219, 32597)}, + { AOM_CDF3(32581, 32706)}, + { AOM_CDF3(31803, 32287)} + }, + { + { AOM_CDF3(26473, 30507)}, + { AOM_CDF3(32431, 32723)}, + { AOM_CDF3(32196, 32611)}, + { AOM_CDF3(31588, 32528)} + } + }, + { + { + { AOM_CDF3(24647, 30463)}, + { AOM_CDF3(32412, 32695)}, + { AOM_CDF3(32468, 32720)}, + { AOM_CDF3(31269, 32523)} + }, + { + { AOM_CDF3(28482, 31505)}, + { AOM_CDF3(32152, 32701)}, + { AOM_CDF3(31732, 32598)}, + { AOM_CDF3(31767, 32712)} + } + }, + { + { + { AOM_CDF3(12358, 24977)}, + { AOM_CDF3(31331, 32385)}, + { AOM_CDF3(32634, 32756)}, + { AOM_CDF3(30411, 32548)} + }, + { + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)}, + { AOM_CDF3(10923, 21845)} + } + } + } +}; + +static const u16 default_joint_cdf[] = { ICDF(4096), ICDF(11264), ICDF(19328)}; +static const u16 default_clsss_cdf[][10] = { + // Vertical component + { + ICDF(28672), ICDF(30976), ICDF(31858), ICDF(32320), ICDF(32551), + ICDF(32656), ICDF(32740), ICDF(32757), ICDF(32762), ICDF(32767) + }, + // Horizontal component + { + ICDF(28672), ICDF(30976), ICDF(31858), ICDF(32320), ICDF(32551), + ICDF(32656), ICDF(32740), ICDF(32757), ICDF(32762), ICDF(32767) + } +}; + +static const u16 default_clsss0_fp_cdf[][2][3] = { + // Vertical component + { + { ICDF(16384), ICDF(24576), ICDF(26624)}, + { ICDF(12288), ICDF(21248), ICDF(24128)} + }, + // Horizontal component + { + { ICDF(16384), ICDF(24576), ICDF(26624)}, + { ICDF(12288), ICDF(21248), ICDF(24128)} + } +}; + +static const u16 default_fp_cdf[][3] = { + // Vertical component + { + ICDF(8192), ICDF(17408), ICDF(21248) + }, + // Horizontal component + { + ICDF(8192), ICDF(17408), ICDF(21248) + } +}; + +static const u16 default_sign_cdf[] = { ICDF(128 * 128), ICDF(128 * 128)}; +static const u16 default_class0_hp_cdf[] = { ICDF(160 * 128), ICDF(160 * 128)}; +static const u16 default_hp_cdf[] = { ICDF(128 * 128), ICDF(128 * 128)}; +static const u16 default_class0_cdf[] = { ICDF(216 * 128), ICDF(216 * 128)}; +static const u16 default_bits_cdf[][10] = { + { + ICDF(128 * 136), ICDF(128 * 140), ICDF(128 * 148), ICDF(128 * 160), + ICDF(128 * 176), ICDF(128 * 192), ICDF(128 * 224), ICDF(128 * 234), + ICDF(128 * 234), ICDF(128 * 240) + }, + { + ICDF(128 * 136), ICDF(128 * 140), ICDF(128 * 148), ICDF(128 * 160), + ICDF(128 * 176), ICDF(128 * 192), ICDF(128 * 224), ICDF(128 * 234), + ICDF(128 * 234), ICDF(128 * 240) + } +}; + +static int rockchip_av1_get_q_ctx(int q) +{ + if (q <= 20) + return 0; + if (q <= 60) + return 1; + if (q <= 120) + return 2; + return 3; +} + +void rockchip_av1_default_coeff_probs(u32 base_qindex, void *ptr) +{ + struct av1cdfs *cdfs = (struct av1cdfs *)ptr; + const int index = rockchip_av1_get_q_ctx(base_qindex); + + memcpy(cdfs->txb_skip_cdf, av1_default_txb_skip_cdfs[index], + sizeof(av1_default_txb_skip_cdfs[0])); + memcpy(cdfs->eob_extra_cdf, av1_default_eob_extra_cdfs[index], + sizeof(av1_default_eob_extra_cdfs[0])); + memcpy(cdfs->dc_sign_cdf, av1_default_dc_sign_cdfs[index], + sizeof(av1_default_dc_sign_cdfs[0])); + memcpy(cdfs->coeff_br_cdf, av1_default_coeff_lps_multi_cdfs[index], + sizeof(av1_default_coeff_lps_multi_cdfs[0])); + memcpy(cdfs->coeff_base_cdf, av1_default_coeff_base_multi_cdfs[index], + sizeof(av1_default_coeff_base_multi_cdfs[0])); + memcpy(cdfs->coeff_base_eob_cdf, + av1_default_coeff_base_eob_multi_cdfs[index], + sizeof(av1_default_coeff_base_eob_multi_cdfs[0])); + memcpy(cdfs->eob_flag_cdf16, av1_default_eob_multi16_cdfs[index], + sizeof(av1_default_eob_multi16_cdfs[0])); + memcpy(cdfs->eob_flag_cdf32, av1_default_eob_multi32_cdfs[index], + sizeof(av1_default_eob_multi32_cdfs[0])); + memcpy(cdfs->eob_flag_cdf64, av1_default_eob_multi64_cdfs[index], + sizeof(av1_default_eob_multi64_cdfs[0])); + memcpy(cdfs->eob_flag_cdf128, av1_default_eob_multi128_cdfs[index], + sizeof(av1_default_eob_multi128_cdfs[0])); + memcpy(cdfs->eob_flag_cdf256, av1_default_eob_multi256_cdfs[index], + sizeof(av1_default_eob_multi256_cdfs[0])); + memcpy(cdfs->eob_flag_cdf512, av1_default_eob_multi512_cdfs[index], + sizeof(av1_default_eob_multi512_cdfs[0])); + memcpy(cdfs->eob_flag_cdf1024, av1_default_eob_multi1024_cdfs[index], + sizeof(av1_default_eob_multi1024_cdfs[0])); +} + +void rockchip_av1_set_default_cdfs(struct av1cdfs *cdfs, + struct mvcdfs *cdfs_ndvc) +{ + memcpy(cdfs->partition_cdf, default_partition_cdf, + sizeof(cdfs->partition_cdf)); + + memcpy(cdfs->tx_type_intra0_cdf, default_intra_ext_tx0_cdf, + sizeof(cdfs->tx_type_intra0_cdf)); + memcpy(cdfs->tx_type_intra1_cdf, default_intra_ext_tx1_cdf, + sizeof(cdfs->tx_type_intra1_cdf)); + memcpy(cdfs->tx_type_inter_cdf, default_inter_ext_tx_cdf, + sizeof(cdfs->tx_type_inter_cdf)); + + memcpy(cdfs->vartx_part_cdf, default_txfm_partition_cdf, + sizeof(cdfs->vartx_part_cdf)); + memcpy(cdfs->mbskip_cdf, default_skip_cdfs, sizeof(cdfs->mbskip_cdf)); + memcpy(cdfs->delta_q_cdf, default_delta_q_cdf, + sizeof(cdfs->delta_q_cdf)); + memcpy(cdfs->delta_lf_multi_cdf, default_delta_lf_multi_cdf, + sizeof(cdfs->delta_lf_multi_cdf)); + memcpy(cdfs->delta_lf_cdf, default_delta_lf_cdf, + sizeof(cdfs->delta_lf_cdf)); + + memcpy(cdfs->segment_pred_cdf, default_segment_pred_cdf, + sizeof(cdfs->segment_pred_cdf)); + + memcpy(cdfs->spatial_pred_seg_tree_cdf, + default_spatial_pred_seg_tree_cdf, + sizeof(cdfs->spatial_pred_seg_tree_cdf)); + + memcpy(cdfs->skip_mode_cdf, default_skip_mode_cdfs, + sizeof(cdfs->skip_mode_cdf)); + + memcpy(cdfs->tx_size_cdf, default_tx_size_cdf, + sizeof(cdfs->tx_size_cdf)); + + memcpy(cdfs->kf_ymode_cdf, default_kf_y_mode_cdf, + sizeof(cdfs->kf_ymode_cdf)); + memcpy(cdfs->uv_mode_cdf, default_uv_mode_cdf, + sizeof(cdfs->uv_mode_cdf)); + memcpy(cdfs->if_ymode_cdf, default_if_y_mode_cdf, + sizeof(cdfs->if_ymode_cdf)); + + memcpy(cdfs->intra_inter_cdf, default_intra_inter_cdf, + sizeof(cdfs->intra_inter_cdf)); + + memcpy(cdfs->comp_ref_cdf, default_comp_ref_cdf, + sizeof(cdfs->comp_ref_cdf)); + memcpy(cdfs->comp_bwdref_cdf, default_comp_bwdref_cdf, + sizeof(cdfs->comp_bwdref_cdf)); + + memcpy(cdfs->comp_inter_cdf, default_comp_inter_cdf, + sizeof(cdfs->comp_inter_cdf)); + + memcpy(cdfs->single_ref_cdf, default_single_ref_cdf, + sizeof(cdfs->single_ref_cdf)); + memcpy(cdfs->comp_ref_type_cdf, default_comp_ref_type_cdf, + sizeof(cdfs->comp_ref_type_cdf)); + memcpy(cdfs->uni_comp_ref_cdf, default_uni_comp_ref_cdf, + sizeof(cdfs->uni_comp_ref_cdf)); + + memcpy(cdfs->newmv_cdf, default_newmv_cdf, sizeof(cdfs->newmv_cdf)); + memcpy(cdfs->zeromv_cdf, default_zeromv_cdf, sizeof(cdfs->zeromv_cdf)); + memcpy(cdfs->refmv_cdf, default_refmv_cdf, sizeof(cdfs->refmv_cdf)); + memcpy(cdfs->drl_cdf, default_drl_cdf, sizeof(cdfs->drl_cdf)); + + memcpy(cdfs->interp_filter_cdf, default_switchable_interp_cdf, + sizeof(cdfs->interp_filter_cdf)); + + // Regular MV cdfs + memcpy(cdfs->mv_cdf.joint_cdf, default_joint_cdf, + sizeof(cdfs->mv_cdf.joint_cdf)); + memcpy(cdfs->mv_cdf.sign_cdf, default_sign_cdf, + sizeof(cdfs->mv_cdf.sign_cdf)); + memcpy(cdfs->mv_cdf.clsss_cdf, default_clsss_cdf, + sizeof(cdfs->mv_cdf.clsss_cdf)); + memcpy(cdfs->mv_cdf.clsss0_fp_cdf, default_clsss0_fp_cdf, + sizeof(cdfs->mv_cdf.clsss0_fp_cdf)); + memcpy(cdfs->mv_cdf.fp_cdf, default_fp_cdf, + sizeof(cdfs->mv_cdf.fp_cdf)); + memcpy(cdfs->mv_cdf.class0_hp_cdf, default_class0_hp_cdf, + sizeof(cdfs->mv_cdf.class0_hp_cdf)); + memcpy(cdfs->mv_cdf.hp_cdf, default_hp_cdf, + sizeof(cdfs->mv_cdf.hp_cdf)); + memcpy(cdfs->mv_cdf.class0_cdf, default_class0_cdf, + sizeof(cdfs->mv_cdf.class0_cdf)); + memcpy(cdfs->mv_cdf.bits_cdf, default_bits_cdf, + sizeof(cdfs->mv_cdf.bits_cdf)); + + // Intrabc cdfs + memcpy(cdfs_ndvc->joint_cdf, default_joint_cdf, + sizeof(cdfs_ndvc->joint_cdf)); + memcpy(cdfs_ndvc->sign_cdf, default_sign_cdf, + sizeof(cdfs_ndvc->sign_cdf)); + memcpy(cdfs_ndvc->clsss_cdf, default_clsss_cdf, + sizeof(cdfs_ndvc->clsss_cdf)); + memcpy(cdfs_ndvc->clsss0_fp_cdf, default_clsss0_fp_cdf, + sizeof(cdfs_ndvc->clsss0_fp_cdf)); + memcpy(cdfs_ndvc->fp_cdf, default_fp_cdf, sizeof(cdfs_ndvc->fp_cdf)); + memcpy(cdfs_ndvc->class0_hp_cdf, default_class0_hp_cdf, + sizeof(cdfs_ndvc->class0_hp_cdf)); + memcpy(cdfs_ndvc->hp_cdf, default_hp_cdf, sizeof(cdfs_ndvc->hp_cdf)); + memcpy(cdfs_ndvc->class0_cdf, default_class0_cdf, + sizeof(cdfs_ndvc->class0_cdf)); + memcpy(cdfs_ndvc->bits_cdf, default_bits_cdf, + sizeof(cdfs_ndvc->bits_cdf)); + + memcpy(cdfs->obmc_cdf, default_obmc_cdf, sizeof(cdfs->obmc_cdf)); + memcpy(cdfs->motion_mode_cdf, default_motion_mode_cdf, + sizeof(cdfs->motion_mode_cdf)); + + memcpy(cdfs->inter_compound_mode_cdf, default_inter_compound_mode_cdf, + sizeof(cdfs->inter_compound_mode_cdf)); + memcpy(cdfs->compound_type_cdf, default_compound_type_cdf, + sizeof(cdfs->compound_type_cdf)); + memcpy(cdfs->interintra_cdf, default_interintra_cdf, + sizeof(cdfs->interintra_cdf)); + memcpy(cdfs->interintra_mode_cdf, default_interintra_mode_cdf, + sizeof(cdfs->interintra_mode_cdf)); + memcpy(cdfs->wedge_interintra_cdf, default_wedge_interintra_cdf, + sizeof(cdfs->wedge_interintra_cdf)); + memcpy(cdfs->wedge_idx_cdf, default_wedge_idx_cdf, + sizeof(cdfs->wedge_idx_cdf)); + + memcpy(cdfs->palette_y_mode_cdf, default_palette_y_mode_cdf, + sizeof(cdfs->palette_y_mode_cdf)); + memcpy(cdfs->palette_uv_mode_cdf, default_palette_uv_mode_cdf, + sizeof(cdfs->palette_uv_mode_cdf)); + memcpy(cdfs->palette_y_size_cdf, default_palette_y_size_cdf, + sizeof(cdfs->palette_y_size_cdf)); + memcpy(cdfs->palette_uv_size_cdf, default_palette_uv_size_cdf, + sizeof(cdfs->palette_uv_size_cdf)); + memcpy(cdfs->palette_y_color_index_cdf, + default_palette_y_color_index_cdf, + sizeof(cdfs->palette_y_color_index_cdf)); + memcpy(cdfs->palette_uv_color_index_cdf, + default_palette_uv_color_index_cdf, + sizeof(cdfs->palette_uv_color_index_cdf)); + + memcpy(cdfs->cfl_sign_cdf, default_cfl_sign_cdf, + sizeof(cdfs->cfl_sign_cdf)); + memcpy(cdfs->cfl_alpha_cdf, default_cfl_alpha_cdf, + sizeof(cdfs->cfl_alpha_cdf)); + + memcpy(cdfs->intrabc_cdf, default_intrabc_cdf, + sizeof(cdfs->intrabc_cdf)); + memcpy(cdfs->angle_delta_cdf, default_angle_delta_cdf, + sizeof(cdfs->angle_delta_cdf)); + memcpy(cdfs->filter_intra_mode_cdf, default_filter_intra_mode_cdf, + sizeof(cdfs->filter_intra_mode_cdf)); + memcpy(cdfs->filter_intra_cdf, default_filter_intra_cdfs, + sizeof(cdfs->filter_intra_cdf)); + memcpy(cdfs->comp_group_idx_cdf, default_comp_group_idx_cdfs, + sizeof(cdfs->comp_group_idx_cdf)); + memcpy(cdfs->compound_idx_cdf, default_compound_idx_cdfs, + sizeof(cdfs->compound_idx_cdf)); +} + +void rockchip_av1_get_cdfs(struct hantro_ctx *ctx, u32 ref_idx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + + av1_dec->cdfs = &av1_dec->cdfs_last[ref_idx]; + av1_dec->cdfs_ndvc = &av1_dec->cdfs_last_ndvc[ref_idx]; +} + +void rockchip_av1_store_cdfs(struct hantro_ctx *ctx, + u32 refresh_frame_flags) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + int i; + + for (i = 0; i < NUM_REF_FRAMES; i++) { + if (refresh_frame_flags & (1 << i)) { + if (&av1_dec->cdfs_last[i] != av1_dec->cdfs) { + av1_dec->cdfs_last[i] = *av1_dec->cdfs; + av1_dec->cdfs_last_ndvc[i] = + *av1_dec->cdfs_ndvc; + } + } + } +} diff --git a/drivers/media/platform/verisilicon/rockchip_av1_entropymode.h b/drivers/media/platform/verisilicon/rockchip_av1_entropymode.h new file mode 100644 index 000000000000..bbf8424c7d2c --- /dev/null +++ b/drivers/media/platform/verisilicon/rockchip_av1_entropymode.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ROCKCHIP_AV1_ENTROPYMODE_H_ +#define _ROCKCHIP_AV1_ENTROPYMODE_H_ + +#include <linux/types.h> + +struct hantro_ctx; + +#define AV1_INTER_MODE_CONTEXTS 15 +#define AV1_INTRA_MODES 13 +#define AV1_REF_CONTEXTS 3 +#define AV1_SWITCHABLE_FILTERS 3 /* number of switchable filters */ +#define AV1_TX_SIZE_CONTEXTS 3 +#define BLOCK_SIZE_GROUPS 4 +#define BR_CDF_SIZE 4 +#define BWD_REFS 3 +#define CFL_ALLOWED_TYPES 2 +#define CFL_ALPHA_CONTEXTS 6 +#define CFL_ALPHABET_SIZE 16 +#define CFL_JOINT_SIGNS 8 +#define CDF_SIZE(x) ((x) - 1) +#define COMP_GROUP_IDX_CONTEXTS 7 +#define COMP_INDEX_CONTEXTS 6 +#define COMP_INTER_CONTEXTS 5 +#define COMP_REF_TYPE_CONTEXTS 5 +#define COMPOUND_TYPES 3 +#define DC_SIGN_CONTEXTS 3 +#define DELTA_LF_PROBS 3 +#define DELTA_Q_PROBS 3 +#define DIRECTIONAL_MODES 8 +#define DRL_MODE_CONTEXTS 3 +#define EOB_COEF_CONTEXTS 9 +#define EXT_TX_SIZES 3 +#define EXT_TX_TYPES 16 +#define EXTTX_SIZES 4 +#define FRAME_LF_COUNT 4 +#define FWD_REFS 4 +#define GLOBALMV_MODE_CONTEXTS 2 +#define ICDF(x) (32768U - (x)) +#define INTER_COMPOUND_MODES 8 +#define INTERINTRA_MODES 4 +#define INTRA_INTER_CONTEXTS 4 +#define KF_MODE_CONTEXTS 5 +#define LEVEL_CONTEXTS 21 +#define MAX_ANGLE_DELTA 3 +#define MAX_MB_SEGMENTS 8 +#define MAX_SEGMENTS 8 +#define MAX_TX_CATS 4 +#define MAX_TX_DEPTH 2 +#define MBSKIP_CONTEXTS 3 +#define MOTION_MODES 3 +#define MOTION_MODE_CONTEXTS 10 +#define NEWMV_MODE_CONTEXTS 6 +#define NUM_BASE_LEVELS 2 +#define NUM_REF_FRAMES 8 +#define PALETTE_BLOCK_SIZES 7 +#define PALETTE_IDX_CONTEXTS 18 +#define PALETTE_SIZES 7 +#define PALETTE_UV_MODE_CONTEXTS 2 +#define PALETTE_Y_MODE_CONTEXTS 3 +#define PARTITION_PLOFFSET 4 +#define NUM_PARTITION_CONTEXTS (4 * PARTITION_PLOFFSET) +#define PLANE_TYPES 2 +#define PREDICTION_PROBS 3 +#define REF_CONTEXTS 5 +#define REFMV_MODE_CONTEXTS 9 +#define SEG_TEMPORAL_PRED_CTXS 3 +#define SIG_COEF_CONTEXTS 42 +#define SIG_COEF_CONTEXTS_EOB 4 +#define SINGLE_REFS 7 +#define SKIP_CONTEXTS 3 +#define SKIP_MODE_CONTEXTS 3 +#define SPATIAL_PREDICTION_PROBS 3 +#define SWITCHABLE_FILTER_CONTEXTS ((AV1_SWITCHABLE_FILTERS + 1) * 4) +#define TOKEN_CDF_Q_CTXS 4 +#define TX_SIZES 5 +#define TX_SIZE_CONTEXTS 2 +#define TX_TYPES 4 +#define TXB_SKIP_CONTEXTS 13 +#define TXFM_PARTITION_CONTEXTS 22 +#define UNI_COMP_REF_CONTEXTS 3 +#define UNIDIR_COMP_REFS 4 +#define UV_INTRA_MODES 14 +#define VARTX_PART_CONTEXTS 22 +#define ZEROMV_MODE_CONTEXTS 2 + +enum blocksizetype { + BLOCK_SIZE_AB4X4, + BLOCK_SIZE_SB4X8, + BLOCK_SIZE_SB8X4, + BLOCK_SIZE_SB8X8, + BLOCK_SIZE_SB8X16, + BLOCK_SIZE_SB16X8, + BLOCK_SIZE_MB16X16, + BLOCK_SIZE_SB16X32, + BLOCK_SIZE_SB32X16, + BLOCK_SIZE_SB32X32, + BLOCK_SIZE_SB32X64, + BLOCK_SIZE_SB64X32, + BLOCK_SIZE_SB64X64, + BLOCK_SIZE_SB64X128, + BLOCK_SIZE_SB128X64, + BLOCK_SIZE_SB128X128, + BLOCK_SIZE_SB4X16, + BLOCK_SIZE_SB16X4, + BLOCK_SIZE_SB8X32, + BLOCK_SIZE_SB32X8, + BLOCK_SIZE_SB16X64, + BLOCK_SIZE_SB64X16, + BLOCK_SIZE_TYPES, + BLOCK_SIZES_ALL = BLOCK_SIZE_TYPES +}; + +enum filterintramodetype { + FILTER_DC_PRED, + FILTER_V_PRED, + FILTER_H_PRED, + FILTER_D153_PRED, + FILTER_PAETH_PRED, + FILTER_INTRA_MODES, + FILTER_INTRA_UNUSED = 7 +}; + +enum frametype { + KEY_FRAME = 0, + INTER_FRAME = 1, + NUM_FRAME_TYPES, +}; + +enum txsize { + TX_4X4 = 0, + TX_8X8 = 1, + TX_16X16 = 2, + TX_32X32 = 3, + TX_SIZE_MAX_SB, +}; + +enum { SIMPLE_TRANSLATION, OBMC_CAUSAL, MOTION_MODE_COUNT }; + +enum mb_prediction_mode { + DC_PRED, /* average of above and left pixels */ + V_PRED, /* vertical prediction */ + H_PRED, /* horizontal prediction */ + D45_PRED, /* Directional 45 deg prediction [anti-clockwise from 0 deg hor] */ + D135_PRED, /* Directional 135 deg prediction [anti-clockwise from 0 deg hor] */ + D117_PRED, /* Directional 112 deg prediction [anti-clockwise from 0 deg hor] */ + D153_PRED, /* Directional 157 deg prediction [anti-clockwise from 0 deg hor] */ + D27_PRED, /* Directional 22 deg prediction [anti-clockwise from 0 deg hor] */ + D63_PRED, /* Directional 67 deg prediction [anti-clockwise from 0 deg hor] */ + SMOOTH_PRED, + TM_PRED_AV1 = SMOOTH_PRED, + SMOOTH_V_PRED, // Vertical interpolation + SMOOTH_H_PRED, // Horizontal interpolation + TM_PRED, /* Truemotion prediction */ + PAETH_PRED = TM_PRED, + NEARESTMV, + NEARMV, + ZEROMV, + NEWMV, + NEAREST_NEARESTMV, + NEAR_NEARMV, + NEAREST_NEWMV, + NEW_NEARESTMV, + NEAR_NEWMV, + NEW_NEARMV, + ZERO_ZEROMV, + NEW_NEWMV, + SPLITMV, + MB_MODE_COUNT +}; + +enum partitiontype { + PARTITION_NONE, + PARTITION_HORZ, + PARTITION_VERT, + PARTITION_SPLIT, + PARTITION_TYPES +}; + +struct mvcdfs { + u16 joint_cdf[3]; + u16 sign_cdf[2]; + u16 clsss_cdf[2][10]; + u16 clsss0_fp_cdf[2][2][3]; + u16 fp_cdf[2][3]; + u16 class0_hp_cdf[2]; + u16 hp_cdf[2]; + u16 class0_cdf[2]; + u16 bits_cdf[2][10]; +}; + +struct av1cdfs { + u16 partition_cdf[13][16]; + u16 kf_ymode_cdf[KF_MODE_CONTEXTS][KF_MODE_CONTEXTS][AV1_INTRA_MODES - 1]; + u16 segment_pred_cdf[PREDICTION_PROBS]; + u16 spatial_pred_seg_tree_cdf[SPATIAL_PREDICTION_PROBS][MAX_MB_SEGMENTS - 1]; + u16 mbskip_cdf[MBSKIP_CONTEXTS]; + u16 delta_q_cdf[DELTA_Q_PROBS]; + u16 delta_lf_multi_cdf[FRAME_LF_COUNT][DELTA_LF_PROBS]; + u16 delta_lf_cdf[DELTA_LF_PROBS]; + u16 skip_mode_cdf[SKIP_MODE_CONTEXTS]; + u16 vartx_part_cdf[VARTX_PART_CONTEXTS][1]; + u16 tx_size_cdf[MAX_TX_CATS][AV1_TX_SIZE_CONTEXTS][MAX_TX_DEPTH]; + u16 if_ymode_cdf[BLOCK_SIZE_GROUPS][AV1_INTRA_MODES - 1]; + u16 uv_mode_cdf[2][AV1_INTRA_MODES][AV1_INTRA_MODES - 1 + 1]; + u16 intra_inter_cdf[INTRA_INTER_CONTEXTS]; + u16 comp_inter_cdf[COMP_INTER_CONTEXTS]; + u16 single_ref_cdf[AV1_REF_CONTEXTS][SINGLE_REFS - 1]; + u16 comp_ref_type_cdf[COMP_REF_TYPE_CONTEXTS][1]; + u16 uni_comp_ref_cdf[UNI_COMP_REF_CONTEXTS][UNIDIR_COMP_REFS - 1][1]; + u16 comp_ref_cdf[AV1_REF_CONTEXTS][FWD_REFS - 1]; + u16 comp_bwdref_cdf[AV1_REF_CONTEXTS][BWD_REFS - 1]; + u16 newmv_cdf[NEWMV_MODE_CONTEXTS]; + u16 zeromv_cdf[ZEROMV_MODE_CONTEXTS]; + u16 refmv_cdf[REFMV_MODE_CONTEXTS]; + u16 drl_cdf[DRL_MODE_CONTEXTS]; + u16 interp_filter_cdf[SWITCHABLE_FILTER_CONTEXTS][AV1_SWITCHABLE_FILTERS - 1]; + struct mvcdfs mv_cdf; + u16 obmc_cdf[BLOCK_SIZE_TYPES]; + u16 motion_mode_cdf[BLOCK_SIZE_TYPES][2]; + u16 inter_compound_mode_cdf[AV1_INTER_MODE_CONTEXTS][INTER_COMPOUND_MODES - 1]; + u16 compound_type_cdf[BLOCK_SIZE_TYPES][CDF_SIZE(COMPOUND_TYPES - 1)]; + u16 interintra_cdf[BLOCK_SIZE_GROUPS]; + u16 interintra_mode_cdf[BLOCK_SIZE_GROUPS][INTERINTRA_MODES - 1]; + u16 wedge_interintra_cdf[BLOCK_SIZE_TYPES]; + u16 wedge_idx_cdf[BLOCK_SIZE_TYPES][CDF_SIZE(16)]; + u16 palette_y_mode_cdf[PALETTE_BLOCK_SIZES][PALETTE_Y_MODE_CONTEXTS][1]; + u16 palette_uv_mode_cdf[PALETTE_UV_MODE_CONTEXTS][1]; + u16 palette_y_size_cdf[PALETTE_BLOCK_SIZES][PALETTE_SIZES - 1]; + u16 palette_uv_size_cdf[PALETTE_BLOCK_SIZES][PALETTE_SIZES - 1]; + u16 cfl_sign_cdf[CFL_JOINT_SIGNS - 1]; + u16 cfl_alpha_cdf[CFL_ALPHA_CONTEXTS][CFL_ALPHABET_SIZE - 1]; + u16 intrabc_cdf[1]; + u16 angle_delta_cdf[DIRECTIONAL_MODES][6]; + u16 filter_intra_mode_cdf[FILTER_INTRA_MODES - 1]; + u16 filter_intra_cdf[BLOCK_SIZES_ALL]; + u16 comp_group_idx_cdf[COMP_GROUP_IDX_CONTEXTS][CDF_SIZE(2)]; + u16 compound_idx_cdf[COMP_INDEX_CONTEXTS][CDF_SIZE(2)]; + u16 dummy0[14]; + // Palette index contexts; sizes 1/7, 2/6, 3/5 packed together + u16 palette_y_color_index_cdf[PALETTE_IDX_CONTEXTS][8]; + u16 palette_uv_color_index_cdf[PALETTE_IDX_CONTEXTS][8]; + u16 tx_type_intra0_cdf[EXTTX_SIZES][AV1_INTRA_MODES][8]; + u16 tx_type_intra1_cdf[EXTTX_SIZES][AV1_INTRA_MODES][4]; + u16 tx_type_inter_cdf[2][EXTTX_SIZES][EXT_TX_TYPES]; + u16 txb_skip_cdf[TX_SIZES][TXB_SKIP_CONTEXTS][CDF_SIZE(2)]; + u16 eob_extra_cdf[TX_SIZES][PLANE_TYPES][EOB_COEF_CONTEXTS][CDF_SIZE(2)]; + u16 dummy1[5]; + u16 eob_flag_cdf16[PLANE_TYPES][2][4]; + u16 eob_flag_cdf32[PLANE_TYPES][2][8]; + u16 eob_flag_cdf64[PLANE_TYPES][2][8]; + u16 eob_flag_cdf128[PLANE_TYPES][2][8]; + u16 eob_flag_cdf256[PLANE_TYPES][2][8]; + u16 eob_flag_cdf512[PLANE_TYPES][2][16]; + u16 eob_flag_cdf1024[PLANE_TYPES][2][16]; + u16 coeff_base_eob_cdf[TX_SIZES][PLANE_TYPES][SIG_COEF_CONTEXTS_EOB][CDF_SIZE(3)]; + u16 coeff_base_cdf[TX_SIZES][PLANE_TYPES][SIG_COEF_CONTEXTS][CDF_SIZE(4) + 1]; + u16 dc_sign_cdf[PLANE_TYPES][DC_SIGN_CONTEXTS][CDF_SIZE(2)]; + u16 dummy2[2]; + u16 coeff_br_cdf[TX_SIZES][PLANE_TYPES][LEVEL_CONTEXTS][CDF_SIZE(BR_CDF_SIZE) + 1]; + u16 dummy3[16]; +}; + +void rockchip_av1_store_cdfs(struct hantro_ctx *ctx, + u32 refresh_frame_flags); +void rockchip_av1_get_cdfs(struct hantro_ctx *ctx, u32 ref_idx); +void rockchip_av1_set_default_cdfs(struct av1cdfs *cdfs, + struct mvcdfs *cdfs_ndvc); +void rockchip_av1_default_coeff_probs(u32 base_qindex, void *ptr); + +#endif /* _ROCKCHIP_AV1_ENTROPYMODE_H_ */ diff --git a/drivers/media/platform/verisilicon/rockchip_av1_filmgrain.c b/drivers/media/platform/verisilicon/rockchip_av1_filmgrain.c new file mode 100644 index 000000000000..f2ae84f0b436 --- /dev/null +++ b/drivers/media/platform/verisilicon/rockchip_av1_filmgrain.c @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0-only or Apache-2.0 + +#include "rockchip_av1_filmgrain.h" + +static const s32 gaussian_sequence[2048] = { + 56, 568, -180, 172, 124, -84, 172, -64, -900, 24, 820, + 224, 1248, 996, 272, -8, -916, -388, -732, -104, -188, 800, + 112, -652, -320, -376, 140, -252, 492, -168, 44, -788, 588, + -584, 500, -228, 12, 680, 272, -476, 972, -100, 652, 368, + 432, -196, -720, -192, 1000, -332, 652, -136, -552, -604, -4, + 192, -220, -136, 1000, -52, 372, -96, -624, 124, -24, 396, + 540, -12, -104, 640, 464, 244, -208, -84, 368, -528, -740, + 248, -968, -848, 608, 376, -60, -292, -40, -156, 252, -292, + 248, 224, -280, 400, -244, 244, -60, 76, -80, 212, 532, + 340, 128, -36, 824, -352, -60, -264, -96, -612, 416, -704, + 220, -204, 640, -160, 1220, -408, 900, 336, 20, -336, -96, + -792, 304, 48, -28, -1232, -1172, -448, 104, -292, -520, 244, + 60, -948, 0, -708, 268, 108, 356, -548, 488, -344, -136, + 488, -196, -224, 656, -236, -1128, 60, 4, 140, 276, -676, + -376, 168, -108, 464, 8, 564, 64, 240, 308, -300, -400, + -456, -136, 56, 120, -408, -116, 436, 504, -232, 328, 844, + -164, -84, 784, -168, 232, -224, 348, -376, 128, 568, 96, + -1244, -288, 276, 848, 832, -360, 656, 464, -384, -332, -356, + 728, -388, 160, -192, 468, 296, 224, 140, -776, -100, 280, + 4, 196, 44, -36, -648, 932, 16, 1428, 28, 528, 808, + 772, 20, 268, 88, -332, -284, 124, -384, -448, 208, -228, + -1044, -328, 660, 380, -148, -300, 588, 240, 540, 28, 136, + -88, -436, 256, 296, -1000, 1400, 0, -48, 1056, -136, 264, + -528, -1108, 632, -484, -592, -344, 796, 124, -668, -768, 388, + 1296, -232, -188, -200, -288, -4, 308, 100, -168, 256, -500, + 204, -508, 648, -136, 372, -272, -120, -1004, -552, -548, -384, + 548, -296, 428, -108, -8, -912, -324, -224, -88, -112, -220, + -100, 996, -796, 548, 360, -216, 180, 428, -200, -212, 148, + 96, 148, 284, 216, -412, -320, 120, -300, -384, -604, -572, + -332, -8, -180, -176, 696, 116, -88, 628, 76, 44, -516, + 240, -208, -40, 100, -592, 344, -308, -452, -228, 20, 916, + -1752, -136, -340, -804, 140, 40, 512, 340, 248, 184, -492, + 896, -156, 932, -628, 328, -688, -448, -616, -752, -100, 560, + -1020, 180, -800, -64, 76, 576, 1068, 396, 660, 552, -108, + -28, 320, -628, 312, -92, -92, -472, 268, 16, 560, 516, + -672, -52, 492, -100, 260, 384, 284, 292, 304, -148, 88, + -152, 1012, 1064, -228, 164, -376, -684, 592, -392, 156, 196, + -524, -64, -884, 160, -176, 636, 648, 404, -396, -436, 864, + 424, -728, 988, -604, 904, -592, 296, -224, 536, -176, -920, + 436, -48, 1176, -884, 416, -776, -824, -884, 524, -548, -564, + -68, -164, -96, 692, 364, -692, -1012, -68, 260, -480, 876, + -1116, 452, -332, -352, 892, -1088, 1220, -676, 12, -292, 244, + 496, 372, -32, 280, 200, 112, -440, -96, 24, -644, -184, + 56, -432, 224, -980, 272, -260, 144, -436, 420, 356, 364, + -528, 76, 172, -744, -368, 404, -752, -416, 684, -688, 72, + 540, 416, 92, 444, 480, -72, -1416, 164, -1172, -68, 24, + 424, 264, 1040, 128, -912, -524, -356, 64, 876, -12, 4, + -88, 532, 272, -524, 320, 276, -508, 940, 24, -400, -120, + 756, 60, 236, -412, 100, 376, -484, 400, -100, -740, -108, + -260, 328, -268, 224, -200, -416, 184, -604, -564, -20, 296, + 60, 892, -888, 60, 164, 68, -760, 216, -296, 904, -336, + -28, 404, -356, -568, -208, -1480, -512, 296, 328, -360, -164, + -1560, -776, 1156, -428, 164, -504, -112, 120, -216, -148, -264, + 308, 32, 64, -72, 72, 116, 176, -64, -272, 460, -536, + -784, -280, 348, 108, -752, -132, 524, -540, -776, 116, -296, + -1196, -288, -560, 1040, -472, 116, -848, -1116, 116, 636, 696, + 284, -176, 1016, 204, -864, -648, -248, 356, 972, -584, -204, + 264, 880, 528, -24, -184, 116, 448, -144, 828, 524, 212, + -212, 52, 12, 200, 268, -488, -404, -880, 824, -672, -40, + 908, -248, 500, 716, -576, 492, -576, 16, 720, -108, 384, + 124, 344, 280, 576, -500, 252, 104, -308, 196, -188, -8, + 1268, 296, 1032, -1196, 436, 316, 372, -432, -200, -660, 704, + -224, 596, -132, 268, 32, -452, 884, 104, -1008, 424, -1348, + -280, 4, -1168, 368, 476, 696, 300, -8, 24, 180, -592, + -196, 388, 304, 500, 724, -160, 244, -84, 272, -256, -420, + 320, 208, -144, -156, 156, 364, 452, 28, 540, 316, 220, + -644, -248, 464, 72, 360, 32, -388, 496, -680, -48, 208, + -116, -408, 60, -604, -392, 548, -840, 784, -460, 656, -544, + -388, -264, 908, -800, -628, -612, -568, 572, -220, 164, 288, + -16, -308, 308, -112, -636, -760, 280, -668, 432, 364, 240, + -196, 604, 340, 384, 196, 592, -44, -500, 432, -580, -132, + 636, -76, 392, 4, -412, 540, 508, 328, -356, -36, 16, + -220, -64, -248, -60, 24, -192, 368, 1040, 92, -24, -1044, + -32, 40, 104, 148, 192, -136, -520, 56, -816, -224, 732, + 392, 356, 212, -80, -424, -1008, -324, 588, -1496, 576, 460, + -816, -848, 56, -580, -92, -1372, -112, -496, 200, 364, 52, + -140, 48, -48, -60, 84, 72, 40, 132, -356, -268, -104, + -284, -404, 732, -520, 164, -304, -540, 120, 328, -76, -460, + 756, 388, 588, 236, -436, -72, -176, -404, -316, -148, 716, + -604, 404, -72, -88, -888, -68, 944, 88, -220, -344, 960, + 472, 460, -232, 704, 120, 832, -228, 692, -508, 132, -476, + 844, -748, -364, -44, 1116, -1104, -1056, 76, 428, 552, -692, + 60, 356, 96, -384, -188, -612, -576, 736, 508, 892, 352, + -1132, 504, -24, -352, 324, 332, -600, -312, 292, 508, -144, + -8, 484, 48, 284, -260, -240, 256, -100, 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156, 180, -252, 944, -924, -772, -520, -428, -624, 300, + -212, -1144, 32, -724, 800, -1128, -212, -1288, -848, 180, -416, + 440, 192, -576, -792, -76, -1080, 80, -532, -352, -132, 380, + -820, 148, 1112, 128, 164, 456, 700, -924, 144, -668, -384, + 648, -832, 508, 552, -52, -100, -656, 208, -568, 748, -88, + 680, 232, 300, 192, -408, -1012, -152, -252, -268, 272, -876, + -664, -648, -332, -136, 16, 12, 1152, -28, 332, -536, 320, + -672, -460, -316, 532, -260, 228, -40, 1052, -816, 180, 88, + -496, -556, -672, -368, 428, 92, 356, 404, -408, 252, 196, + -176, -556, 792, 268, 32, 372, 40, 96, -332, 328, 120, + 372, -900, -40, 472, -264, -592, 952, 128, 656, 112, 664, + -232, 420, 4, -344, -464, 556, 244, -416, -32, 252, 0, + -412, 188, -696, 508, -476, 324, -1096, 656, -312, 560, 264, + -136, 304, 160, -64, -580, 248, 336, -720, 560, -348, -288, + -276, -196, -500, 852, -544, -236, -1128, -992, -776, 116, 56, + 52, 860, 884, 212, -12, 168, 1020, 512, -552, 924, -148, + 716, 188, 164, -340, -520, -184, 880, -152, -680, -208, -1156, + -300, -528, -472, 364, 100, -744, -1056, -32, 540, 280, 144, + -676, -32, -232, -280, -224, 96, 568, -76, 172, 148, 148, + 104, 32, -296, -32, 788, -80, 32, -16, 280, 288, 944, + 428, -484 +}; + +static inline s32 clamp(s32 value, s32 low, s32 high) +{ + return value < low ? low : (value > high ? high : value); +} + +static inline s32 round_power_of_two(const s32 val, s32 n) +{ + const s32 a = (s32)1 << (n - 1); + + return (val + a) >> n; +} + +static void rockchip_av1_init_random_generator(u8 luma_num, u16 seed, + u16 *random_register) +{ + u16 random_reg = seed; + + random_reg ^= ((luma_num * 37 + 178) & 255) << 8; + random_reg ^= ((luma_num * 173 + 105) & 255); + *random_register = random_reg; +} + +static inline void rockchip_av1_update_random_register(u16 *random_register) +{ + u16 bit; + u16 random_reg = *random_register; + + bit = ((random_reg >> 0) ^ (random_reg >> 1) ^ (random_reg >> 3) ^ + (random_reg >> 12)) & 1; + *random_register = (random_reg >> 1) | (bit << 15); +} + +static inline s32 rockchip_av1_get_random_number(u16 random_register) +{ + return (random_register >> 5) & ((1 << 11) - 1); +} + +void rockchip_av1_generate_luma_grain_block(s32 (*luma_grain_block)[73][82], + s32 bitdepth, + u8 num_y_points, + s32 grain_scale_shift, + s32 ar_coeff_lag, + s32 (*ar_coeffs_y)[24], + s32 ar_coeff_shift, + s32 grain_min, + s32 grain_max, + u16 random_seed) +{ + s32 gauss_sec_shift = 12 - bitdepth + grain_scale_shift; + u16 grain_random_register = random_seed; + s32 i, j; + + for (i = 0; i < 73; i++) { + for (j = 0; j < 82; j++) { + if (num_y_points > 0) { + rockchip_av1_update_random_register + (&grain_random_register); + (*luma_grain_block)[i][j] = + round_power_of_two(gaussian_sequence + [rockchip_av1_get_random_number + (grain_random_register)], + gauss_sec_shift); + } else { + (*luma_grain_block)[i][j] = 0; + } + } + } + + for (i = 3; i < 73; i++) + for (j = 3; j < 82 - 3; j++) { + s32 pos = 0; + s32 wsum = 0; + s32 deltarow, deltacol; + + for (deltarow = -ar_coeff_lag; deltarow <= 0; + deltarow++) { + for (deltacol = -ar_coeff_lag; + deltacol <= ar_coeff_lag; deltacol++) { + if (deltarow == 0 && deltacol == 0) + break; + wsum = wsum + (*ar_coeffs_y)[pos] * + (*luma_grain_block)[i + deltarow][j + deltacol]; + ++pos; + } + } + (*luma_grain_block)[i][j] = + clamp((*luma_grain_block)[i][j] + + round_power_of_two(wsum, ar_coeff_shift), + grain_min, grain_max); + } +} + +// Calculate chroma grain noise once per frame +void rockchip_av1_generate_chroma_grain_block(s32 (*luma_grain_block)[73][82], + s32 (*cb_grain_block)[38][44], + s32 (*cr_grain_block)[38][44], + s32 bitdepth, + u8 num_y_points, + u8 num_cb_points, + u8 num_cr_points, + s32 grain_scale_shift, + s32 ar_coeff_lag, + s32 (*ar_coeffs_cb)[25], + s32 (*ar_coeffs_cr)[25], + s32 ar_coeff_shift, + s32 grain_min, + s32 grain_max, + u8 chroma_scaling_from_luma, + u16 random_seed) +{ + s32 gauss_sec_shift = 12 - bitdepth + grain_scale_shift; + u16 grain_random_register = 0; + s32 i, j; + + rockchip_av1_init_random_generator(7, random_seed, + &grain_random_register); + for (i = 0; i < 38; i++) { + for (j = 0; j < 44; j++) { + if (num_cb_points || chroma_scaling_from_luma) { + rockchip_av1_update_random_register + (&grain_random_register); + (*cb_grain_block)[i][j] = + round_power_of_two(gaussian_sequence + [rockchip_av1_get_random_number + (grain_random_register)], + gauss_sec_shift); + } else { + (*cb_grain_block)[i][j] = 0; + } + } + } + + rockchip_av1_init_random_generator(11, random_seed, + &grain_random_register); + for (i = 0; i < 38; i++) { + for (j = 0; j < 44; j++) { + if (num_cr_points || chroma_scaling_from_luma) { + rockchip_av1_update_random_register + (&grain_random_register); + (*cr_grain_block)[i][j] = + round_power_of_two(gaussian_sequence + [rockchip_av1_get_random_number + (grain_random_register)], + gauss_sec_shift); + } else { + (*cr_grain_block)[i][j] = 0; + } + } + } + + for (i = 3; i < 38; i++) { + for (j = 3; j < 44 - 3; j++) { + s32 wsum_cb = 0; + s32 wsum_cr = 0; + s32 pos = 0; + s32 deltarow, deltacol; + + for (deltarow = -ar_coeff_lag; deltarow <= 0; + deltarow++) { + for (deltacol = -ar_coeff_lag; + deltacol <= ar_coeff_lag; deltacol++) { + if (deltarow == 0 && deltacol == 0) + break; + wsum_cb = wsum_cb + (*ar_coeffs_cb)[pos] * + (*cb_grain_block)[i + deltarow][j + deltacol]; + wsum_cr = + wsum_cr + + (*ar_coeffs_cr)[pos] * + (*cr_grain_block)[i + deltarow][j + deltacol]; + ++pos; + } + } + + if (num_y_points > 0) { + s32 av_luma = 0; + s32 luma_coord_y = (i << 1) - 3; + s32 luma_coord_x = (j << 1) - 3; + + av_luma += + (*luma_grain_block)[luma_coord_y][luma_coord_x]; + av_luma += + (*luma_grain_block)[luma_coord_y][luma_coord_x + 1]; + av_luma += + (*luma_grain_block)[luma_coord_y + 1][luma_coord_x]; + av_luma += + (*luma_grain_block)[(luma_coord_y + 1)][luma_coord_x + 1]; + av_luma = round_power_of_two(av_luma, 2); + + wsum_cb = wsum_cb + (*ar_coeffs_cb)[pos] * av_luma; + wsum_cr = wsum_cr + (*ar_coeffs_cr)[pos] * av_luma; + } + + if (num_cb_points || chroma_scaling_from_luma) { + (*cb_grain_block)[i][j] = + clamp((*cb_grain_block)[i][j] + + round_power_of_two(wsum_cb, ar_coeff_shift), + grain_min, grain_max); + } + if (num_cr_points || chroma_scaling_from_luma) { + (*cr_grain_block)[i][j] = + clamp((*cr_grain_block)[i][j] + + round_power_of_two(wsum_cr, ar_coeff_shift), + grain_min, grain_max); + } + } + } +} diff --git a/drivers/media/platform/verisilicon/rockchip_av1_filmgrain.h b/drivers/media/platform/verisilicon/rockchip_av1_filmgrain.h new file mode 100644 index 000000000000..31a8b7920c31 --- /dev/null +++ b/drivers/media/platform/verisilicon/rockchip_av1_filmgrain.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ROCKCHIP_AV1_FILMGRAIN_H_ +#define _ROCKCHIP_AV1_FILMGRAIN_H_ + +#include <linux/types.h> + +void rockchip_av1_generate_luma_grain_block(s32 (*luma_grain_block)[73][82], + s32 bitdepth, + u8 num_y_points, + s32 grain_scale_shift, + s32 ar_coeff_lag, + s32 (*ar_coeffs_y)[24], + s32 ar_coeff_shift, + s32 grain_min, + s32 grain_max, + u16 random_seed); + +void rockchip_av1_generate_chroma_grain_block(s32 (*luma_grain_block)[73][82], + s32 (*cb_grain_block)[38][44], + s32 (*cr_grain_block)[38][44], + s32 bitdepth, + u8 num_y_points, + u8 num_cb_points, + u8 num_cr_points, + s32 grain_scale_shift, + s32 ar_coeff_lag, + s32 (*ar_coeffs_cb)[25], + s32 (*ar_coeffs_cr)[25], + s32 ar_coeff_shift, + s32 grain_min, + s32 grain_max, + u8 chroma_scaling_from_luma, + u16 random_seed); + +#endif diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c new file mode 100644 index 000000000000..cc4483857489 --- /dev/null +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c @@ -0,0 +1,2232 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Collabora + * + * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com> + */ + +#include <media/v4l2-mem2mem.h> +#include "hantro.h" +#include "hantro_v4l2.h" +#include "rockchip_vpu981_regs.h" + +#define AV1_DEC_MODE 17 +#define GM_GLOBAL_MODELS_PER_FRAME 7 +#define GLOBAL_MODEL_TOTAL_SIZE (6 * 4 + 4 * 2) +#define GLOBAL_MODEL_SIZE ALIGN(GM_GLOBAL_MODELS_PER_FRAME * GLOBAL_MODEL_TOTAL_SIZE, 2048) +#define AV1_MAX_TILES 128 +#define AV1_TILE_INFO_SIZE (AV1_MAX_TILES * 16) +#define AV1DEC_MAX_PIC_BUFFERS 24 +#define AV1_REF_SCALE_SHIFT 14 +#define AV1_INVALID_IDX -1 +#define MAX_FRAME_DISTANCE 31 +#define AV1_PRIMARY_REF_NONE 7 +#define AV1_TILE_SIZE ALIGN(32 * 128, 4096) +/* + * These 3 values aren't defined enum v4l2_av1_segment_feature because + * they are not part of the specification + */ +#define V4L2_AV1_SEG_LVL_ALT_LF_Y_H 2 +#define V4L2_AV1_SEG_LVL_ALT_LF_U 3 +#define V4L2_AV1_SEG_LVL_ALT_LF_V 4 + +#define SUPERRES_SCALE_BITS 3 +#define SCALE_NUMERATOR 8 +#define SUPERRES_SCALE_DENOMINATOR_MIN (SCALE_NUMERATOR + 1) + +#define RS_SUBPEL_BITS 6 +#define RS_SUBPEL_MASK ((1 << RS_SUBPEL_BITS) - 1) +#define RS_SCALE_SUBPEL_BITS 14 +#define RS_SCALE_SUBPEL_MASK ((1 << RS_SCALE_SUBPEL_BITS) - 1) +#define RS_SCALE_EXTRA_BITS (RS_SCALE_SUBPEL_BITS - RS_SUBPEL_BITS) +#define RS_SCALE_EXTRA_OFF (1 << (RS_SCALE_EXTRA_BITS - 1)) + +#define IS_INTRA(type) ((type == V4L2_AV1_KEY_FRAME) || (type == V4L2_AV1_INTRA_ONLY_FRAME)) + +#define LST_BUF_IDX (V4L2_AV1_REF_LAST_FRAME - V4L2_AV1_REF_LAST_FRAME) +#define LST2_BUF_IDX (V4L2_AV1_REF_LAST2_FRAME - V4L2_AV1_REF_LAST_FRAME) +#define LST3_BUF_IDX (V4L2_AV1_REF_LAST3_FRAME - V4L2_AV1_REF_LAST_FRAME) +#define GLD_BUF_IDX (V4L2_AV1_REF_GOLDEN_FRAME - V4L2_AV1_REF_LAST_FRAME) +#define BWD_BUF_IDX (V4L2_AV1_REF_BWDREF_FRAME - V4L2_AV1_REF_LAST_FRAME) +#define ALT2_BUF_IDX (V4L2_AV1_REF_ALTREF2_FRAME - V4L2_AV1_REF_LAST_FRAME) +#define ALT_BUF_IDX (V4L2_AV1_REF_ALTREF_FRAME - V4L2_AV1_REF_LAST_FRAME) + +#define DIV_LUT_PREC_BITS 14 +#define DIV_LUT_BITS 8 +#define DIV_LUT_NUM BIT(DIV_LUT_BITS) +#define WARP_PARAM_REDUCE_BITS 6 +#define WARPEDMODEL_PREC_BITS 16 + +#define AV1_DIV_ROUND_UP_POW2(value, n) \ +({ \ + typeof(n) _n = n; \ + typeof(value) _value = value; \ + (_value + (BIT(_n) >> 1)) >> _n; \ +}) + +#define AV1_DIV_ROUND_UP_POW2_SIGNED(value, n) \ +({ \ + typeof(n) _n_ = n; \ + typeof(value) _value_ = value; \ + (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \ + : AV1_DIV_ROUND_UP_POW2((_value_), (_n_))); \ +}) + +struct rockchip_av1_film_grain { + u8 scaling_lut_y[256]; + u8 scaling_lut_cb[256]; + u8 scaling_lut_cr[256]; + s16 cropped_luma_grain_block[4096]; + s16 cropped_chroma_grain_block[1024 * 2]; +}; + +static const short div_lut[DIV_LUT_NUM + 1] = { + 16384, 16320, 16257, 16194, 16132, 16070, 16009, 15948, 15888, 15828, 15768, + 15709, 15650, 15592, 15534, 15477, 15420, 15364, 15308, 15252, 15197, 15142, + 15087, 15033, 14980, 14926, 14873, 14821, 14769, 14717, 14665, 14614, 14564, + 14513, 14463, 14413, 14364, 14315, 14266, 14218, 14170, 14122, 14075, 14028, + 13981, 13935, 13888, 13843, 13797, 13752, 13707, 13662, 13618, 13574, 13530, + 13487, 13443, 13400, 13358, 13315, 13273, 13231, 13190, 13148, 13107, 13066, + 13026, 12985, 12945, 12906, 12866, 12827, 12788, 12749, 12710, 12672, 12633, + 12596, 12558, 12520, 12483, 12446, 12409, 12373, 12336, 12300, 12264, 12228, + 12193, 12157, 12122, 12087, 12053, 12018, 11984, 11950, 11916, 11882, 11848, + 11815, 11782, 11749, 11716, 11683, 11651, 11619, 11586, 11555, 11523, 11491, + 11460, 11429, 11398, 11367, 11336, 11305, 11275, 11245, 11215, 11185, 11155, + 11125, 11096, 11067, 11038, 11009, 10980, 10951, 10923, 10894, 10866, 10838, + 10810, 10782, 10755, 10727, 10700, 10673, 10645, 10618, 10592, 10565, 10538, + 10512, 10486, 10460, 10434, 10408, 10382, 10356, 10331, 10305, 10280, 10255, + 10230, 10205, 10180, 10156, 10131, 10107, 10082, 10058, 10034, 10010, 9986, + 9963, 9939, 9916, 9892, 9869, 9846, 9823, 9800, 9777, 9754, 9732, + 9709, 9687, 9664, 9642, 9620, 9598, 9576, 9554, 9533, 9511, 9489, + 9468, 9447, 9425, 9404, 9383, 9362, 9341, 9321, 9300, 9279, 9259, + 9239, 9218, 9198, 9178, 9158, 9138, 9118, 9098, 9079, 9059, 9039, + 9020, 9001, 8981, 8962, 8943, 8924, 8905, 8886, 8867, 8849, 8830, + 8812, 8793, 8775, 8756, 8738, 8720, 8702, 8684, 8666, 8648, 8630, + 8613, 8595, 8577, 8560, 8542, 8525, 8508, 8490, 8473, 8456, 8439, + 8422, 8405, 8389, 8372, 8355, 8339, 8322, 8306, 8289, 8273, 8257, + 8240, 8224, 8208, 8192, +}; + +static int rockchip_vpu981_get_frame_index(struct hantro_ctx *ctx, int ref) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + u64 timestamp; + int i, idx = frame->ref_frame_idx[ref]; + + if (idx >= V4L2_AV1_TOTAL_REFS_PER_FRAME || idx < 0) + return AV1_INVALID_IDX; + + timestamp = frame->reference_frame_ts[idx]; + for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { + if (!av1_dec->frame_refs[i].used) + continue; + if (av1_dec->frame_refs[i].timestamp == timestamp) + return i; + } + + return AV1_INVALID_IDX; +} + +static int rockchip_vpu981_get_order_hint(struct hantro_ctx *ctx, int ref) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + int idx = rockchip_vpu981_get_frame_index(ctx, ref); + + if (idx != AV1_INVALID_IDX) + return av1_dec->frame_refs[idx].order_hint; + + return 0; +} + +static int rockchip_vpu981_av1_dec_frame_ref(struct hantro_ctx *ctx, + u64 timestamp) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + int i; + + for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { + int j; + + if (av1_dec->frame_refs[i].used) + continue; + + av1_dec->frame_refs[i].width = frame->frame_width_minus_1 + 1; + av1_dec->frame_refs[i].height = frame->frame_height_minus_1 + 1; + av1_dec->frame_refs[i].mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); + av1_dec->frame_refs[i].mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); + av1_dec->frame_refs[i].timestamp = timestamp; + av1_dec->frame_refs[i].frame_type = frame->frame_type; + av1_dec->frame_refs[i].order_hint = frame->order_hint; + if (!av1_dec->frame_refs[i].vb2_ref) + av1_dec->frame_refs[i].vb2_ref = hantro_get_dst_buf(ctx); + + for (j = 0; j < V4L2_AV1_TOTAL_REFS_PER_FRAME; j++) + av1_dec->frame_refs[i].order_hints[j] = frame->order_hints[j]; + av1_dec->frame_refs[i].used = true; + av1_dec->current_frame_index = i; + + return i; + } + + return AV1_INVALID_IDX; +} + +static void rockchip_vpu981_av1_dec_frame_unref(struct hantro_ctx *ctx, int idx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + + if (idx >= 0) + av1_dec->frame_refs[idx].used = false; +} + +static void rockchip_vpu981_av1_dec_clean_refs(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + + int ref, idx; + + for (idx = 0; idx < AV1_MAX_FRAME_BUF_COUNT; idx++) { + u64 timestamp = av1_dec->frame_refs[idx].timestamp; + bool used = false; + + if (!av1_dec->frame_refs[idx].used) + continue; + + for (ref = 0; ref < V4L2_AV1_TOTAL_REFS_PER_FRAME; ref++) { + if (ctrls->frame->reference_frame_ts[ref] == timestamp) + used = true; + } + + if (!used) + rockchip_vpu981_av1_dec_frame_unref(ctx, idx); + } +} + +static size_t rockchip_vpu981_av1_dec_luma_size(struct hantro_ctx *ctx) +{ + return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8; +} + +static size_t rockchip_vpu981_av1_dec_chroma_size(struct hantro_ctx *ctx) +{ + size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx); + + return ALIGN((cr_offset * 3) / 2, 64); +} + +static void rockchip_vpu981_av1_dec_tiles_free(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + + if (av1_dec->db_data_col.cpu) + dma_free_coherent(vpu->dev, av1_dec->db_data_col.size, + av1_dec->db_data_col.cpu, + av1_dec->db_data_col.dma); + av1_dec->db_data_col.cpu = NULL; + + if (av1_dec->db_ctrl_col.cpu) + dma_free_coherent(vpu->dev, av1_dec->db_ctrl_col.size, + av1_dec->db_ctrl_col.cpu, + av1_dec->db_ctrl_col.dma); + av1_dec->db_ctrl_col.cpu = NULL; + + if (av1_dec->cdef_col.cpu) + dma_free_coherent(vpu->dev, av1_dec->cdef_col.size, + av1_dec->cdef_col.cpu, av1_dec->cdef_col.dma); + av1_dec->cdef_col.cpu = NULL; + + if (av1_dec->sr_col.cpu) + dma_free_coherent(vpu->dev, av1_dec->sr_col.size, + av1_dec->sr_col.cpu, av1_dec->sr_col.dma); + av1_dec->sr_col.cpu = NULL; + + if (av1_dec->lr_col.cpu) + dma_free_coherent(vpu->dev, av1_dec->lr_col.size, + av1_dec->lr_col.cpu, av1_dec->lr_col.dma); + av1_dec->lr_col.cpu = NULL; +} + +static int rockchip_vpu981_av1_dec_tiles_reallocate(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + unsigned int num_tile_cols = 1 << ctrls->tile_group_entry->tile_col; + unsigned int height = ALIGN(ctrls->frame->frame_height_minus_1 + 1, 64); + unsigned int height_in_sb = height / 64; + unsigned int stripe_num = ((height + 8) + 63) / 64; + size_t size; + + if (av1_dec->db_data_col.size >= + ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols) + return 0; + + rockchip_vpu981_av1_dec_tiles_free(ctx); + + size = ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols; + av1_dec->db_data_col.cpu = dma_alloc_coherent(vpu->dev, size, + &av1_dec->db_data_col.dma, + GFP_KERNEL); + if (!av1_dec->db_data_col.cpu) + goto buffer_allocation_error; + av1_dec->db_data_col.size = size; + + size = ALIGN(height * 2 * 16 / 4, 128) * num_tile_cols; + av1_dec->db_ctrl_col.cpu = dma_alloc_coherent(vpu->dev, size, + &av1_dec->db_ctrl_col.dma, + GFP_KERNEL); + if (!av1_dec->db_ctrl_col.cpu) + goto buffer_allocation_error; + av1_dec->db_ctrl_col.size = size; + + size = ALIGN(height_in_sb * 44 * ctx->bit_depth * 16 / 8, 128) * num_tile_cols; + av1_dec->cdef_col.cpu = dma_alloc_coherent(vpu->dev, size, + &av1_dec->cdef_col.dma, + GFP_KERNEL); + if (!av1_dec->cdef_col.cpu) + goto buffer_allocation_error; + av1_dec->cdef_col.size = size; + + size = ALIGN(height_in_sb * (3040 + 1280), 128) * num_tile_cols; + av1_dec->sr_col.cpu = dma_alloc_coherent(vpu->dev, size, + &av1_dec->sr_col.dma, + GFP_KERNEL); + if (!av1_dec->sr_col.cpu) + goto buffer_allocation_error; + av1_dec->sr_col.size = size; + + size = ALIGN(stripe_num * 1536 * ctx->bit_depth / 8, 128) * num_tile_cols; + av1_dec->lr_col.cpu = dma_alloc_coherent(vpu->dev, size, + &av1_dec->lr_col.dma, + GFP_KERNEL); + if (!av1_dec->lr_col.cpu) + goto buffer_allocation_error; + av1_dec->lr_col.size = size; + + av1_dec->num_tile_cols_allocated = num_tile_cols; + return 0; + +buffer_allocation_error: + rockchip_vpu981_av1_dec_tiles_free(ctx); + return -ENOMEM; +} + +void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + + if (av1_dec->global_model.cpu) + dma_free_coherent(vpu->dev, av1_dec->global_model.size, + av1_dec->global_model.cpu, + av1_dec->global_model.dma); + av1_dec->global_model.cpu = NULL; + + if (av1_dec->tile_info.cpu) + dma_free_coherent(vpu->dev, av1_dec->tile_info.size, + av1_dec->tile_info.cpu, + av1_dec->tile_info.dma); + av1_dec->tile_info.cpu = NULL; + + if (av1_dec->film_grain.cpu) + dma_free_coherent(vpu->dev, av1_dec->film_grain.size, + av1_dec->film_grain.cpu, + av1_dec->film_grain.dma); + av1_dec->film_grain.cpu = NULL; + + if (av1_dec->prob_tbl.cpu) + dma_free_coherent(vpu->dev, av1_dec->prob_tbl.size, + av1_dec->prob_tbl.cpu, av1_dec->prob_tbl.dma); + av1_dec->prob_tbl.cpu = NULL; + + if (av1_dec->prob_tbl_out.cpu) + dma_free_coherent(vpu->dev, av1_dec->prob_tbl_out.size, + av1_dec->prob_tbl_out.cpu, + av1_dec->prob_tbl_out.dma); + av1_dec->prob_tbl_out.cpu = NULL; + + if (av1_dec->tile_buf.cpu) + dma_free_coherent(vpu->dev, av1_dec->tile_buf.size, + av1_dec->tile_buf.cpu, av1_dec->tile_buf.dma); + av1_dec->tile_buf.cpu = NULL; + + rockchip_vpu981_av1_dec_tiles_free(ctx); +} + +int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + + memset(av1_dec, 0, sizeof(*av1_dec)); + + av1_dec->global_model.cpu = dma_alloc_coherent(vpu->dev, GLOBAL_MODEL_SIZE, + &av1_dec->global_model.dma, + GFP_KERNEL); + if (!av1_dec->global_model.cpu) + return -ENOMEM; + av1_dec->global_model.size = GLOBAL_MODEL_SIZE; + + av1_dec->tile_info.cpu = dma_alloc_coherent(vpu->dev, AV1_MAX_TILES, + &av1_dec->tile_info.dma, + GFP_KERNEL); + if (!av1_dec->tile_info.cpu) + return -ENOMEM; + av1_dec->tile_info.size = AV1_MAX_TILES; + + av1_dec->film_grain.cpu = dma_alloc_coherent(vpu->dev, + ALIGN(sizeof(struct rockchip_av1_film_grain), 2048), + &av1_dec->film_grain.dma, + GFP_KERNEL); + if (!av1_dec->film_grain.cpu) + return -ENOMEM; + av1_dec->film_grain.size = ALIGN(sizeof(struct rockchip_av1_film_grain), 2048); + + av1_dec->prob_tbl.cpu = dma_alloc_coherent(vpu->dev, + ALIGN(sizeof(struct av1cdfs), 2048), + &av1_dec->prob_tbl.dma, + GFP_KERNEL); + if (!av1_dec->prob_tbl.cpu) + return -ENOMEM; + av1_dec->prob_tbl.size = ALIGN(sizeof(struct av1cdfs), 2048); + + av1_dec->prob_tbl_out.cpu = dma_alloc_coherent(vpu->dev, + ALIGN(sizeof(struct av1cdfs), 2048), + &av1_dec->prob_tbl_out.dma, + GFP_KERNEL); + if (!av1_dec->prob_tbl_out.cpu) + return -ENOMEM; + av1_dec->prob_tbl_out.size = ALIGN(sizeof(struct av1cdfs), 2048); + av1_dec->cdfs = &av1_dec->default_cdfs; + av1_dec->cdfs_ndvc = &av1_dec->default_cdfs_ndvc; + + rockchip_av1_set_default_cdfs(av1_dec->cdfs, av1_dec->cdfs_ndvc); + + av1_dec->tile_buf.cpu = dma_alloc_coherent(vpu->dev, + AV1_TILE_SIZE, + &av1_dec->tile_buf.dma, + GFP_KERNEL); + if (!av1_dec->tile_buf.cpu) + return -ENOMEM; + av1_dec->tile_buf.size = AV1_TILE_SIZE; + + return 0; +} + +static int rockchip_vpu981_av1_dec_prepare_run(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + + ctrls->sequence = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_SEQUENCE); + if (WARN_ON(!ctrls->sequence)) + return -EINVAL; + + ctrls->tile_group_entry = + hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY); + if (WARN_ON(!ctrls->tile_group_entry)) + return -EINVAL; + + ctrls->frame = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_FRAME); + if (WARN_ON(!ctrls->frame)) + return -EINVAL; + + ctrls->film_grain = + hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_FILM_GRAIN); + + return rockchip_vpu981_av1_dec_tiles_reallocate(ctx); +} + +static inline int rockchip_vpu981_av1_dec_get_msb(u32 n) +{ + if (n == 0) + return 0; + return 31 ^ __builtin_clz(n); +} + +static short rockchip_vpu981_av1_dec_resolve_divisor_32(u32 d, short *shift) +{ + int f; + u64 e; + + *shift = rockchip_vpu981_av1_dec_get_msb(d); + /* e is obtained from D after resetting the most significant 1 bit. */ + e = d - ((u32)1 << *shift); + /* Get the most significant DIV_LUT_BITS (8) bits of e into f */ + if (*shift > DIV_LUT_BITS) + f = AV1_DIV_ROUND_UP_POW2(e, *shift - DIV_LUT_BITS); + else + f = e << (DIV_LUT_BITS - *shift); + if (f > DIV_LUT_NUM) + return -1; + *shift += DIV_LUT_PREC_BITS; + /* Use f as lookup into the precomputed table of multipliers */ + return div_lut[f]; +} + +static void +rockchip_vpu981_av1_dec_get_shear_params(const u32 *params, s64 *alpha, + s64 *beta, s64 *gamma, s64 *delta) +{ + const int *mat = params; + short shift; + short y; + long long gv, dv; + + if (mat[2] <= 0) + return; + + *alpha = clamp_val(mat[2] - (1 << WARPEDMODEL_PREC_BITS), S16_MIN, S16_MAX); + *beta = clamp_val(mat[3], S16_MIN, S16_MAX); + + y = rockchip_vpu981_av1_dec_resolve_divisor_32(abs(mat[2]), &shift) * (mat[2] < 0 ? -1 : 1); + + gv = ((long long)mat[4] * (1 << WARPEDMODEL_PREC_BITS)) * y; + + *gamma = clamp_val((int)AV1_DIV_ROUND_UP_POW2_SIGNED(gv, shift), S16_MIN, S16_MAX); + + dv = ((long long)mat[3] * mat[4]) * y; + *delta = clamp_val(mat[5] - + (int)AV1_DIV_ROUND_UP_POW2_SIGNED(dv, shift) - (1 << WARPEDMODEL_PREC_BITS), + S16_MIN, S16_MAX); + + *alpha = AV1_DIV_ROUND_UP_POW2_SIGNED(*alpha, WARP_PARAM_REDUCE_BITS) + * (1 << WARP_PARAM_REDUCE_BITS); + *beta = AV1_DIV_ROUND_UP_POW2_SIGNED(*beta, WARP_PARAM_REDUCE_BITS) + * (1 << WARP_PARAM_REDUCE_BITS); + *gamma = AV1_DIV_ROUND_UP_POW2_SIGNED(*gamma, WARP_PARAM_REDUCE_BITS) + * (1 << WARP_PARAM_REDUCE_BITS); + *delta = AV1_DIV_ROUND_UP_POW2_SIGNED(*delta, WARP_PARAM_REDUCE_BITS) + * (1 << WARP_PARAM_REDUCE_BITS); +} + +static void rockchip_vpu981_av1_dec_set_global_model(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + const struct v4l2_av1_global_motion *gm = &frame->global_motion; + u8 *dst = av1_dec->global_model.cpu; + struct hantro_dev *vpu = ctx->dev; + int ref_frame, i; + + memset(dst, 0, GLOBAL_MODEL_SIZE); + for (ref_frame = 0; ref_frame < V4L2_AV1_REFS_PER_FRAME; ++ref_frame) { + s64 alpha = 0, beta = 0, gamma = 0, delta = 0; + + for (i = 0; i < 6; ++i) { + if (i == 2) + *(s32 *)dst = + gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][3]; + else if (i == 3) + *(s32 *)dst = + gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][2]; + else + *(s32 *)dst = + gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][i]; + dst += 4; + } + + if (gm->type[V4L2_AV1_REF_LAST_FRAME + ref_frame] <= V4L2_AV1_WARP_MODEL_AFFINE) + rockchip_vpu981_av1_dec_get_shear_params(&gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][0], + &alpha, &beta, &gamma, &delta); + + *(s16 *)dst = alpha; + dst += 2; + *(s16 *)dst = beta; + dst += 2; + *(s16 *)dst = gamma; + dst += 2; + *(s16 *)dst = delta; + dst += 2; + } + + hantro_write_addr(vpu, AV1_GLOBAL_MODEL, av1_dec->global_model.dma); +} + +static int rockchip_vpu981_av1_tile_log2(int target) +{ + int k; + + /* + * returns the smallest value for k such that 1 << k is greater + * than or equal to target + */ + for (k = 0; (1 << k) < target; k++); + + return k; +} + +static void rockchip_vpu981_av1_dec_set_tile_info(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info; + const struct v4l2_ctrl_av1_tile_group_entry *group_entry = + ctrls->tile_group_entry; + int context_update_y = + tile_info->context_update_tile_id / tile_info->tile_cols; + int context_update_x = + tile_info->context_update_tile_id % tile_info->tile_cols; + int context_update_tile_id = + context_update_x * tile_info->tile_rows + context_update_y; + u8 *dst = av1_dec->tile_info.cpu; + struct hantro_dev *vpu = ctx->dev; + int tile0, tile1; + + memset(dst, 0, av1_dec->tile_info.size); + + for (tile0 = 0; tile0 < tile_info->tile_cols; tile0++) { + for (tile1 = 0; tile1 < tile_info->tile_rows; tile1++) { + int tile_id = tile1 * tile_info->tile_cols + tile0; + u32 start, end; + u32 y0 = + tile_info->height_in_sbs_minus_1[tile1] + 1; + u32 x0 = tile_info->width_in_sbs_minus_1[tile0] + 1; + + /* tile size in SB units (width,height) */ + *dst++ = x0; + *dst++ = 0; + *dst++ = 0; + *dst++ = 0; + *dst++ = y0; + *dst++ = 0; + *dst++ = 0; + *dst++ = 0; + + /* tile start position */ + start = group_entry[tile_id].tile_offset - group_entry[0].tile_offset; + *dst++ = start & 255; + *dst++ = (start >> 8) & 255; + *dst++ = (start >> 16) & 255; + *dst++ = (start >> 24) & 255; + + /* number of bytes in tile data */ + end = start + group_entry[tile_id].tile_size; + *dst++ = end & 255; + *dst++ = (end >> 8) & 255; + *dst++ = (end >> 16) & 255; + *dst++ = (end >> 24) & 255; + } + } + + hantro_reg_write(vpu, &av1_multicore_expect_context_update, !!(context_update_x == 0)); + hantro_reg_write(vpu, &av1_tile_enable, + !!((tile_info->tile_cols > 1) || (tile_info->tile_rows > 1))); + hantro_reg_write(vpu, &av1_num_tile_cols_8k, tile_info->tile_cols); + hantro_reg_write(vpu, &av1_num_tile_rows_8k, tile_info->tile_rows); + hantro_reg_write(vpu, &av1_context_update_tile_id, context_update_tile_id); + hantro_reg_write(vpu, &av1_tile_transpose, 1); + if (rockchip_vpu981_av1_tile_log2(tile_info->tile_cols) || + rockchip_vpu981_av1_tile_log2(tile_info->tile_rows)) + hantro_reg_write(vpu, &av1_dec_tile_size_mag, tile_info->tile_size_bytes - 1); + else + hantro_reg_write(vpu, &av1_dec_tile_size_mag, 3); + + hantro_write_addr(vpu, AV1_TILE_BASE, av1_dec->tile_info.dma); +} + +static int rockchip_vpu981_av1_dec_get_dist(struct hantro_ctx *ctx, + int a, int b) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + int bits = ctrls->sequence->order_hint_bits - 1; + int diff, m; + + if (!ctrls->sequence->order_hint_bits) + return 0; + + diff = a - b; + m = 1 << bits; + diff = (diff & (m - 1)) - (diff & m); + + return diff; +} + +static void rockchip_vpu981_av1_dec_set_frame_sign_bias(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + const struct v4l2_ctrl_av1_sequence *sequence = ctrls->sequence; + int i; + + if (!sequence->order_hint_bits || IS_INTRA(frame->frame_type)) { + for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) + av1_dec->ref_frame_sign_bias[i] = 0; + + return; + } + // Identify the nearest forward and backward references. + for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME - 1; i++) { + if (rockchip_vpu981_get_frame_index(ctx, i) >= 0) { + int rel_off = + rockchip_vpu981_av1_dec_get_dist(ctx, + rockchip_vpu981_get_order_hint(ctx, i), + frame->order_hint); + av1_dec->ref_frame_sign_bias[i + 1] = (rel_off <= 0) ? 0 : 1; + } + } +} + +static bool +rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx, + int width, int height) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + struct hantro_dev *vpu = ctx->dev; + struct hantro_decoded_buffer *dst; + dma_addr_t luma_addr, chroma_addr, mv_addr = 0; + size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx); + size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx); + int cur_width = frame->frame_width_minus_1 + 1; + int cur_height = frame->frame_height_minus_1 + 1; + int scale_width = + ((width << AV1_REF_SCALE_SHIFT) + cur_width / 2) / cur_width; + int scale_height = + ((height << AV1_REF_SCALE_SHIFT) + cur_height / 2) / cur_height; + + switch (ref) { + case 0: + hantro_reg_write(vpu, &av1_ref0_height, height); + hantro_reg_write(vpu, &av1_ref0_width, width); + hantro_reg_write(vpu, &av1_ref0_ver_scale, scale_width); + hantro_reg_write(vpu, &av1_ref0_hor_scale, scale_height); + break; + case 1: + hantro_reg_write(vpu, &av1_ref1_height, height); + hantro_reg_write(vpu, &av1_ref1_width, width); + hantro_reg_write(vpu, &av1_ref1_ver_scale, scale_width); + hantro_reg_write(vpu, &av1_ref1_hor_scale, scale_height); + break; + case 2: + hantro_reg_write(vpu, &av1_ref2_height, height); + hantro_reg_write(vpu, &av1_ref2_width, width); + hantro_reg_write(vpu, &av1_ref2_ver_scale, scale_width); + hantro_reg_write(vpu, &av1_ref2_hor_scale, scale_height); + break; + case 3: + hantro_reg_write(vpu, &av1_ref3_height, height); + hantro_reg_write(vpu, &av1_ref3_width, width); + hantro_reg_write(vpu, &av1_ref3_ver_scale, scale_width); + hantro_reg_write(vpu, &av1_ref3_hor_scale, scale_height); + break; + case 4: + hantro_reg_write(vpu, &av1_ref4_height, height); + hantro_reg_write(vpu, &av1_ref4_width, width); + hantro_reg_write(vpu, &av1_ref4_ver_scale, scale_width); + hantro_reg_write(vpu, &av1_ref4_hor_scale, scale_height); + break; + case 5: + hantro_reg_write(vpu, &av1_ref5_height, height); + hantro_reg_write(vpu, &av1_ref5_width, width); + hantro_reg_write(vpu, &av1_ref5_ver_scale, scale_width); + hantro_reg_write(vpu, &av1_ref5_hor_scale, scale_height); + break; + case 6: + hantro_reg_write(vpu, &av1_ref6_height, height); + hantro_reg_write(vpu, &av1_ref6_width, width); + hantro_reg_write(vpu, &av1_ref6_ver_scale, scale_width); + hantro_reg_write(vpu, &av1_ref6_hor_scale, scale_height); + break; + default: + pr_warn("AV1 invalid reference frame index\n"); + } + + dst = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf); + luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); + chroma_addr = luma_addr + cr_offset; + mv_addr = luma_addr + mv_offset; + + hantro_write_addr(vpu, AV1_REFERENCE_Y(ref), luma_addr); + hantro_write_addr(vpu, AV1_REFERENCE_CB(ref), chroma_addr); + hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), mv_addr); + + return (scale_width != (1 << AV1_REF_SCALE_SHIFT)) || + (scale_height != (1 << AV1_REF_SCALE_SHIFT)); +} + +static void rockchip_vpu981_av1_dec_set_sign_bias(struct hantro_ctx *ctx, + int ref, int val) +{ + struct hantro_dev *vpu = ctx->dev; + + switch (ref) { + case 0: + hantro_reg_write(vpu, &av1_ref0_sign_bias, val); + break; + case 1: + hantro_reg_write(vpu, &av1_ref1_sign_bias, val); + break; + case 2: + hantro_reg_write(vpu, &av1_ref2_sign_bias, val); + break; + case 3: + hantro_reg_write(vpu, &av1_ref3_sign_bias, val); + break; + case 4: + hantro_reg_write(vpu, &av1_ref4_sign_bias, val); + break; + case 5: + hantro_reg_write(vpu, &av1_ref5_sign_bias, val); + break; + case 6: + hantro_reg_write(vpu, &av1_ref6_sign_bias, val); + break; + default: + pr_warn("AV1 invalid sign bias index\n"); + break; + } +} + +static void rockchip_vpu981_av1_dec_set_segmentation(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + const struct v4l2_av1_segmentation *seg = &frame->segmentation; + u32 segval[V4L2_AV1_MAX_SEGMENTS][V4L2_AV1_SEG_LVL_MAX] = { 0 }; + struct hantro_dev *vpu = ctx->dev; + u8 segsign = 0, preskip_segid = 0, last_active_seg = 0, i, j; + + if (!!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED) && + frame->primary_ref_frame < V4L2_AV1_REFS_PER_FRAME) { + int idx = rockchip_vpu981_get_frame_index(ctx, frame->primary_ref_frame); + + if (idx >= 0) { + dma_addr_t luma_addr, mv_addr = 0; + struct hantro_decoded_buffer *seg; + size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx); + + seg = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf); + luma_addr = hantro_get_dec_buf_addr(ctx, &seg->base.vb.vb2_buf); + mv_addr = luma_addr + mv_offset; + + hantro_write_addr(vpu, AV1_SEGMENTATION, mv_addr); + hantro_reg_write(vpu, &av1_use_temporal3_mvs, 1); + } + } + + hantro_reg_write(vpu, &av1_segment_temp_upd_e, + !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_TEMPORAL_UPDATE)); + hantro_reg_write(vpu, &av1_segment_upd_e, + !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_UPDATE_MAP)); + hantro_reg_write(vpu, &av1_segment_e, + !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED)); + + hantro_reg_write(vpu, &av1_error_resilient, + !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE)); + + if (IS_INTRA(frame->frame_type) || + !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE)) { + hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0); + } + + if (seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED) { + int s; + + for (s = 0; s < V4L2_AV1_MAX_SEGMENTS; s++) { + if (seg->feature_enabled[s] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_Q)) { + segval[s][V4L2_AV1_SEG_LVL_ALT_Q] = + clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_Q]), + 0, 255); + segsign |= + (seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_Q] < 0) << s; + } + + if (seg->feature_enabled[s] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_Y_V)) + segval[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_V] = + clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]), + -63, 63); + + if (seg->feature_enabled[s] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_Y_H)) + segval[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_H] = + clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]), + -63, 63); + + if (seg->feature_enabled[s] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_U)) + segval[s][V4L2_AV1_SEG_LVL_ALT_LF_U] = + clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_U]), + -63, 63); + + if (seg->feature_enabled[s] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_V)) + segval[s][V4L2_AV1_SEG_LVL_ALT_LF_V] = + clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_V]), + -63, 63); + + if (frame->frame_type && seg->feature_enabled[s] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_FRAME)) + segval[s][V4L2_AV1_SEG_LVL_REF_FRAME]++; + + if (seg->feature_enabled[s] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_SKIP)) + segval[s][V4L2_AV1_SEG_LVL_REF_SKIP] = 1; + + if (seg->feature_enabled[s] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_GLOBALMV)) + segval[s][V4L2_AV1_SEG_LVL_REF_GLOBALMV] = 1; + } + } + + for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) { + for (j = 0; j < V4L2_AV1_SEG_LVL_MAX; j++) { + if (seg->feature_enabled[i] + & V4L2_AV1_SEGMENT_FEATURE_ENABLED(j)) { + preskip_segid |= (j >= V4L2_AV1_SEG_LVL_REF_FRAME); + last_active_seg = max(i, last_active_seg); + } + } + } + + hantro_reg_write(vpu, &av1_last_active_seg, last_active_seg); + hantro_reg_write(vpu, &av1_preskip_segid, preskip_segid); + + hantro_reg_write(vpu, &av1_seg_quant_sign, segsign); + + /* Write QP, filter level, ref frame and skip for every segment */ + hantro_reg_write(vpu, &av1_quant_seg0, + segval[0][V4L2_AV1_SEG_LVL_ALT_Q]); + hantro_reg_write(vpu, &av1_filt_level_delta0_seg0, + segval[0][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); + hantro_reg_write(vpu, &av1_filt_level_delta1_seg0, + segval[0][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); + hantro_reg_write(vpu, &av1_filt_level_delta2_seg0, + segval[0][V4L2_AV1_SEG_LVL_ALT_LF_U]); + hantro_reg_write(vpu, &av1_filt_level_delta3_seg0, + segval[0][V4L2_AV1_SEG_LVL_ALT_LF_V]); + hantro_reg_write(vpu, &av1_refpic_seg0, + segval[0][V4L2_AV1_SEG_LVL_REF_FRAME]); + hantro_reg_write(vpu, &av1_skip_seg0, + segval[0][V4L2_AV1_SEG_LVL_REF_SKIP]); + hantro_reg_write(vpu, &av1_global_mv_seg0, + segval[0][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); + + hantro_reg_write(vpu, &av1_quant_seg1, + segval[1][V4L2_AV1_SEG_LVL_ALT_Q]); + hantro_reg_write(vpu, &av1_filt_level_delta0_seg1, + segval[1][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); + hantro_reg_write(vpu, &av1_filt_level_delta1_seg1, + segval[1][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); + hantro_reg_write(vpu, &av1_filt_level_delta2_seg1, + segval[1][V4L2_AV1_SEG_LVL_ALT_LF_U]); + hantro_reg_write(vpu, &av1_filt_level_delta3_seg1, + segval[1][V4L2_AV1_SEG_LVL_ALT_LF_V]); + hantro_reg_write(vpu, &av1_refpic_seg1, + segval[1][V4L2_AV1_SEG_LVL_REF_FRAME]); + hantro_reg_write(vpu, &av1_skip_seg1, + segval[1][V4L2_AV1_SEG_LVL_REF_SKIP]); + hantro_reg_write(vpu, &av1_global_mv_seg1, + segval[1][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); + + hantro_reg_write(vpu, &av1_quant_seg2, + segval[2][V4L2_AV1_SEG_LVL_ALT_Q]); + hantro_reg_write(vpu, &av1_filt_level_delta0_seg2, + segval[2][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); + hantro_reg_write(vpu, &av1_filt_level_delta1_seg2, + segval[2][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); + hantro_reg_write(vpu, &av1_filt_level_delta2_seg2, + segval[2][V4L2_AV1_SEG_LVL_ALT_LF_U]); + hantro_reg_write(vpu, &av1_filt_level_delta3_seg2, + segval[2][V4L2_AV1_SEG_LVL_ALT_LF_V]); + hantro_reg_write(vpu, &av1_refpic_seg2, + segval[2][V4L2_AV1_SEG_LVL_REF_FRAME]); + hantro_reg_write(vpu, &av1_skip_seg2, + segval[2][V4L2_AV1_SEG_LVL_REF_SKIP]); + hantro_reg_write(vpu, &av1_global_mv_seg2, + segval[2][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); + + hantro_reg_write(vpu, &av1_quant_seg3, + segval[3][V4L2_AV1_SEG_LVL_ALT_Q]); + hantro_reg_write(vpu, &av1_filt_level_delta0_seg3, + segval[3][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); + hantro_reg_write(vpu, &av1_filt_level_delta1_seg3, + segval[3][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); + hantro_reg_write(vpu, &av1_filt_level_delta2_seg3, + segval[3][V4L2_AV1_SEG_LVL_ALT_LF_U]); + hantro_reg_write(vpu, &av1_filt_level_delta3_seg3, + segval[3][V4L2_AV1_SEG_LVL_ALT_LF_V]); + hantro_reg_write(vpu, &av1_refpic_seg3, + segval[3][V4L2_AV1_SEG_LVL_REF_FRAME]); + hantro_reg_write(vpu, &av1_skip_seg3, + segval[3][V4L2_AV1_SEG_LVL_REF_SKIP]); + hantro_reg_write(vpu, &av1_global_mv_seg3, + segval[3][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); + + hantro_reg_write(vpu, &av1_quant_seg4, + segval[4][V4L2_AV1_SEG_LVL_ALT_Q]); + hantro_reg_write(vpu, &av1_filt_level_delta0_seg4, + segval[4][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); + hantro_reg_write(vpu, &av1_filt_level_delta1_seg4, + segval[4][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); + hantro_reg_write(vpu, &av1_filt_level_delta2_seg4, + segval[4][V4L2_AV1_SEG_LVL_ALT_LF_U]); + hantro_reg_write(vpu, &av1_filt_level_delta3_seg4, + segval[4][V4L2_AV1_SEG_LVL_ALT_LF_V]); + hantro_reg_write(vpu, &av1_refpic_seg4, + segval[4][V4L2_AV1_SEG_LVL_REF_FRAME]); + hantro_reg_write(vpu, &av1_skip_seg4, + segval[4][V4L2_AV1_SEG_LVL_REF_SKIP]); + hantro_reg_write(vpu, &av1_global_mv_seg4, + segval[4][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); + + hantro_reg_write(vpu, &av1_quant_seg5, + segval[5][V4L2_AV1_SEG_LVL_ALT_Q]); + hantro_reg_write(vpu, &av1_filt_level_delta0_seg5, + segval[5][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); + hantro_reg_write(vpu, &av1_filt_level_delta1_seg5, + segval[5][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); + hantro_reg_write(vpu, &av1_filt_level_delta2_seg5, + segval[5][V4L2_AV1_SEG_LVL_ALT_LF_U]); + hantro_reg_write(vpu, &av1_filt_level_delta3_seg5, + segval[5][V4L2_AV1_SEG_LVL_ALT_LF_V]); + hantro_reg_write(vpu, &av1_refpic_seg5, + segval[5][V4L2_AV1_SEG_LVL_REF_FRAME]); + hantro_reg_write(vpu, &av1_skip_seg5, + segval[5][V4L2_AV1_SEG_LVL_REF_SKIP]); + hantro_reg_write(vpu, &av1_global_mv_seg5, + segval[5][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); + + hantro_reg_write(vpu, &av1_quant_seg6, + segval[6][V4L2_AV1_SEG_LVL_ALT_Q]); + hantro_reg_write(vpu, &av1_filt_level_delta0_seg6, + segval[6][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); + hantro_reg_write(vpu, &av1_filt_level_delta1_seg6, + segval[6][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); + hantro_reg_write(vpu, &av1_filt_level_delta2_seg6, + segval[6][V4L2_AV1_SEG_LVL_ALT_LF_U]); + hantro_reg_write(vpu, &av1_filt_level_delta3_seg6, + segval[6][V4L2_AV1_SEG_LVL_ALT_LF_V]); + hantro_reg_write(vpu, &av1_refpic_seg6, + segval[6][V4L2_AV1_SEG_LVL_REF_FRAME]); + hantro_reg_write(vpu, &av1_skip_seg6, + segval[6][V4L2_AV1_SEG_LVL_REF_SKIP]); + hantro_reg_write(vpu, &av1_global_mv_seg6, + segval[6][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); + + hantro_reg_write(vpu, &av1_quant_seg7, + segval[7][V4L2_AV1_SEG_LVL_ALT_Q]); + hantro_reg_write(vpu, &av1_filt_level_delta0_seg7, + segval[7][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); + hantro_reg_write(vpu, &av1_filt_level_delta1_seg7, + segval[7][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); + hantro_reg_write(vpu, &av1_filt_level_delta2_seg7, + segval[7][V4L2_AV1_SEG_LVL_ALT_LF_U]); + hantro_reg_write(vpu, &av1_filt_level_delta3_seg7, + segval[7][V4L2_AV1_SEG_LVL_ALT_LF_V]); + hantro_reg_write(vpu, &av1_refpic_seg7, + segval[7][V4L2_AV1_SEG_LVL_REF_FRAME]); + hantro_reg_write(vpu, &av1_skip_seg7, + segval[7][V4L2_AV1_SEG_LVL_REF_SKIP]); + hantro_reg_write(vpu, &av1_global_mv_seg7, + segval[7][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); +} + +static bool rockchip_vpu981_av1_dec_is_lossless(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + const struct v4l2_av1_segmentation *segmentation = &frame->segmentation; + const struct v4l2_av1_quantization *quantization = &frame->quantization; + int i; + + for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) { + int qindex = quantization->base_q_idx; + + if (segmentation->feature_enabled[i] & + V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_Q)) { + qindex += segmentation->feature_data[i][V4L2_AV1_SEG_LVL_ALT_Q]; + } + qindex = clamp(qindex, 0, 255); + + if (qindex || + quantization->delta_q_y_dc || + quantization->delta_q_u_dc || + quantization->delta_q_u_ac || + quantization->delta_q_v_dc || + quantization->delta_q_v_ac) + return false; + } + return true; +} + +static void rockchip_vpu981_av1_dec_set_loopfilter(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + const struct v4l2_av1_loop_filter *loop_filter = &frame->loop_filter; + bool filtering_dis = (loop_filter->level[0] == 0) && (loop_filter->level[1] == 0); + struct hantro_dev *vpu = ctx->dev; + + hantro_reg_write(vpu, &av1_filtering_dis, filtering_dis); + hantro_reg_write(vpu, &av1_filt_level_base_gt32, loop_filter->level[0] > 32); + hantro_reg_write(vpu, &av1_filt_sharpness, loop_filter->sharpness); + + hantro_reg_write(vpu, &av1_filt_level0, loop_filter->level[0]); + hantro_reg_write(vpu, &av1_filt_level1, loop_filter->level[1]); + hantro_reg_write(vpu, &av1_filt_level2, loop_filter->level[2]); + hantro_reg_write(vpu, &av1_filt_level3, loop_filter->level[3]); + + if (loop_filter->flags & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_ENABLED && + !rockchip_vpu981_av1_dec_is_lossless(ctx) && + !(frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC)) { + hantro_reg_write(vpu, &av1_filt_ref_adj_0, + loop_filter->ref_deltas[0]); + hantro_reg_write(vpu, &av1_filt_ref_adj_1, + loop_filter->ref_deltas[1]); + hantro_reg_write(vpu, &av1_filt_ref_adj_2, + loop_filter->ref_deltas[2]); + hantro_reg_write(vpu, &av1_filt_ref_adj_3, + loop_filter->ref_deltas[3]); + hantro_reg_write(vpu, &av1_filt_ref_adj_4, + loop_filter->ref_deltas[4]); + hantro_reg_write(vpu, &av1_filt_ref_adj_5, + loop_filter->ref_deltas[5]); + hantro_reg_write(vpu, &av1_filt_ref_adj_6, + loop_filter->ref_deltas[6]); + hantro_reg_write(vpu, &av1_filt_ref_adj_7, + loop_filter->ref_deltas[7]); + hantro_reg_write(vpu, &av1_filt_mb_adj_0, + loop_filter->mode_deltas[0]); + hantro_reg_write(vpu, &av1_filt_mb_adj_1, + loop_filter->mode_deltas[1]); + } else { + hantro_reg_write(vpu, &av1_filt_ref_adj_0, 0); + hantro_reg_write(vpu, &av1_filt_ref_adj_1, 0); + hantro_reg_write(vpu, &av1_filt_ref_adj_2, 0); + hantro_reg_write(vpu, &av1_filt_ref_adj_3, 0); + hantro_reg_write(vpu, &av1_filt_ref_adj_4, 0); + hantro_reg_write(vpu, &av1_filt_ref_adj_5, 0); + hantro_reg_write(vpu, &av1_filt_ref_adj_6, 0); + hantro_reg_write(vpu, &av1_filt_ref_adj_7, 0); + hantro_reg_write(vpu, &av1_filt_mb_adj_0, 0); + hantro_reg_write(vpu, &av1_filt_mb_adj_1, 0); + } + + hantro_write_addr(vpu, AV1_DB_DATA_COL, av1_dec->db_data_col.dma); + hantro_write_addr(vpu, AV1_DB_CTRL_COL, av1_dec->db_ctrl_col.dma); +} + +static void rockchip_vpu981_av1_dec_update_prob(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + bool frame_is_intra = IS_INTRA(frame->frame_type); + struct av1cdfs *out_cdfs = (struct av1cdfs *)av1_dec->prob_tbl_out.cpu; + int i; + + if (frame->flags & V4L2_AV1_FRAME_FLAG_DISABLE_FRAME_END_UPDATE_CDF) + return; + + for (i = 0; i < NUM_REF_FRAMES; i++) { + if (frame->refresh_frame_flags & BIT(i)) { + struct mvcdfs stored_mv_cdf; + + rockchip_av1_get_cdfs(ctx, i); + stored_mv_cdf = av1_dec->cdfs->mv_cdf; + *av1_dec->cdfs = *out_cdfs; + if (frame_is_intra) { + av1_dec->cdfs->mv_cdf = stored_mv_cdf; + *av1_dec->cdfs_ndvc = out_cdfs->mv_cdf; + } + rockchip_av1_store_cdfs(ctx, + frame->refresh_frame_flags); + break; + } + } +} + +void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx) +{ + rockchip_vpu981_av1_dec_update_prob(ctx); +} + +static void rockchip_vpu981_av1_dec_set_prob(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + const struct v4l2_av1_quantization *quantization = &frame->quantization; + struct hantro_dev *vpu = ctx->dev; + bool error_resilient_mode = + !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE); + bool frame_is_intra = IS_INTRA(frame->frame_type); + + if (error_resilient_mode || frame_is_intra || + frame->primary_ref_frame == AV1_PRIMARY_REF_NONE) { + av1_dec->cdfs = &av1_dec->default_cdfs; + av1_dec->cdfs_ndvc = &av1_dec->default_cdfs_ndvc; + rockchip_av1_default_coeff_probs(quantization->base_q_idx, + av1_dec->cdfs); + } else { + rockchip_av1_get_cdfs(ctx, frame->ref_frame_idx[frame->primary_ref_frame]); + } + rockchip_av1_store_cdfs(ctx, frame->refresh_frame_flags); + + memcpy(av1_dec->prob_tbl.cpu, av1_dec->cdfs, sizeof(struct av1cdfs)); + + if (frame_is_intra) { + int mv_offset = offsetof(struct av1cdfs, mv_cdf); + /* Overwrite MV context area with intrabc MV context */ + memcpy(av1_dec->prob_tbl.cpu + mv_offset, av1_dec->cdfs_ndvc, + sizeof(struct mvcdfs)); + } + + hantro_write_addr(vpu, AV1_PROP_TABLE_OUT, av1_dec->prob_tbl_out.dma); + hantro_write_addr(vpu, AV1_PROP_TABLE, av1_dec->prob_tbl.dma); +} + +static void +rockchip_vpu981_av1_dec_init_scaling_function(const u8 *values, const u8 *scaling, + u8 num_points, u8 *scaling_lut) +{ + int i, point; + + if (num_points == 0) { + memset(scaling_lut, 0, 256); + return; + } + + for (point = 0; point < num_points - 1; point++) { + int x; + s32 delta_y = scaling[point + 1] - scaling[point]; + s32 delta_x = values[point + 1] - values[point]; + s64 delta = + delta_x ? delta_y * ((65536 + (delta_x >> 1)) / + delta_x) : 0; + + for (x = 0; x < delta_x; x++) { + scaling_lut[values[point] + x] = + scaling[point] + + (s32)((x * delta + 32768) >> 16); + } + } + + for (i = values[num_points - 1]; i < 256; i++) + scaling_lut[i] = scaling[num_points - 1]; +} + +static void rockchip_vpu981_av1_dec_set_fgs(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_film_grain *film_grain = ctrls->film_grain; + struct rockchip_av1_film_grain *fgmem = av1_dec->film_grain.cpu; + struct hantro_dev *vpu = ctx->dev; + bool scaling_from_luma = + !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA); + s32 (*ar_coeffs_y)[24]; + s32 (*ar_coeffs_cb)[25]; + s32 (*ar_coeffs_cr)[25]; + s32 (*luma_grain_block)[73][82]; + s32 (*cb_grain_block)[38][44]; + s32 (*cr_grain_block)[38][44]; + s32 ar_coeff_lag, ar_coeff_shift; + s32 grain_scale_shift, bitdepth; + s32 grain_center, grain_min, grain_max; + int i, j; + + hantro_reg_write(vpu, &av1_apply_grain, 0); + + if (!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_APPLY_GRAIN)) { + hantro_reg_write(vpu, &av1_num_y_points_b, 0); + hantro_reg_write(vpu, &av1_num_cb_points_b, 0); + hantro_reg_write(vpu, &av1_num_cr_points_b, 0); + hantro_reg_write(vpu, &av1_scaling_shift, 0); + hantro_reg_write(vpu, &av1_cb_mult, 0); + hantro_reg_write(vpu, &av1_cb_luma_mult, 0); + hantro_reg_write(vpu, &av1_cb_offset, 0); + hantro_reg_write(vpu, &av1_cr_mult, 0); + hantro_reg_write(vpu, &av1_cr_luma_mult, 0); + hantro_reg_write(vpu, &av1_cr_offset, 0); + hantro_reg_write(vpu, &av1_overlap_flag, 0); + hantro_reg_write(vpu, &av1_clip_to_restricted_range, 0); + hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, 0); + hantro_reg_write(vpu, &av1_random_seed, 0); + hantro_write_addr(vpu, AV1_FILM_GRAIN, 0); + return; + } + + ar_coeffs_y = kzalloc(sizeof(int32_t) * 24, GFP_KERNEL); + ar_coeffs_cb = kzalloc(sizeof(int32_t) * 25, GFP_KERNEL); + ar_coeffs_cr = kzalloc(sizeof(int32_t) * 25, GFP_KERNEL); + luma_grain_block = kzalloc(sizeof(int32_t) * 73 * 82, GFP_KERNEL); + cb_grain_block = kzalloc(sizeof(int32_t) * 38 * 44, GFP_KERNEL); + cr_grain_block = kzalloc(sizeof(int32_t) * 38 * 44, GFP_KERNEL); + + if (!ar_coeffs_y || !ar_coeffs_cb || !ar_coeffs_cr || + !luma_grain_block || !cb_grain_block || !cr_grain_block) { + pr_warn("Fail allocating memory for film grain parameters\n"); + goto alloc_fail; + } + + hantro_reg_write(vpu, &av1_apply_grain, 1); + + hantro_reg_write(vpu, &av1_num_y_points_b, + film_grain->num_y_points > 0); + hantro_reg_write(vpu, &av1_num_cb_points_b, + film_grain->num_cb_points > 0); + hantro_reg_write(vpu, &av1_num_cr_points_b, + film_grain->num_cr_points > 0); + hantro_reg_write(vpu, &av1_scaling_shift, + film_grain->grain_scaling_minus_8 + 8); + + if (!scaling_from_luma) { + hantro_reg_write(vpu, &av1_cb_mult, film_grain->cb_mult - 128); + hantro_reg_write(vpu, &av1_cb_luma_mult, film_grain->cb_luma_mult - 128); + hantro_reg_write(vpu, &av1_cb_offset, film_grain->cb_offset - 256); + hantro_reg_write(vpu, &av1_cr_mult, film_grain->cr_mult - 128); + hantro_reg_write(vpu, &av1_cr_luma_mult, film_grain->cr_luma_mult - 128); + hantro_reg_write(vpu, &av1_cr_offset, film_grain->cr_offset - 256); + } else { + hantro_reg_write(vpu, &av1_cb_mult, 0); + hantro_reg_write(vpu, &av1_cb_luma_mult, 0); + hantro_reg_write(vpu, &av1_cb_offset, 0); + hantro_reg_write(vpu, &av1_cr_mult, 0); + hantro_reg_write(vpu, &av1_cr_luma_mult, 0); + hantro_reg_write(vpu, &av1_cr_offset, 0); + } + + hantro_reg_write(vpu, &av1_overlap_flag, + !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_OVERLAP)); + hantro_reg_write(vpu, &av1_clip_to_restricted_range, + !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_CLIP_TO_RESTRICTED_RANGE)); + hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, scaling_from_luma); + hantro_reg_write(vpu, &av1_random_seed, film_grain->grain_seed); + + rockchip_vpu981_av1_dec_init_scaling_function(film_grain->point_y_value, + film_grain->point_y_scaling, + film_grain->num_y_points, + fgmem->scaling_lut_y); + + if (film_grain->flags & + V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA) { + memcpy(fgmem->scaling_lut_cb, fgmem->scaling_lut_y, + sizeof(*fgmem->scaling_lut_y) * 256); + memcpy(fgmem->scaling_lut_cr, fgmem->scaling_lut_y, + sizeof(*fgmem->scaling_lut_y) * 256); + } else { + rockchip_vpu981_av1_dec_init_scaling_function + (film_grain->point_cb_value, film_grain->point_cb_scaling, + film_grain->num_cb_points, fgmem->scaling_lut_cb); + rockchip_vpu981_av1_dec_init_scaling_function + (film_grain->point_cr_value, film_grain->point_cr_scaling, + film_grain->num_cr_points, fgmem->scaling_lut_cr); + } + + for (i = 0; i < V4L2_AV1_AR_COEFFS_SIZE; i++) { + if (i < 24) + (*ar_coeffs_y)[i] = film_grain->ar_coeffs_y_plus_128[i] - 128; + (*ar_coeffs_cb)[i] = film_grain->ar_coeffs_cb_plus_128[i] - 128; + (*ar_coeffs_cr)[i] = film_grain->ar_coeffs_cr_plus_128[i] - 128; + } + + ar_coeff_lag = film_grain->ar_coeff_lag; + ar_coeff_shift = film_grain->ar_coeff_shift_minus_6 + 6; + grain_scale_shift = film_grain->grain_scale_shift; + bitdepth = ctx->bit_depth; + grain_center = 128 << (bitdepth - 8); + grain_min = 0 - grain_center; + grain_max = (256 << (bitdepth - 8)) - 1 - grain_center; + + rockchip_av1_generate_luma_grain_block(luma_grain_block, bitdepth, + film_grain->num_y_points, grain_scale_shift, + ar_coeff_lag, ar_coeffs_y, ar_coeff_shift, + grain_min, grain_max, film_grain->grain_seed); + + rockchip_av1_generate_chroma_grain_block(luma_grain_block, cb_grain_block, + cr_grain_block, bitdepth, + film_grain->num_y_points, + film_grain->num_cb_points, + film_grain->num_cr_points, + grain_scale_shift, ar_coeff_lag, ar_coeffs_cb, + ar_coeffs_cr, ar_coeff_shift, grain_min, + grain_max, + scaling_from_luma, + film_grain->grain_seed); + + for (i = 0; i < 64; i++) { + for (j = 0; j < 64; j++) + fgmem->cropped_luma_grain_block[i * 64 + j] = + (*luma_grain_block)[i + 9][j + 9]; + } + + for (i = 0; i < 32; i++) { + for (j = 0; j < 32; j++) { + fgmem->cropped_chroma_grain_block[i * 64 + 2 * j] = + (*cb_grain_block)[i + 6][j + 6]; + fgmem->cropped_chroma_grain_block[i * 64 + 2 * j + 1] = + (*cr_grain_block)[i + 6][j + 6]; + } + } + + hantro_write_addr(vpu, AV1_FILM_GRAIN, av1_dec->film_grain.dma); + +alloc_fail: + kfree(ar_coeffs_y); + kfree(ar_coeffs_cb); + kfree(ar_coeffs_cr); + kfree(luma_grain_block); + kfree(cb_grain_block); + kfree(cr_grain_block); +} + +static void rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + const struct v4l2_av1_cdef *cdef = &frame->cdef; + struct hantro_dev *vpu = ctx->dev; + u32 luma_pri_strength = 0; + u16 luma_sec_strength = 0; + u32 chroma_pri_strength = 0; + u16 chroma_sec_strength = 0; + int i; + + hantro_reg_write(vpu, &av1_cdef_bits, cdef->bits); + hantro_reg_write(vpu, &av1_cdef_damping, cdef->damping_minus_3); + + for (i = 0; i < BIT(cdef->bits); i++) { + luma_pri_strength |= cdef->y_pri_strength[i] << (i * 4); + if (cdef->y_sec_strength[i] == 4) + luma_sec_strength |= 3 << (i * 2); + else + luma_sec_strength |= cdef->y_sec_strength[i] << (i * 2); + + chroma_pri_strength |= cdef->uv_pri_strength[i] << (i * 4); + if (cdef->uv_sec_strength[i] == 4) + chroma_sec_strength |= 3 << (i * 2); + else + chroma_sec_strength |= cdef->uv_sec_strength[i] << (i * 2); + } + + hantro_reg_write(vpu, &av1_cdef_luma_primary_strength, + luma_pri_strength); + hantro_reg_write(vpu, &av1_cdef_luma_secondary_strength, + luma_sec_strength); + hantro_reg_write(vpu, &av1_cdef_chroma_primary_strength, + chroma_pri_strength); + hantro_reg_write(vpu, &av1_cdef_chroma_secondary_strength, + chroma_sec_strength); + + hantro_write_addr(vpu, AV1_CDEF_COL, av1_dec->cdef_col.dma); +} + +static void rockchip_vpu981_av1_dec_set_lr(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + const struct v4l2_av1_loop_restoration *loop_restoration = + &frame->loop_restoration; + struct hantro_dev *vpu = ctx->dev; + u16 lr_type = 0, lr_unit_size = 0; + u8 restoration_unit_size[V4L2_AV1_NUM_PLANES_MAX] = { 3, 3, 3 }; + int i; + + if (loop_restoration->flags & V4L2_AV1_LOOP_RESTORATION_FLAG_USES_LR) { + restoration_unit_size[0] = 1 + loop_restoration->lr_unit_shift; + restoration_unit_size[1] = + 1 + loop_restoration->lr_unit_shift - loop_restoration->lr_uv_shift; + restoration_unit_size[2] = + 1 + loop_restoration->lr_unit_shift - loop_restoration->lr_uv_shift; + } + + for (i = 0; i < V4L2_AV1_NUM_PLANES_MAX; i++) { + lr_type |= + loop_restoration->frame_restoration_type[i] << (i * 2); + lr_unit_size |= restoration_unit_size[i] << (i * 2); + } + + hantro_reg_write(vpu, &av1_lr_type, lr_type); + hantro_reg_write(vpu, &av1_lr_unit_size, lr_unit_size); + hantro_write_addr(vpu, AV1_LR_COL, av1_dec->lr_col.dma); +} + +static void rockchip_vpu981_av1_dec_set_superres_params(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + struct hantro_dev *vpu = ctx->dev; + u8 superres_scale_denominator = SCALE_NUMERATOR; + int superres_luma_step = RS_SCALE_SUBPEL_BITS; + int superres_chroma_step = RS_SCALE_SUBPEL_BITS; + int superres_luma_step_invra = RS_SCALE_SUBPEL_BITS; + int superres_chroma_step_invra = RS_SCALE_SUBPEL_BITS; + int superres_init_luma_subpel_x = 0; + int superres_init_chroma_subpel_x = 0; + int superres_is_scaled = 0; + int min_w = min_t(uint32_t, 16, frame->upscaled_width); + int upscaled_luma, downscaled_luma; + int downscaled_chroma, upscaled_chroma; + int step_luma, step_chroma; + int err_luma, err_chroma; + int initial_luma, initial_chroma; + int width = 0; + + if (frame->flags & V4L2_AV1_FRAME_FLAG_USE_SUPERRES) + superres_scale_denominator = frame->superres_denom; + + if (superres_scale_denominator <= SCALE_NUMERATOR) + goto set_regs; + + width = (frame->upscaled_width * SCALE_NUMERATOR + + (superres_scale_denominator / 2)) / superres_scale_denominator; + + if (width < min_w) + width = min_w; + + if (width == frame->upscaled_width) + goto set_regs; + + superres_is_scaled = 1; + upscaled_luma = frame->upscaled_width; + downscaled_luma = width; + downscaled_chroma = (downscaled_luma + 1) >> 1; + upscaled_chroma = (upscaled_luma + 1) >> 1; + step_luma = + ((downscaled_luma << RS_SCALE_SUBPEL_BITS) + + (upscaled_luma / 2)) / upscaled_luma; + step_chroma = + ((downscaled_chroma << RS_SCALE_SUBPEL_BITS) + + (upscaled_chroma / 2)) / upscaled_chroma; + err_luma = + (upscaled_luma * step_luma) + - (downscaled_luma << RS_SCALE_SUBPEL_BITS); + err_chroma = + (upscaled_chroma * step_chroma) + - (downscaled_chroma << RS_SCALE_SUBPEL_BITS); + initial_luma = + ((-((upscaled_luma - downscaled_luma) << (RS_SCALE_SUBPEL_BITS - 1)) + + upscaled_luma / 2) + / upscaled_luma + (1 << (RS_SCALE_EXTRA_BITS - 1)) - err_luma / 2) + & RS_SCALE_SUBPEL_MASK; + initial_chroma = + ((-((upscaled_chroma - downscaled_chroma) << (RS_SCALE_SUBPEL_BITS - 1)) + + upscaled_chroma / 2) + / upscaled_chroma + (1 << (RS_SCALE_EXTRA_BITS - 1)) - err_chroma / 2) + & RS_SCALE_SUBPEL_MASK; + superres_luma_step = step_luma; + superres_chroma_step = step_chroma; + superres_luma_step_invra = + ((upscaled_luma << RS_SCALE_SUBPEL_BITS) + (downscaled_luma / 2)) + / downscaled_luma; + superres_chroma_step_invra = + ((upscaled_chroma << RS_SCALE_SUBPEL_BITS) + (downscaled_chroma / 2)) + / downscaled_chroma; + superres_init_luma_subpel_x = initial_luma; + superres_init_chroma_subpel_x = initial_chroma; + +set_regs: + hantro_reg_write(vpu, &av1_superres_pic_width, frame->upscaled_width); + + if (frame->flags & V4L2_AV1_FRAME_FLAG_USE_SUPERRES) + hantro_reg_write(vpu, &av1_scale_denom_minus9, + frame->superres_denom - SUPERRES_SCALE_DENOMINATOR_MIN); + else + hantro_reg_write(vpu, &av1_scale_denom_minus9, frame->superres_denom); + + hantro_reg_write(vpu, &av1_superres_luma_step, superres_luma_step); + hantro_reg_write(vpu, &av1_superres_chroma_step, superres_chroma_step); + hantro_reg_write(vpu, &av1_superres_luma_step_invra, + superres_luma_step_invra); + hantro_reg_write(vpu, &av1_superres_chroma_step_invra, + superres_chroma_step_invra); + hantro_reg_write(vpu, &av1_superres_init_luma_subpel_x, + superres_init_luma_subpel_x); + hantro_reg_write(vpu, &av1_superres_init_chroma_subpel_x, + superres_init_chroma_subpel_x); + hantro_reg_write(vpu, &av1_superres_is_scaled, superres_is_scaled); + + hantro_write_addr(vpu, AV1_SR_COL, av1_dec->sr_col.dma); +} + +static void rockchip_vpu981_av1_dec_set_picture_dimensions(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + struct hantro_dev *vpu = ctx->dev; + int pic_width_in_cbs = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); + int pic_height_in_cbs = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); + int pic_width_pad = ALIGN(frame->frame_width_minus_1 + 1, 8) + - (frame->frame_width_minus_1 + 1); + int pic_height_pad = ALIGN(frame->frame_height_minus_1 + 1, 8) + - (frame->frame_height_minus_1 + 1); + + hantro_reg_write(vpu, &av1_pic_width_in_cbs, pic_width_in_cbs); + hantro_reg_write(vpu, &av1_pic_height_in_cbs, pic_height_in_cbs); + hantro_reg_write(vpu, &av1_pic_width_pad, pic_width_pad); + hantro_reg_write(vpu, &av1_pic_height_pad, pic_height_pad); + + rockchip_vpu981_av1_dec_set_superres_params(ctx); +} + +static void rockchip_vpu981_av1_dec_set_other_frames(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + struct hantro_dev *vpu = ctx->dev; + bool use_ref_frame_mvs = + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS); + int cur_frame_offset = frame->order_hint; + int alt_frame_offset = 0; + int gld_frame_offset = 0; + int bwd_frame_offset = 0; + int alt2_frame_offset = 0; + int refs_selected[3] = { 0, 0, 0 }; + int cur_mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); + int cur_mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); + int cur_offset[V4L2_AV1_TOTAL_REFS_PER_FRAME - 1]; + int cur_roffset[V4L2_AV1_TOTAL_REFS_PER_FRAME - 1]; + int mf_types[3] = { 0, 0, 0 }; + int ref_stamp = 2; + int ref_ind = 0; + int rf, idx; + + alt_frame_offset = rockchip_vpu981_get_order_hint(ctx, ALT_BUF_IDX); + gld_frame_offset = rockchip_vpu981_get_order_hint(ctx, GLD_BUF_IDX); + bwd_frame_offset = rockchip_vpu981_get_order_hint(ctx, BWD_BUF_IDX); + alt2_frame_offset = rockchip_vpu981_get_order_hint(ctx, ALT2_BUF_IDX); + + idx = rockchip_vpu981_get_frame_index(ctx, LST_BUF_IDX); + if (idx >= 0) { + int alt_frame_offset_in_lst = + av1_dec->frame_refs[idx].order_hints[V4L2_AV1_REF_ALTREF_FRAME]; + bool is_lst_overlay = + (alt_frame_offset_in_lst == gld_frame_offset); + + if (!is_lst_overlay) { + int lst_mi_cols = av1_dec->frame_refs[idx].mi_cols; + int lst_mi_rows = av1_dec->frame_refs[idx].mi_rows; + bool lst_intra_only = + IS_INTRA(av1_dec->frame_refs[idx].frame_type); + + if (lst_mi_cols == cur_mi_cols && + lst_mi_rows == cur_mi_rows && !lst_intra_only) { + mf_types[ref_ind] = V4L2_AV1_REF_LAST_FRAME; + refs_selected[ref_ind++] = LST_BUF_IDX; + } + } + ref_stamp--; + } + + idx = rockchip_vpu981_get_frame_index(ctx, BWD_BUF_IDX); + if (rockchip_vpu981_av1_dec_get_dist(ctx, bwd_frame_offset, cur_frame_offset) > 0) { + int bwd_mi_cols = av1_dec->frame_refs[idx].mi_cols; + int bwd_mi_rows = av1_dec->frame_refs[idx].mi_rows; + bool bwd_intra_only = + IS_INTRA(av1_dec->frame_refs[idx].frame_type); + + if (bwd_mi_cols == cur_mi_cols && bwd_mi_rows == cur_mi_rows && + !bwd_intra_only) { + mf_types[ref_ind] = V4L2_AV1_REF_BWDREF_FRAME; + refs_selected[ref_ind++] = BWD_BUF_IDX; + ref_stamp--; + } + } + + idx = rockchip_vpu981_get_frame_index(ctx, ALT2_BUF_IDX); + if (rockchip_vpu981_av1_dec_get_dist(ctx, alt2_frame_offset, cur_frame_offset) > 0) { + int alt2_mi_cols = av1_dec->frame_refs[idx].mi_cols; + int alt2_mi_rows = av1_dec->frame_refs[idx].mi_rows; + bool alt2_intra_only = + IS_INTRA(av1_dec->frame_refs[idx].frame_type); + + if (alt2_mi_cols == cur_mi_cols && alt2_mi_rows == cur_mi_rows && + !alt2_intra_only) { + mf_types[ref_ind] = V4L2_AV1_REF_ALTREF2_FRAME; + refs_selected[ref_ind++] = ALT2_BUF_IDX; + ref_stamp--; + } + } + + idx = rockchip_vpu981_get_frame_index(ctx, ALT_BUF_IDX); + if (rockchip_vpu981_av1_dec_get_dist(ctx, alt_frame_offset, cur_frame_offset) > 0 && + ref_stamp >= 0) { + int alt_mi_cols = av1_dec->frame_refs[idx].mi_cols; + int alt_mi_rows = av1_dec->frame_refs[idx].mi_rows; + bool alt_intra_only = + IS_INTRA(av1_dec->frame_refs[idx].frame_type); + + if (alt_mi_cols == cur_mi_cols && alt_mi_rows == cur_mi_rows && + !alt_intra_only) { + mf_types[ref_ind] = V4L2_AV1_REF_ALTREF_FRAME; + refs_selected[ref_ind++] = ALT_BUF_IDX; + ref_stamp--; + } + } + + idx = rockchip_vpu981_get_frame_index(ctx, LST2_BUF_IDX); + if (idx >= 0 && ref_stamp >= 0) { + int lst2_mi_cols = av1_dec->frame_refs[idx].mi_cols; + int lst2_mi_rows = av1_dec->frame_refs[idx].mi_rows; + bool lst2_intra_only = + IS_INTRA(av1_dec->frame_refs[idx].frame_type); + + if (lst2_mi_cols == cur_mi_cols && lst2_mi_rows == cur_mi_rows && + !lst2_intra_only) { + mf_types[ref_ind] = V4L2_AV1_REF_LAST2_FRAME; + refs_selected[ref_ind++] = LST2_BUF_IDX; + ref_stamp--; + } + } + + for (rf = 0; rf < V4L2_AV1_TOTAL_REFS_PER_FRAME - 1; ++rf) { + idx = rockchip_vpu981_get_frame_index(ctx, rf); + if (idx >= 0) { + int rf_order_hint = rockchip_vpu981_get_order_hint(ctx, rf); + + cur_offset[rf] = + rockchip_vpu981_av1_dec_get_dist(ctx, cur_frame_offset, rf_order_hint); + cur_roffset[rf] = + rockchip_vpu981_av1_dec_get_dist(ctx, rf_order_hint, cur_frame_offset); + } else { + cur_offset[rf] = 0; + cur_roffset[rf] = 0; + } + } + + hantro_reg_write(vpu, &av1_use_temporal0_mvs, 0); + hantro_reg_write(vpu, &av1_use_temporal1_mvs, 0); + hantro_reg_write(vpu, &av1_use_temporal2_mvs, 0); + hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0); + + hantro_reg_write(vpu, &av1_mf1_last_offset, 0); + hantro_reg_write(vpu, &av1_mf1_last2_offset, 0); + hantro_reg_write(vpu, &av1_mf1_last3_offset, 0); + hantro_reg_write(vpu, &av1_mf1_golden_offset, 0); + hantro_reg_write(vpu, &av1_mf1_bwdref_offset, 0); + hantro_reg_write(vpu, &av1_mf1_altref2_offset, 0); + hantro_reg_write(vpu, &av1_mf1_altref_offset, 0); + + if (use_ref_frame_mvs && ref_ind > 0 && + cur_offset[mf_types[0] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && + cur_offset[mf_types[0] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { + int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[0]); + int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[0]); + u32 *oh = av1_dec->frame_refs[idx].order_hints; + int val; + + hantro_reg_write(vpu, &av1_use_temporal0_mvs, 1); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); + hantro_reg_write(vpu, &av1_mf1_last_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); + hantro_reg_write(vpu, &av1_mf1_last2_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); + hantro_reg_write(vpu, &av1_mf1_last3_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); + hantro_reg_write(vpu, &av1_mf1_golden_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); + hantro_reg_write(vpu, &av1_mf1_bwdref_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); + hantro_reg_write(vpu, &av1_mf1_altref2_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); + hantro_reg_write(vpu, &av1_mf1_altref_offset, val); + } + + hantro_reg_write(vpu, &av1_mf2_last_offset, 0); + hantro_reg_write(vpu, &av1_mf2_last2_offset, 0); + hantro_reg_write(vpu, &av1_mf2_last3_offset, 0); + hantro_reg_write(vpu, &av1_mf2_golden_offset, 0); + hantro_reg_write(vpu, &av1_mf2_bwdref_offset, 0); + hantro_reg_write(vpu, &av1_mf2_altref2_offset, 0); + hantro_reg_write(vpu, &av1_mf2_altref_offset, 0); + + if (use_ref_frame_mvs && ref_ind > 1 && + cur_offset[mf_types[1] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && + cur_offset[mf_types[1] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { + int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[1]); + int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[1]); + u32 *oh = av1_dec->frame_refs[idx].order_hints; + int val; + + hantro_reg_write(vpu, &av1_use_temporal1_mvs, 1); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); + hantro_reg_write(vpu, &av1_mf2_last_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); + hantro_reg_write(vpu, &av1_mf2_last2_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); + hantro_reg_write(vpu, &av1_mf2_last3_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); + hantro_reg_write(vpu, &av1_mf2_golden_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); + hantro_reg_write(vpu, &av1_mf2_bwdref_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); + hantro_reg_write(vpu, &av1_mf2_altref2_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); + hantro_reg_write(vpu, &av1_mf2_altref_offset, val); + } + + hantro_reg_write(vpu, &av1_mf3_last_offset, 0); + hantro_reg_write(vpu, &av1_mf3_last2_offset, 0); + hantro_reg_write(vpu, &av1_mf3_last3_offset, 0); + hantro_reg_write(vpu, &av1_mf3_golden_offset, 0); + hantro_reg_write(vpu, &av1_mf3_bwdref_offset, 0); + hantro_reg_write(vpu, &av1_mf3_altref2_offset, 0); + hantro_reg_write(vpu, &av1_mf3_altref_offset, 0); + + if (use_ref_frame_mvs && ref_ind > 2 && + cur_offset[mf_types[2] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && + cur_offset[mf_types[2] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { + int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[2]); + int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[2]); + u32 *oh = av1_dec->frame_refs[idx].order_hints; + int val; + + hantro_reg_write(vpu, &av1_use_temporal2_mvs, 1); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); + hantro_reg_write(vpu, &av1_mf3_last_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); + hantro_reg_write(vpu, &av1_mf3_last2_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); + hantro_reg_write(vpu, &av1_mf3_last3_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); + hantro_reg_write(vpu, &av1_mf3_golden_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); + hantro_reg_write(vpu, &av1_mf3_bwdref_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); + hantro_reg_write(vpu, &av1_mf3_altref2_offset, val); + + val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); + hantro_reg_write(vpu, &av1_mf3_altref_offset, val); + } + + hantro_reg_write(vpu, &av1_cur_last_offset, cur_offset[0]); + hantro_reg_write(vpu, &av1_cur_last2_offset, cur_offset[1]); + hantro_reg_write(vpu, &av1_cur_last3_offset, cur_offset[2]); + hantro_reg_write(vpu, &av1_cur_golden_offset, cur_offset[3]); + hantro_reg_write(vpu, &av1_cur_bwdref_offset, cur_offset[4]); + hantro_reg_write(vpu, &av1_cur_altref2_offset, cur_offset[5]); + hantro_reg_write(vpu, &av1_cur_altref_offset, cur_offset[6]); + + hantro_reg_write(vpu, &av1_cur_last_roffset, cur_roffset[0]); + hantro_reg_write(vpu, &av1_cur_last2_roffset, cur_roffset[1]); + hantro_reg_write(vpu, &av1_cur_last3_roffset, cur_roffset[2]); + hantro_reg_write(vpu, &av1_cur_golden_roffset, cur_roffset[3]); + hantro_reg_write(vpu, &av1_cur_bwdref_roffset, cur_roffset[4]); + hantro_reg_write(vpu, &av1_cur_altref2_roffset, cur_roffset[5]); + hantro_reg_write(vpu, &av1_cur_altref_roffset, cur_roffset[6]); + + hantro_reg_write(vpu, &av1_mf1_type, mf_types[0] - V4L2_AV1_REF_LAST_FRAME); + hantro_reg_write(vpu, &av1_mf2_type, mf_types[1] - V4L2_AV1_REF_LAST_FRAME); + hantro_reg_write(vpu, &av1_mf3_type, mf_types[2] - V4L2_AV1_REF_LAST_FRAME); +} + +static void rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; + int frame_type = frame->frame_type; + bool allow_intrabc = !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC); + int ref_count[AV1DEC_MAX_PIC_BUFFERS] = { 0 }; + struct hantro_dev *vpu = ctx->dev; + int i, ref_frames = 0; + bool scale_enable = false; + + if (IS_INTRA(frame_type) && !allow_intrabc) + return; + + if (!allow_intrabc) { + for (i = 0; i < V4L2_AV1_REFS_PER_FRAME; i++) { + int idx = rockchip_vpu981_get_frame_index(ctx, i); + + if (idx >= 0) + ref_count[idx]++; + } + + for (i = 0; i < AV1DEC_MAX_PIC_BUFFERS; i++) { + if (ref_count[i]) + ref_frames++; + } + } else { + ref_frames = 1; + } + hantro_reg_write(vpu, &av1_ref_frames, ref_frames); + + rockchip_vpu981_av1_dec_set_frame_sign_bias(ctx); + + for (i = V4L2_AV1_REF_LAST_FRAME; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) { + u32 ref = i - 1; + int idx = 0; + int width, height; + + if (allow_intrabc) { + idx = av1_dec->current_frame_index; + width = frame->frame_width_minus_1 + 1; + height = frame->frame_height_minus_1 + 1; + } else { + if (rockchip_vpu981_get_frame_index(ctx, ref) > 0) + idx = rockchip_vpu981_get_frame_index(ctx, ref); + width = av1_dec->frame_refs[idx].width; + height = av1_dec->frame_refs[idx].height; + } + + scale_enable |= + rockchip_vpu981_av1_dec_set_ref(ctx, ref, idx, width, + height); + + rockchip_vpu981_av1_dec_set_sign_bias(ctx, ref, + av1_dec->ref_frame_sign_bias[i]); + } + hantro_reg_write(vpu, &av1_ref_scaling_enable, scale_enable); + + hantro_reg_write(vpu, &av1_ref0_gm_mode, + frame->global_motion.type[V4L2_AV1_REF_LAST_FRAME]); + hantro_reg_write(vpu, &av1_ref1_gm_mode, + frame->global_motion.type[V4L2_AV1_REF_LAST2_FRAME]); + hantro_reg_write(vpu, &av1_ref2_gm_mode, + frame->global_motion.type[V4L2_AV1_REF_LAST3_FRAME]); + hantro_reg_write(vpu, &av1_ref3_gm_mode, + frame->global_motion.type[V4L2_AV1_REF_GOLDEN_FRAME]); + hantro_reg_write(vpu, &av1_ref4_gm_mode, + frame->global_motion.type[V4L2_AV1_REF_BWDREF_FRAME]); + hantro_reg_write(vpu, &av1_ref5_gm_mode, + frame->global_motion.type[V4L2_AV1_REF_ALTREF2_FRAME]); + hantro_reg_write(vpu, &av1_ref6_gm_mode, + frame->global_motion.type[V4L2_AV1_REF_ALTREF_FRAME]); + + rockchip_vpu981_av1_dec_set_other_frames(ctx); +} + +static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + + hantro_reg_write(vpu, &av1_skip_mode, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT)); + hantro_reg_write(vpu, &av1_tempor_mvp_e, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS)); + hantro_reg_write(vpu, &av1_delta_lf_res_log, + ctrls->frame->loop_filter.delta_lf_res); + hantro_reg_write(vpu, &av1_delta_lf_multi, + !!(ctrls->frame->loop_filter.flags + & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_MULTI)); + hantro_reg_write(vpu, &av1_delta_lf_present, + !!(ctrls->frame->loop_filter.flags + & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_PRESENT)); + hantro_reg_write(vpu, &av1_disable_cdf_update, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_DISABLE_CDF_UPDATE)); + hantro_reg_write(vpu, &av1_allow_warp, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_WARPED_MOTION)); + hantro_reg_write(vpu, &av1_show_frame, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SHOW_FRAME)); + hantro_reg_write(vpu, &av1_switchable_motion_mode, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE)); + hantro_reg_write(vpu, &av1_enable_cdef, + !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF)); + hantro_reg_write(vpu, &av1_allow_masked_compound, + !!(ctrls->sequence->flags + & V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND)); + hantro_reg_write(vpu, &av1_allow_interintra, + !!(ctrls->sequence->flags + & V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTERINTRA_COMPOUND)); + hantro_reg_write(vpu, &av1_enable_intra_edge_filter, + !!(ctrls->sequence->flags + & V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTRA_EDGE_FILTER)); + hantro_reg_write(vpu, &av1_allow_filter_intra, + !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_FILTER_INTRA)); + hantro_reg_write(vpu, &av1_enable_jnt_comp, + !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_JNT_COMP)); + hantro_reg_write(vpu, &av1_enable_dual_filter, + !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_DUAL_FILTER)); + hantro_reg_write(vpu, &av1_reduced_tx_set_used, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REDUCED_TX_SET)); + hantro_reg_write(vpu, &av1_allow_screen_content_tools, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS)); + hantro_reg_write(vpu, &av1_allow_intrabc, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC)); + + if (!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS)) + hantro_reg_write(vpu, &av1_force_interger_mv, 0); + else + hantro_reg_write(vpu, &av1_force_interger_mv, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_FORCE_INTEGER_MV)); + + hantro_reg_write(vpu, &av1_blackwhite_e, 0); + hantro_reg_write(vpu, &av1_delta_q_res_log, ctrls->frame->quantization.delta_q_res); + hantro_reg_write(vpu, &av1_delta_q_present, + !!(ctrls->frame->quantization.flags + & V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT)); + + hantro_reg_write(vpu, &av1_idr_pic_e, !ctrls->frame->frame_type); + hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx); + hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8); + hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8); + + hantro_reg_write(vpu, &av1_mcomp_filt_type, ctrls->frame->interpolation_filter); + hantro_reg_write(vpu, &av1_high_prec_mv_e, + !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV)); + hantro_reg_write(vpu, &av1_comp_pred_mode, + (ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT) ? 2 : 0); + hantro_reg_write(vpu, &av1_transform_mode, (ctrls->frame->tx_mode == 1) ? 3 : 4); + hantro_reg_write(vpu, &av1_max_cb_size, + (ctrls->sequence->flags + & V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK) ? 7 : 6); + hantro_reg_write(vpu, &av1_min_cb_size, 3); + + hantro_reg_write(vpu, &av1_comp_pred_fixed_ref, 0); + hantro_reg_write(vpu, &av1_comp_pred_var_ref0_av1, 0); + hantro_reg_write(vpu, &av1_comp_pred_var_ref1_av1, 0); + hantro_reg_write(vpu, &av1_filt_level_seg0, 0); + hantro_reg_write(vpu, &av1_filt_level_seg1, 0); + hantro_reg_write(vpu, &av1_filt_level_seg2, 0); + hantro_reg_write(vpu, &av1_filt_level_seg3, 0); + hantro_reg_write(vpu, &av1_filt_level_seg4, 0); + hantro_reg_write(vpu, &av1_filt_level_seg5, 0); + hantro_reg_write(vpu, &av1_filt_level_seg6, 0); + hantro_reg_write(vpu, &av1_filt_level_seg7, 0); + + hantro_reg_write(vpu, &av1_qp_delta_y_dc_av1, ctrls->frame->quantization.delta_q_y_dc); + hantro_reg_write(vpu, &av1_qp_delta_ch_dc_av1, ctrls->frame->quantization.delta_q_u_dc); + hantro_reg_write(vpu, &av1_qp_delta_ch_ac_av1, ctrls->frame->quantization.delta_q_u_ac); + if (ctrls->frame->quantization.flags & V4L2_AV1_QUANTIZATION_FLAG_USING_QMATRIX) { + hantro_reg_write(vpu, &av1_qmlevel_y, ctrls->frame->quantization.qm_y); + hantro_reg_write(vpu, &av1_qmlevel_u, ctrls->frame->quantization.qm_u); + hantro_reg_write(vpu, &av1_qmlevel_v, ctrls->frame->quantization.qm_v); + } else { + hantro_reg_write(vpu, &av1_qmlevel_y, 0xff); + hantro_reg_write(vpu, &av1_qmlevel_u, 0xff); + hantro_reg_write(vpu, &av1_qmlevel_v, 0xff); + } + + hantro_reg_write(vpu, &av1_lossless_e, rockchip_vpu981_av1_dec_is_lossless(ctx)); + hantro_reg_write(vpu, &av1_quant_delta_v_dc, ctrls->frame->quantization.delta_q_v_dc); + hantro_reg_write(vpu, &av1_quant_delta_v_ac, ctrls->frame->quantization.delta_q_v_ac); + + hantro_reg_write(vpu, &av1_skip_ref0, + (ctrls->frame->skip_mode_frame[0]) ? ctrls->frame->skip_mode_frame[0] : 1); + hantro_reg_write(vpu, &av1_skip_ref1, + (ctrls->frame->skip_mode_frame[1]) ? ctrls->frame->skip_mode_frame[1] : 1); + + hantro_write_addr(vpu, AV1_MC_SYNC_CURR, av1_dec->tile_buf.dma); + hantro_write_addr(vpu, AV1_MC_SYNC_LEFT, av1_dec->tile_buf.dma); +} + +static void +rockchip_vpu981_av1_dec_set_input_buffer(struct hantro_ctx *ctx, + struct vb2_v4l2_buffer *vb2_src) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; + const struct v4l2_ctrl_av1_tile_group_entry *group_entry = + ctrls->tile_group_entry; + struct hantro_dev *vpu = ctx->dev; + dma_addr_t src_dma; + u32 src_len, src_buf_len; + int start_bit, offset; + + src_dma = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); + src_len = vb2_get_plane_payload(&vb2_src->vb2_buf, 0); + src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); + + start_bit = (group_entry[0].tile_offset & 0xf) * 8; + offset = group_entry[0].tile_offset & ~0xf; + + hantro_reg_write(vpu, &av1_strm_buffer_len, src_buf_len); + hantro_reg_write(vpu, &av1_strm_start_bit, start_bit); + hantro_reg_write(vpu, &av1_stream_len, src_len); + hantro_reg_write(vpu, &av1_strm_start_offset, 0); + hantro_write_addr(vpu, AV1_INPUT_STREAM, src_dma + offset); +} + +static void +rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx) +{ + struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; + struct hantro_dev *vpu = ctx->dev; + struct hantro_decoded_buffer *dst; + struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t luma_addr, chroma_addr, mv_addr = 0; + size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx); + size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx); + + vb2_dst = av1_dec->frame_refs[av1_dec->current_frame_index].vb2_ref; + dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf); + luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); + chroma_addr = luma_addr + cr_offset; + mv_addr = luma_addr + mv_offset; + + hantro_write_addr(vpu, AV1_TILE_OUT_LU, luma_addr); + hantro_write_addr(vpu, AV1_TILE_OUT_CH, chroma_addr); + hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr); +} + +int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + struct vb2_v4l2_buffer *vb2_src; + int ret; + + hantro_start_prepare_run(ctx); + + ret = rockchip_vpu981_av1_dec_prepare_run(ctx); + if (ret) + goto prepare_error; + + vb2_src = hantro_get_src_buf(ctx); + if (!vb2_src) { + ret = -EINVAL; + goto prepare_error; + } + + rockchip_vpu981_av1_dec_clean_refs(ctx); + rockchip_vpu981_av1_dec_frame_ref(ctx, vb2_src->vb2_buf.timestamp); + + rockchip_vpu981_av1_dec_set_parameters(ctx); + rockchip_vpu981_av1_dec_set_global_model(ctx); + rockchip_vpu981_av1_dec_set_tile_info(ctx); + rockchip_vpu981_av1_dec_set_reference_frames(ctx); + rockchip_vpu981_av1_dec_set_segmentation(ctx); + rockchip_vpu981_av1_dec_set_loopfilter(ctx); + rockchip_vpu981_av1_dec_set_picture_dimensions(ctx); + rockchip_vpu981_av1_dec_set_cdef(ctx); + rockchip_vpu981_av1_dec_set_lr(ctx); + rockchip_vpu981_av1_dec_set_fgs(ctx); + rockchip_vpu981_av1_dec_set_prob(ctx); + + hantro_reg_write(vpu, &av1_dec_mode, AV1_DEC_MODE); + hantro_reg_write(vpu, &av1_dec_out_ec_byte_word, 0); + hantro_reg_write(vpu, &av1_write_mvs_e, 1); + hantro_reg_write(vpu, &av1_dec_out_ec_bypass, 1); + hantro_reg_write(vpu, &av1_dec_clk_gate_e, 1); + + hantro_reg_write(vpu, &av1_dec_abort_e, 0); + hantro_reg_write(vpu, &av1_dec_tile_int_e, 0); + + hantro_reg_write(vpu, &av1_dec_alignment, 64); + hantro_reg_write(vpu, &av1_apf_disable, 0); + hantro_reg_write(vpu, &av1_apf_threshold, 8); + hantro_reg_write(vpu, &av1_dec_buswidth, 2); + hantro_reg_write(vpu, &av1_dec_max_burst, 16); + hantro_reg_write(vpu, &av1_error_conceal_e, 0); + hantro_reg_write(vpu, &av1_axi_rd_ostd_threshold, 64); + hantro_reg_write(vpu, &av1_axi_wr_ostd_threshold, 64); + + hantro_reg_write(vpu, &av1_ext_timeout_cycles, 0xfffffff); + hantro_reg_write(vpu, &av1_ext_timeout_override_e, 1); + hantro_reg_write(vpu, &av1_timeout_cycles, 0xfffffff); + hantro_reg_write(vpu, &av1_timeout_override_e, 1); + + rockchip_vpu981_av1_dec_set_output_buffer(ctx); + rockchip_vpu981_av1_dec_set_input_buffer(ctx, vb2_src); + + hantro_end_prepare_run(ctx); + + hantro_reg_write(vpu, &av1_dec_e, 1); + + return 0; + +prepare_error: + hantro_end_prepare_run(ctx); + hantro_irq_done(vpu, VB2_BUF_STATE_ERROR); + return ret; +} + +static void rockchip_vpu981_postproc_enable(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + int width = ctx->dst_fmt.width; + int height = ctx->dst_fmt.height; + struct vb2_v4l2_buffer *vb2_dst; + size_t chroma_offset; + dma_addr_t dst_dma; + + vb2_dst = hantro_get_dst_buf(ctx); + + dst_dma = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + chroma_offset = ctx->dst_fmt.plane_fmt[0].bytesperline * + ctx->dst_fmt.height; + + /* enable post processor */ + hantro_reg_write(vpu, &av1_pp_out_e, 1); + hantro_reg_write(vpu, &av1_pp_in_format, 0); + hantro_reg_write(vpu, &av1_pp0_dup_hor, 1); + hantro_reg_write(vpu, &av1_pp0_dup_ver, 1); + + hantro_reg_write(vpu, &av1_pp_in_height, height / 2); + hantro_reg_write(vpu, &av1_pp_in_width, width / 2); + hantro_reg_write(vpu, &av1_pp_out_height, height); + hantro_reg_write(vpu, &av1_pp_out_width, width); + hantro_reg_write(vpu, &av1_pp_out_y_stride, + ctx->dst_fmt.plane_fmt[0].bytesperline); + hantro_reg_write(vpu, &av1_pp_out_c_stride, + ctx->dst_fmt.plane_fmt[0].bytesperline); + switch (ctx->dst_fmt.pixelformat) { + case V4L2_PIX_FMT_P010: + hantro_reg_write(vpu, &av1_pp_out_format, 1); + break; + case V4L2_PIX_FMT_NV12: + hantro_reg_write(vpu, &av1_pp_out_format, 3); + break; + default: + hantro_reg_write(vpu, &av1_pp_out_format, 0); + } + + hantro_reg_write(vpu, &av1_ppd_blend_exist, 0); + hantro_reg_write(vpu, &av1_ppd_dith_exist, 0); + hantro_reg_write(vpu, &av1_ablend_crop_e, 0); + hantro_reg_write(vpu, &av1_pp_format_customer1_e, 0); + hantro_reg_write(vpu, &av1_pp_crop_exist, 0); + hantro_reg_write(vpu, &av1_pp_up_level, 0); + hantro_reg_write(vpu, &av1_pp_down_level, 0); + hantro_reg_write(vpu, &av1_pp_exist, 0); + + hantro_write_addr(vpu, AV1_PP_OUT_LU, dst_dma); + hantro_write_addr(vpu, AV1_PP_OUT_CH, dst_dma + chroma_offset); +} + +static void rockchip_vpu981_postproc_disable(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + + /* disable post processor */ + hantro_reg_write(vpu, &av1_pp_out_e, 0); +} + +const struct hantro_postproc_ops rockchip_vpu981_postproc_ops = { + .enable = rockchip_vpu981_postproc_enable, + .disable = rockchip_vpu981_postproc_disable, +}; diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h new file mode 100644 index 000000000000..182e6c830ff6 --- /dev/null +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_regs.h @@ -0,0 +1,477 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Collabora + * + * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com> + */ + +#ifndef _ROCKCHIP_VPU981_REGS_H_ +#define _ROCKCHIP_VPU981_REGS_H_ + +#include "hantro.h" + +#define AV1_SWREG(nr) ((nr) * 4) + +#define AV1_DEC_REG(b, s, m) \ + ((const struct hantro_reg) { \ + .base = AV1_SWREG(b), \ + .shift = s, \ + .mask = m, \ + }) + +#define AV1_REG_INTERRUPT AV1_SWREG(1) +#define AV1_REG_INTERRUPT_DEC_RDY_INT BIT(12) + +#define AV1_REG_CONFIG AV1_SWREG(2) +#define AV1_REG_CONFIG_DEC_CLK_GATE_E BIT(10) + +#define av1_dec_e AV1_DEC_REG(1, 0, 0x1) +#define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1) +#define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1) + +#define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1) + +#define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1) +#define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1) +#define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1) +#define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1) +#define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1) +#define av1_skip_mode AV1_DEC_REG(3, 26, 0x1) +#define av1_dec_mode AV1_DEC_REG(3, 27, 0x1f) + +#define av1_ref_frames AV1_DEC_REG(4, 0, 0xf) +#define av1_pic_height_in_cbs AV1_DEC_REG(4, 6, 0x1fff) +#define av1_pic_width_in_cbs AV1_DEC_REG(4, 19, 0x1fff) + +#define av1_ref_scaling_enable AV1_DEC_REG(5, 0, 0x1) +#define av1_filt_level_base_gt32 AV1_DEC_REG(5, 1, 0x1) +#define av1_error_resilient AV1_DEC_REG(5, 2, 0x1) +#define av1_force_interger_mv AV1_DEC_REG(5, 3, 0x1) +#define av1_allow_intrabc AV1_DEC_REG(5, 4, 0x1) +#define av1_allow_screen_content_tools AV1_DEC_REG(5, 5, 0x1) +#define av1_reduced_tx_set_used AV1_DEC_REG(5, 6, 0x1) +#define av1_enable_dual_filter AV1_DEC_REG(5, 7, 0x1) +#define av1_enable_jnt_comp AV1_DEC_REG(5, 8, 0x1) +#define av1_allow_filter_intra AV1_DEC_REG(5, 9, 0x1) +#define av1_enable_intra_edge_filter AV1_DEC_REG(5, 10, 0x1) +#define av1_tempor_mvp_e AV1_DEC_REG(5, 11, 0x1) +#define av1_allow_interintra AV1_DEC_REG(5, 12, 0x1) +#define av1_allow_masked_compound AV1_DEC_REG(5, 13, 0x1) +#define av1_enable_cdef AV1_DEC_REG(5, 14, 0x1) +#define av1_switchable_motion_mode AV1_DEC_REG(5, 15, 0x1) +#define av1_show_frame AV1_DEC_REG(5, 16, 0x1) +#define av1_superres_is_scaled AV1_DEC_REG(5, 17, 0x1) +#define av1_allow_warp AV1_DEC_REG(5, 18, 0x1) +#define av1_disable_cdf_update AV1_DEC_REG(5, 19, 0x1) +#define av1_preskip_segid AV1_DEC_REG(5, 20, 0x1) +#define av1_delta_lf_present AV1_DEC_REG(5, 21, 0x1) +#define av1_delta_lf_multi AV1_DEC_REG(5, 22, 0x1) +#define av1_delta_lf_res_log AV1_DEC_REG(5, 23, 0x3) +#define av1_strm_start_bit AV1_DEC_REG(5, 25, 0x7f) + +#define av1_stream_len AV1_DEC_REG(6, 0, 0xffffffff) + +#define av1_delta_q_present AV1_DEC_REG(7, 0, 0x1) +#define av1_delta_q_res_log AV1_DEC_REG(7, 1, 0x3) +#define av1_cdef_damping AV1_DEC_REG(7, 3, 0x3) +#define av1_cdef_bits AV1_DEC_REG(7, 5, 0x3) +#define av1_apply_grain AV1_DEC_REG(7, 7, 0x1) +#define av1_num_y_points_b AV1_DEC_REG(7, 8, 0x1) +#define av1_num_cb_points_b AV1_DEC_REG(7, 9, 0x1) +#define av1_num_cr_points_b AV1_DEC_REG(7, 10, 0x1) +#define av1_overlap_flag AV1_DEC_REG(7, 11, 0x1) +#define av1_clip_to_restricted_range AV1_DEC_REG(7, 12, 0x1) +#define av1_chroma_scaling_from_luma AV1_DEC_REG(7, 13, 0x1) +#define av1_random_seed AV1_DEC_REG(7, 14, 0xffff) +#define av1_blackwhite_e AV1_DEC_REG(7, 30, 0x1) + +#define av1_scaling_shift AV1_DEC_REG(8, 0, 0xf) +#define av1_bit_depth_c_minus8 AV1_DEC_REG(8, 4, 0x3) +#define av1_bit_depth_y_minus8 AV1_DEC_REG(8, 6, 0x3) +#define av1_quant_base_qindex AV1_DEC_REG(8, 8, 0xff) +#define av1_idr_pic_e AV1_DEC_REG(8, 16, 0x1) +#define av1_superres_pic_width AV1_DEC_REG(8, 17, 0x7fff) + +#define av1_ref4_sign_bias AV1_DEC_REG(9, 2, 0x1) +#define av1_ref5_sign_bias AV1_DEC_REG(9, 3, 0x1) +#define av1_ref6_sign_bias AV1_DEC_REG(9, 4, 0x1) +#define av1_mf1_type AV1_DEC_REG(9, 5, 0x7) +#define av1_mf2_type AV1_DEC_REG(9, 8, 0x7) +#define av1_mf3_type AV1_DEC_REG(9, 11, 0x7) +#define av1_scale_denom_minus9 AV1_DEC_REG(9, 14, 0x7) +#define av1_last_active_seg AV1_DEC_REG(9, 17, 0x7) +#define av1_context_update_tile_id AV1_DEC_REG(9, 20, 0xfff) + +#define av1_tile_transpose AV1_DEC_REG(10, 0, 0x1) +#define av1_tile_enable AV1_DEC_REG(10, 1, 0x1) +#define av1_multicore_full_width AV1_DEC_REG(10, 2, 0xff) +#define av1_num_tile_rows_8k AV1_DEC_REG(10, 10, 0x7f) +#define av1_num_tile_cols_8k AV1_DEC_REG(10, 17, 0x7f) +#define av1_multicore_tile_start_x AV1_DEC_REG(10, 24, 0xff) + +#define av1_use_temporal3_mvs AV1_DEC_REG(11, 0, 0x1) +#define av1_use_temporal2_mvs AV1_DEC_REG(11, 1, 0x1) +#define av1_use_temporal1_mvs AV1_DEC_REG(11, 2, 0x1) +#define av1_use_temporal0_mvs AV1_DEC_REG(11, 3, 0x1) +#define av1_comp_pred_mode AV1_DEC_REG(11, 4, 0x3) +#define av1_high_prec_mv_e AV1_DEC_REG(11, 7, 0x1) +#define av1_mcomp_filt_type AV1_DEC_REG(11, 8, 0x7) +#define av1_multicore_expect_context_update AV1_DEC_REG(11, 11, 0x1) +#define av1_multicore_sbx_offset AV1_DEC_REG(11, 12, 0x7f) +#define av1_ulticore_tile_col AV1_DEC_REG(11, 19, 0x7f) +#define av1_transform_mode AV1_DEC_REG(11, 27, 0x7) +#define av1_dec_tile_size_mag AV1_DEC_REG(11, 30, 0x3) + +#define av1_seg_quant_sign AV1_DEC_REG(12, 2, 0xff) +#define av1_max_cb_size AV1_DEC_REG(12, 10, 0x7) +#define av1_min_cb_size AV1_DEC_REG(12, 13, 0x7) +#define av1_comp_pred_fixed_ref AV1_DEC_REG(12, 16, 0x7) +#define av1_multicore_tile_width AV1_DEC_REG(12, 19, 0x7f) +#define av1_pic_height_pad AV1_DEC_REG(12, 26, 0x7) +#define av1_pic_width_pad AV1_DEC_REG(12, 29, 0x7) + +#define av1_segment_e AV1_DEC_REG(13, 0, 0x1) +#define av1_segment_upd_e AV1_DEC_REG(13, 1, 0x1) +#define av1_segment_temp_upd_e AV1_DEC_REG(13, 2, 0x1) +#define av1_comp_pred_var_ref0_av1 AV1_DEC_REG(13, 3, 0x7) +#define av1_comp_pred_var_ref1_av1 AV1_DEC_REG(13, 6, 0x7) +#define av1_lossless_e AV1_DEC_REG(13, 9, 0x1) +#define av1_qp_delta_ch_ac_av1 AV1_DEC_REG(13, 11, 0x7f) +#define av1_qp_delta_ch_dc_av1 AV1_DEC_REG(13, 18, 0x7f) +#define av1_qp_delta_y_dc_av1 AV1_DEC_REG(13, 25, 0x7f) + +#define av1_quant_seg0 AV1_DEC_REG(14, 0, 0xff) +#define av1_filt_level_seg0 AV1_DEC_REG(14, 8, 0x3f) +#define av1_skip_seg0 AV1_DEC_REG(14, 14, 0x1) +#define av1_refpic_seg0 AV1_DEC_REG(14, 15, 0xf) +#define av1_filt_level_delta0_seg0 AV1_DEC_REG(14, 19, 0x7f) +#define av1_filt_level0 AV1_DEC_REG(14, 26, 0x3f) + +#define av1_quant_seg1 AV1_DEC_REG(15, 0, 0xff) +#define av1_filt_level_seg1 AV1_DEC_REG(15, 8, 0x3f) +#define av1_skip_seg1 AV1_DEC_REG(15, 14, 0x1) +#define av1_refpic_seg1 AV1_DEC_REG(15, 15, 0xf) +#define av1_filt_level_delta0_seg1 AV1_DEC_REG(15, 19, 0x7f) +#define av1_filt_level1 AV1_DEC_REG(15, 26, 0x3f) + +#define av1_quant_seg2 AV1_DEC_REG(16, 0, 0xff) +#define av1_filt_level_seg2 AV1_DEC_REG(16, 8, 0x3f) +#define av1_skip_seg2 AV1_DEC_REG(16, 14, 0x1) +#define av1_refpic_seg2 AV1_DEC_REG(16, 15, 0xf) +#define av1_filt_level_delta0_seg2 AV1_DEC_REG(16, 19, 0x7f) +#define av1_filt_level2 AV1_DEC_REG(16, 26, 0x3f) + +#define av1_quant_seg3 AV1_DEC_REG(17, 0, 0xff) +#define av1_filt_level_seg3 AV1_DEC_REG(17, 8, 0x3f) +#define av1_skip_seg3 AV1_DEC_REG(17, 14, 0x1) +#define av1_refpic_seg3 AV1_DEC_REG(17, 15, 0xf) +#define av1_filt_level_delta0_seg3 AV1_DEC_REG(17, 19, 0x7f) +#define av1_filt_level3 AV1_DEC_REG(17, 26, 0x3f) + +#define av1_quant_seg4 AV1_DEC_REG(18, 0, 0xff) +#define av1_filt_level_seg4 AV1_DEC_REG(18, 8, 0x3f) +#define av1_skip_seg4 AV1_DEC_REG(18, 14, 0x1) +#define av1_refpic_seg4 AV1_DEC_REG(18, 15, 0xf) +#define av1_filt_level_delta0_seg4 AV1_DEC_REG(18, 19, 0x7f) +#define av1_lr_type AV1_DEC_REG(18, 26, 0x3f) + +#define av1_quant_seg5 AV1_DEC_REG(19, 0, 0xff) +#define av1_filt_level_seg5 AV1_DEC_REG(19, 8, 0x3f) +#define av1_skip_seg5 AV1_DEC_REG(19, 14, 0x1) +#define av1_refpic_seg5 AV1_DEC_REG(19, 15, 0xf) +#define av1_filt_level_delta0_seg5 AV1_DEC_REG(19, 19, 0x7f) +#define av1_lr_unit_size AV1_DEC_REG(19, 26, 0x3f) + +#define av1_filt_level_delta1_seg0 AV1_DEC_REG(20, 0, 0x7f) +#define av1_filt_level_delta2_seg0 AV1_DEC_REG(20, 7, 0x7f) +#define av1_filt_level_delta3_seg0 AV1_DEC_REG(20, 14, 0x7f) +#define av1_global_mv_seg0 AV1_DEC_REG(20, 21, 0x1) +#define av1_mf1_last_offset AV1_DEC_REG(20, 22, 0x1ff) + +#define av1_filt_level_delta1_seg1 AV1_DEC_REG(21, 0, 0x7f) +#define av1_filt_level_delta2_seg1 AV1_DEC_REG(21, 7, 0x7f) +#define av1_filt_level_delta3_seg1 AV1_DEC_REG(21, 14, 0x7f) +#define av1_global_mv_seg1 AV1_DEC_REG(21, 21, 0x1) +#define av1_mf1_last2_offset AV1_DEC_REG(21, 22, 0x1ff) + +#define av1_filt_level_delta1_seg2 AV1_DEC_REG(22, 0, 0x7f) +#define av1_filt_level_delta2_seg2 AV1_DEC_REG(22, 7, 0x7f) +#define av1_filt_level_delta3_seg2 AV1_DEC_REG(22, 14, 0x7f) +#define av1_global_mv_seg2 AV1_DEC_REG(22, 21, 0x1) +#define av1_mf1_last3_offset AV1_DEC_REG(22, 22, 0x1ff) + +#define av1_filt_level_delta1_seg3 AV1_DEC_REG(23, 0, 0x7f) +#define av1_filt_level_delta2_seg3 AV1_DEC_REG(23, 7, 0x7f) +#define av1_filt_level_delta3_seg3 AV1_DEC_REG(23, 14, 0x7f) +#define av1_global_mv_seg3 AV1_DEC_REG(23, 21, 0x1) +#define av1_mf1_golden_offset AV1_DEC_REG(23, 22, 0x1ff) + +#define av1_filt_level_delta1_seg4 AV1_DEC_REG(24, 0, 0x7f) +#define av1_filt_level_delta2_seg4 AV1_DEC_REG(24, 7, 0x7f) +#define av1_filt_level_delta3_seg4 AV1_DEC_REG(24, 14, 0x7f) +#define av1_global_mv_seg4 AV1_DEC_REG(24, 21, 0x1) +#define av1_mf1_bwdref_offset AV1_DEC_REG(24, 22, 0x1ff) + +#define av1_filt_level_delta1_seg5 AV1_DEC_REG(25, 0, 0x7f) +#define av1_filt_level_delta2_seg5 AV1_DEC_REG(25, 7, 0x7f) +#define av1_filt_level_delta3_seg5 AV1_DEC_REG(25, 14, 0x7f) +#define av1_global_mv_seg5 AV1_DEC_REG(25, 21, 0x1) +#define av1_mf1_altref2_offset AV1_DEC_REG(25, 22, 0x1ff) + +#define av1_filt_level_delta1_seg6 AV1_DEC_REG(26, 0, 0x7f) +#define av1_filt_level_delta2_seg6 AV1_DEC_REG(26, 7, 0x7f) +#define av1_filt_level_delta3_seg6 AV1_DEC_REG(26, 14, 0x7f) +#define av1_global_mv_seg6 AV1_DEC_REG(26, 21, 0x1) +#define av1_mf1_altref_offset AV1_DEC_REG(26, 22, 0x1ff) + +#define av1_filt_level_delta1_seg7 AV1_DEC_REG(27, 0, 0x7f) +#define av1_filt_level_delta2_seg7 AV1_DEC_REG(27, 7, 0x7f) +#define av1_filt_level_delta3_seg7 AV1_DEC_REG(27, 14, 0x7f) +#define av1_global_mv_seg7 AV1_DEC_REG(27, 21, 0x1) +#define av1_mf2_last_offset AV1_DEC_REG(27, 22, 0x1ff) + +#define av1_cb_offset AV1_DEC_REG(28, 0, 0x1ff) +#define av1_cb_luma_mult AV1_DEC_REG(28, 9, 0xff) +#define av1_cb_mult AV1_DEC_REG(28, 17, 0xff) +#define av1_quant_delta_v_dc AV1_DEC_REG(28, 25, 0x7f) + +#define av1_cr_offset AV1_DEC_REG(29, 0, 0x1ff) +#define av1_cr_luma_mult AV1_DEC_REG(29, 9, 0xff) +#define av1_cr_mult AV1_DEC_REG(29, 17, 0xff) +#define av1_quant_delta_v_ac AV1_DEC_REG(29, 25, 0x7f) + +#define av1_filt_ref_adj_5 AV1_DEC_REG(30, 0, 0x7f) +#define av1_filt_ref_adj_4 AV1_DEC_REG(30, 7, 0x7f) +#define av1_filt_mb_adj_1 AV1_DEC_REG(30, 14, 0x7f) +#define av1_filt_mb_adj_0 AV1_DEC_REG(30, 21, 0x7f) +#define av1_filt_sharpness AV1_DEC_REG(30, 28, 0x7) + +#define av1_quant_seg6 AV1_DEC_REG(31, 0, 0xff) +#define av1_filt_level_seg6 AV1_DEC_REG(31, 8, 0x3f) +#define av1_skip_seg6 AV1_DEC_REG(31, 14, 0x1) +#define av1_refpic_seg6 AV1_DEC_REG(31, 15, 0xf) +#define av1_filt_level_delta0_seg6 AV1_DEC_REG(31, 19, 0x7f) +#define av1_skip_ref0 AV1_DEC_REG(31, 26, 0xf) + +#define av1_quant_seg7 AV1_DEC_REG(32, 0, 0xff) +#define av1_filt_level_seg7 AV1_DEC_REG(32, 8, 0x3f) +#define av1_skip_seg7 AV1_DEC_REG(32, 14, 0x1) +#define av1_refpic_seg7 AV1_DEC_REG(32, 15, 0xf) +#define av1_filt_level_delta0_seg7 AV1_DEC_REG(32, 19, 0x7f) +#define av1_skip_ref1 AV1_DEC_REG(32, 26, 0xf) + +#define av1_ref0_height AV1_DEC_REG(33, 0, 0xffff) +#define av1_ref0_width AV1_DEC_REG(33, 16, 0xffff) + +#define av1_ref1_height AV1_DEC_REG(34, 0, 0xffff) +#define av1_ref1_width AV1_DEC_REG(34, 16, 0xffff) + +#define av1_ref2_height AV1_DEC_REG(35, 0, 0xffff) +#define av1_ref2_width AV1_DEC_REG(35, 16, 0xffff) + +#define av1_ref0_ver_scale AV1_DEC_REG(36, 0, 0xffff) +#define av1_ref0_hor_scale AV1_DEC_REG(36, 16, 0xffff) + +#define av1_ref1_ver_scale AV1_DEC_REG(37, 0, 0xffff) +#define av1_ref1_hor_scale AV1_DEC_REG(37, 16, 0xffff) + +#define av1_ref2_ver_scale AV1_DEC_REG(38, 0, 0xffff) +#define av1_ref2_hor_scale AV1_DEC_REG(38, 16, 0xffff) + +#define av1_ref3_ver_scale AV1_DEC_REG(39, 0, 0xffff) +#define av1_ref3_hor_scale AV1_DEC_REG(39, 16, 0xffff) + +#define av1_ref4_ver_scale AV1_DEC_REG(40, 0, 0xffff) +#define av1_ref4_hor_scale AV1_DEC_REG(40, 16, 0xffff) + +#define av1_ref5_ver_scale AV1_DEC_REG(41, 0, 0xffff) +#define av1_ref5_hor_scale AV1_DEC_REG(41, 16, 0xffff) + +#define av1_ref6_ver_scale AV1_DEC_REG(42, 0, 0xffff) +#define av1_ref6_hor_scale AV1_DEC_REG(42, 16, 0xffff) + +#define av1_ref3_height AV1_DEC_REG(43, 0, 0xffff) +#define av1_ref3_width AV1_DEC_REG(43, 16, 0xffff) + +#define av1_ref4_height AV1_DEC_REG(44, 0, 0xffff) +#define av1_ref4_width AV1_DEC_REG(44, 16, 0xffff) + +#define av1_ref5_height AV1_DEC_REG(45, 0, 0xffff) +#define av1_ref5_width AV1_DEC_REG(45, 16, 0xffff) + +#define av1_ref6_height AV1_DEC_REG(46, 0, 0xffff) +#define av1_ref6_width AV1_DEC_REG(46, 16, 0xffff) + +#define av1_mf2_last2_offset AV1_DEC_REG(47, 0, 0x1ff) +#define av1_mf2_last3_offset AV1_DEC_REG(47, 9, 0x1ff) +#define av1_mf2_golden_offset AV1_DEC_REG(47, 18, 0x1ff) +#define av1_qmlevel_y AV1_DEC_REG(47, 27, 0xf) + +#define av1_mf2_bwdref_offset AV1_DEC_REG(48, 0, 0x1ff) +#define av1_mf2_altref2_offset AV1_DEC_REG(48, 9, 0x1ff) +#define av1_mf2_altref_offset AV1_DEC_REG(48, 18, 0x1ff) +#define av1_qmlevel_u AV1_DEC_REG(48, 27, 0xf) + +#define av1_filt_ref_adj_6 AV1_DEC_REG(49, 0, 0x7f) +#define av1_filt_ref_adj_7 AV1_DEC_REG(49, 7, 0x7f) +#define av1_qmlevel_v AV1_DEC_REG(49, 14, 0xf) + +#define av1_superres_chroma_step AV1_DEC_REG(51, 0, 0x3fff) +#define av1_superres_luma_step AV1_DEC_REG(51, 14, 0x3fff) + +#define av1_superres_init_chroma_subpel_x AV1_DEC_REG(52, 0, 0x3fff) +#define av1_superres_init_luma_subpel_x AV1_DEC_REG(52, 14, 0x3fff) + +#define av1_cdef_chroma_secondary_strength AV1_DEC_REG(53, 0, 0xffff) +#define av1_cdef_luma_secondary_strength AV1_DEC_REG(53, 16, 0xffff) + +#define av1_apf_threshold AV1_DEC_REG(55, 0, 0xffff) +#define av1_apf_single_pu_mode AV1_DEC_REG(55, 30, 0x1) +#define av1_apf_disable AV1_DEC_REG(55, 30, 0x1) + +#define av1_dec_max_burst AV1_DEC_REG(58, 0, 0xff) +#define av1_dec_buswidth AV1_DEC_REG(58, 8, 0x7) +#define av1_dec_multicore_mode AV1_DEC_REG(58, 11, 0x3) +#define av1_dec_axi_wd_id_e AV1_DEC_REG(58, 13, 0x1) +#define av1_dec_axi_rd_id_e AV1_DEC_REG(58, 14, 0x1) +#define av1_dec_mc_polltime AV1_DEC_REG(58, 17, 0x3ff) +#define av1_dec_mc_pollmode AV1_DEC_REG(58, 27, 0x3) + +#define av1_filt_ref_adj_3 AV1_DEC_REG(59, 0, 0x3f) +#define av1_filt_ref_adj_2 AV1_DEC_REG(59, 7, 0x3f) +#define av1_filt_ref_adj_1 AV1_DEC_REG(59, 14, 0x3f) +#define av1_filt_ref_adj_0 AV1_DEC_REG(59, 21, 0x3f) +#define av1_ref0_sign_bias AV1_DEC_REG(59, 28, 0x1) +#define av1_ref1_sign_bias AV1_DEC_REG(59, 29, 0x1) +#define av1_ref2_sign_bias AV1_DEC_REG(59, 30, 0x1) +#define av1_ref3_sign_bias AV1_DEC_REG(59, 31, 0x1) + +#define av1_cur_last_roffset AV1_DEC_REG(184, 0, 0x1ff) +#define av1_cur_last_offset AV1_DEC_REG(184, 9, 0x1ff) +#define av1_mf3_last_offset AV1_DEC_REG(184, 18, 0x1ff) +#define av1_ref0_gm_mode AV1_DEC_REG(184, 27, 0x3) + +#define av1_cur_last2_roffset AV1_DEC_REG(185, 0, 0x1ff) +#define av1_cur_last2_offset AV1_DEC_REG(185, 9, 0x1ff) +#define av1_mf3_last2_offset AV1_DEC_REG(185, 18, 0x1ff) +#define av1_ref1_gm_mode AV1_DEC_REG(185, 27, 0x3) + +#define av1_cur_last3_roffset AV1_DEC_REG(186, 0, 0x1ff) +#define av1_cur_last3_offset AV1_DEC_REG(186, 9, 0x1ff) +#define av1_mf3_last3_offset AV1_DEC_REG(186, 18, 0x1ff) +#define av1_ref2_gm_mode AV1_DEC_REG(186, 27, 0x3) + +#define av1_cur_golden_roffset AV1_DEC_REG(187, 0, 0x1ff) +#define av1_cur_golden_offset AV1_DEC_REG(187, 9, 0x1ff) +#define av1_mf3_golden_offset AV1_DEC_REG(187, 18, 0x1ff) +#define av1_ref3_gm_mode AV1_DEC_REG(187, 27, 0x3) + +#define av1_cur_bwdref_roffset AV1_DEC_REG(188, 0, 0x1ff) +#define av1_cur_bwdref_offset AV1_DEC_REG(188, 9, 0x1ff) +#define av1_mf3_bwdref_offset AV1_DEC_REG(188, 18, 0x1ff) +#define av1_ref4_gm_mode AV1_DEC_REG(188, 27, 0x3) + +#define av1_cur_altref2_roffset AV1_DEC_REG(257, 0, 0x1ff) +#define av1_cur_altref2_offset AV1_DEC_REG(257, 9, 0x1ff) +#define av1_mf3_altref2_offset AV1_DEC_REG(257, 18, 0x1ff) +#define av1_ref5_gm_mode AV1_DEC_REG(257, 27, 0x3) + +#define av1_strm_buffer_len AV1_DEC_REG(258, 0, 0xffffffff) + +#define av1_strm_start_offset AV1_DEC_REG(259, 0, 0xffffffff) + +#define av1_ppd_blend_exist AV1_DEC_REG(260, 21, 0x1) +#define av1_ppd_dith_exist AV1_DEC_REG(260, 23, 0x1) +#define av1_ablend_crop_e AV1_DEC_REG(260, 24, 0x1) +#define av1_pp_format_p010_e AV1_DEC_REG(260, 25, 0x1) +#define av1_pp_format_customer1_e AV1_DEC_REG(260, 26, 0x1) +#define av1_pp_crop_exist AV1_DEC_REG(260, 27, 0x1) +#define av1_pp_up_level AV1_DEC_REG(260, 28, 0x1) +#define av1_pp_down_level AV1_DEC_REG(260, 29, 0x3) +#define av1_pp_exist AV1_DEC_REG(260, 31, 0x1) + +#define av1_cur_altref_roffset AV1_DEC_REG(262, 0, 0x1ff) +#define av1_cur_altref_offset AV1_DEC_REG(262, 9, 0x1ff) +#define av1_mf3_altref_offset AV1_DEC_REG(262, 18, 0x1ff) +#define av1_ref6_gm_mode AV1_DEC_REG(262, 27, 0x3) + +#define av1_cdef_luma_primary_strength AV1_DEC_REG(263, 0, 0xffffffff) + +#define av1_cdef_chroma_primary_strength AV1_DEC_REG(264, 0, 0xffffffff) + +#define av1_axi_arqos AV1_DEC_REG(265, 0, 0xf) +#define av1_axi_awqos AV1_DEC_REG(265, 4, 0xf) +#define av1_axi_wr_ostd_threshold AV1_DEC_REG(265, 8, 0x3ff) +#define av1_axi_rd_ostd_threshold AV1_DEC_REG(265, 18, 0x3ff) +#define av1_axi_wr_4k_dis AV1_DEC_REG(265, 31, 0x1) + +#define av1_128bit_mode AV1_DEC_REG(266, 5, 0x1) +#define av1_wr_shaper_bypass AV1_DEC_REG(266, 10, 0x1) +#define av1_error_conceal_e AV1_DEC_REG(266, 30, 0x1) + +#define av1_superres_chroma_step_invra AV1_DEC_REG(298, 0, 0xffff) +#define av1_superres_luma_step_invra AV1_DEC_REG(298, 16, 0xffff) + +#define av1_dec_alignment AV1_DEC_REG(314, 0, 0xffff) + +#define av1_ext_timeout_cycles AV1_DEC_REG(318, 0, 0x7fffffff) +#define av1_ext_timeout_override_e AV1_DEC_REG(318, 31, 0x1) + +#define av1_timeout_cycles AV1_DEC_REG(319, 0, 0x7fffffff) +#define av1_timeout_override_e AV1_DEC_REG(319, 31, 0x1) + +#define av1_pp_out_e AV1_DEC_REG(320, 0, 0x1) +#define av1_pp_cr_first AV1_DEC_REG(320, 1, 0x1) +#define av1_pp_out_mode AV1_DEC_REG(320, 2, 0x1) +#define av1_pp_out_tile_e AV1_DEC_REG(320, 3, 0x1) +#define av1_pp_status AV1_DEC_REG(320, 4, 0xf) +#define av1_pp_in_blk_size AV1_DEC_REG(320, 8, 0x7) +#define av1_pp_out_p010_fmt AV1_DEC_REG(320, 11, 0x3) +#define av1_pp_out_rgb_fmt AV1_DEC_REG(320, 13, 0x1f) +#define av1_rgb_range_max AV1_DEC_REG(320, 18, 0xfff) +#define av1_pp_rgb_planar AV1_DEC_REG(320, 30, 0x1) + +#define av1_scale_hratio AV1_DEC_REG(322, 0, 0x3ffff) +#define av1_pp_out_format AV1_DEC_REG(322, 18, 0x1f) +#define av1_ver_scale_mode AV1_DEC_REG(322, 23, 0x3) +#define av1_hor_scale_mode AV1_DEC_REG(322, 25, 0x3) +#define av1_pp_in_format AV1_DEC_REG(322, 27, 0x1f) + +#define av1_pp_out_c_stride AV1_DEC_REG(329, 0, 0xffff) +#define av1_pp_out_y_stride AV1_DEC_REG(329, 16, 0xffff) + +#define av1_pp_in_height AV1_DEC_REG(331, 0, 0xffff) +#define av1_pp_in_width AV1_DEC_REG(331, 16, 0xffff) + +#define av1_pp_out_height AV1_DEC_REG(332, 0, 0xffff) +#define av1_pp_out_width AV1_DEC_REG(332, 16, 0xffff) + +#define av1_pp1_dup_ver AV1_DEC_REG(394, 0, 0xff) +#define av1_pp1_dup_hor AV1_DEC_REG(394, 8, 0xff) +#define av1_pp0_dup_ver AV1_DEC_REG(394, 16, 0xff) +#define av1_pp0_dup_hor AV1_DEC_REG(394, 24, 0xff) + +#define AV1_TILE_OUT_LU (AV1_SWREG(65)) +#define AV1_REFERENCE_Y(i) (AV1_SWREG(67) + ((i) * 0x8)) +#define AV1_SEGMENTATION (AV1_SWREG(81)) +#define AV1_GLOBAL_MODEL (AV1_SWREG(83)) +#define AV1_CDEF_COL (AV1_SWREG(85)) +#define AV1_SR_COL (AV1_SWREG(89)) +#define AV1_LR_COL (AV1_SWREG(91)) +#define AV1_FILM_GRAIN (AV1_SWREG(95)) +#define AV1_TILE_OUT_CH (AV1_SWREG(99)) +#define AV1_REFERENCE_CB(i) (AV1_SWREG(101) + ((i) * 0x8)) +#define AV1_TILE_OUT_MV (AV1_SWREG(133)) +#define AV1_REFERENCE_MV(i) (AV1_SWREG(135) + ((i) * 0x8)) +#define AV1_TILE_BASE (AV1_SWREG(167)) +#define AV1_INPUT_STREAM (AV1_SWREG(169)) +#define AV1_PROP_TABLE_OUT (AV1_SWREG(171)) +#define AV1_PROP_TABLE (AV1_SWREG(173)) +#define AV1_MC_SYNC_CURR (AV1_SWREG(175)) +#define AV1_MC_SYNC_LEFT (AV1_SWREG(177)) +#define AV1_DB_DATA_COL (AV1_SWREG(179)) +#define AV1_DB_CTRL_COL (AV1_SWREG(183)) +#define AV1_PP_OUT_LU (AV1_SWREG(326)) +#define AV1_PP_OUT_CH (AV1_SWREG(328)) + +#endif /* _ROCKCHIP_VPU981_REGS_H_ */ diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c index 8de6fd2e8eef..816ffa905a4b 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c @@ -13,9 +13,13 @@ #include "hantro_g1_regs.h" #include "hantro_h1_regs.h" #include "rockchip_vpu2_regs.h" +#include "rockchip_vpu981_regs.h" #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) +#define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000) + +#define ROCKCHIP_VPU981_MIN_SIZE 64 /* * Supported formats. @@ -74,6 +78,37 @@ static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = { }, }; +static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, + .postprocessed = true, + .frmsize = { + .min_width = ROCKCHIP_VPU981_MIN_SIZE, + .max_width = FMT_UHD_WIDTH, + .step_width = MB_DIM, + .min_height = ROCKCHIP_VPU981_MIN_SIZE, + .max_height = FMT_UHD_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_P010, + .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, + .postprocessed = true, + .frmsize = { + .min_width = ROCKCHIP_VPU981_MIN_SIZE, + .max_width = FMT_UHD_WIDTH, + .step_width = MB_DIM, + .min_height = ROCKCHIP_VPU981_MIN_SIZE, + .max_height = FMT_UHD_HEIGHT, + .step_height = MB_DIM, + }, + }, +}; + static const struct hantro_fmt rk3066_vpu_dec_fmts[] = { { .fourcc = V4L2_PIX_FMT_NV12, @@ -277,6 +312,48 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { }, }; +static const struct hantro_fmt rockchip_vpu981_dec_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12_4L4, + .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, + .frmsize = { + .min_width = ROCKCHIP_VPU981_MIN_SIZE, + .max_width = FMT_UHD_WIDTH, + .step_width = MB_DIM, + .min_height = ROCKCHIP_VPU981_MIN_SIZE, + .max_height = FMT_UHD_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_NV15_4L4, + .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, + .frmsize = { + .min_width = ROCKCHIP_VPU981_MIN_SIZE, + .max_width = FMT_UHD_WIDTH, + .step_width = MB_DIM, + .min_height = ROCKCHIP_VPU981_MIN_SIZE, + .max_height = FMT_UHD_HEIGHT, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_AV1_FRAME, + .codec_mode = HANTRO_MODE_AV1_DEC, + .max_depth = 2, + .frmsize = { + .min_width = ROCKCHIP_VPU981_MIN_SIZE, + .max_width = FMT_UHD_WIDTH, + .step_width = MB_DIM, + .min_height = ROCKCHIP_VPU981_MIN_SIZE, + .max_height = FMT_UHD_HEIGHT, + .step_height = MB_DIM, + }, + }, +}; + static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id) { struct hantro_dev *vpu = dev_id; @@ -331,6 +408,24 @@ static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id) return IRQ_HANDLED; } +static irqreturn_t rk3588_vpu981_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status; + + status = vdpu_read(vpu, AV1_REG_INTERRUPT); + state = (status & AV1_REG_INTERRUPT_DEC_RDY_INT) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vdpu_write(vpu, 0, AV1_REG_INTERRUPT); + vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} + static int rk3036_vpu_hw_init(struct hantro_dev *vpu) { /* Bump ACLK to max. possible freq. to improve performance. */ @@ -346,6 +441,13 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) return 0; } +static int rk3588_vpu981_hw_init(struct hantro_dev *vpu) +{ + /* Bump ACLKs to max. possible freq. to improve performance. */ + clk_set_rate(vpu->clocks[0].clk, RK3588_ACLK_MAX_FREQ); + return 0; +} + static int rockchip_vpu_hw_init(struct hantro_dev *vpu) { /* Bump ACLK to max. possible freq. to improve performance. */ @@ -498,6 +600,14 @@ static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = { }, }; +static const struct hantro_codec_ops rk3588_vpu981_codec_ops[] = { + [HANTRO_MODE_AV1_DEC] = { + .run = rockchip_vpu981_av1_dec_run, + .init = rockchip_vpu981_av1_dec_init, + .exit = rockchip_vpu981_av1_dec_exit, + .done = rockchip_vpu981_av1_dec_done, + }, +}; /* * VPU variant. */ @@ -529,10 +639,18 @@ static const char * const rk3066_vpu_clk_names[] = { "aclk_vepu", "hclk_vepu" }; +static const struct hantro_irq rk3588_vpu981_irqs[] = { + { "vdpu", rk3588_vpu981_irq }, +}; + static const char * const rockchip_vpu_clk_names[] = { "aclk", "hclk" }; +static const char * const rk3588_vpu981_vpu_clk_names[] = { + "aclk", "hclk", "aclk_vdpu_root", "hclk_vdpu_root" +}; + /* VDPU1/VEPU1 */ const struct hantro_variant rk3036_vpu_variant = { @@ -678,3 +796,19 @@ const struct hantro_variant px30_vpu_variant = { .clk_names = rockchip_vpu_clk_names, .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; + +const struct hantro_variant rk3588_vpu981_variant = { + .dec_offset = 0x0, + .dec_fmts = rockchip_vpu981_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(rockchip_vpu981_dec_fmts), + .postproc_fmts = rockchip_vpu981_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu981_postproc_fmts), + .postproc_ops = &rockchip_vpu981_postproc_ops, + .codec = HANTRO_AV1_DECODER, + .codec_ops = rk3588_vpu981_codec_ops, + .irqs = rk3588_vpu981_irqs, + .num_irqs = ARRAY_SIZE(rk3588_vpu981_irqs), + .init = rk3588_vpu981_hw_init, + .clk_names = rk3588_vpu981_vpu_clk_names, + .num_clocks = ARRAY_SIZE(rk3588_vpu981_vpu_clk_names) +}; diff --git a/drivers/media/platform/via/via-camera.c b/drivers/media/platform/via/via-camera.c index 450254403fa8..4cb8f29e2f14 100644 --- a/drivers/media/platform/via/via-camera.c +++ b/drivers/media/platform/via/via-camera.c @@ -11,7 +11,7 @@ #include <linux/device.h> #include <linux/list.h> #include <linux/pci.h> -#include <linux/gpio.h> +#include <linux/gpio/consumer.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/videodev2.h> @@ -26,7 +26,6 @@ #include <linux/dma-mapping.h> #include <linux/pm_qos.h> #include <linux/via-core.h> -#include <linux/via-gpio.h> #include <linux/via_i2c.h> #ifdef CONFIG_X86 @@ -71,8 +70,8 @@ struct via_camera { /* * GPIO info for power/reset management */ - int power_gpio; - int reset_gpio; + struct gpio_desc *power_gpio; + struct gpio_desc *reset_gpio; /* * I/O memory stuff. */ @@ -180,27 +179,19 @@ static struct via_format *via_find_format(u32 pixelformat) */ static int via_sensor_power_setup(struct via_camera *cam) { - int ret; + struct device *dev = &cam->platdev->dev; + + cam->power_gpio = devm_gpiod_get(dev, "VGPIO3", GPIOD_OUT_LOW); + if (IS_ERR(cam->power_gpio)) + return dev_err_probe(dev, PTR_ERR(cam->power_gpio), + "failed to get power GPIO"); + + /* Request the reset line asserted */ + cam->reset_gpio = devm_gpiod_get(dev, "VGPIO2", GPIOD_OUT_HIGH); + if (IS_ERR(cam->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(cam->reset_gpio), + "failed to get reset GPIO"); - cam->power_gpio = viafb_gpio_lookup("VGPIO3"); - cam->reset_gpio = viafb_gpio_lookup("VGPIO2"); - if (!gpio_is_valid(cam->power_gpio) || !gpio_is_valid(cam->reset_gpio)) { - dev_err(&cam->platdev->dev, "Unable to find GPIO lines\n"); - return -EINVAL; - } - ret = gpio_request(cam->power_gpio, "viafb-camera"); - if (ret) { - dev_err(&cam->platdev->dev, "Unable to request power GPIO\n"); - return ret; - } - ret = gpio_request(cam->reset_gpio, "viafb-camera"); - if (ret) { - dev_err(&cam->platdev->dev, "Unable to request reset GPIO\n"); - gpio_free(cam->power_gpio); - return ret; - } - gpio_direction_output(cam->power_gpio, 0); - gpio_direction_output(cam->reset_gpio, 0); return 0; } @@ -209,25 +200,23 @@ static int via_sensor_power_setup(struct via_camera *cam) */ static void via_sensor_power_up(struct via_camera *cam) { - gpio_set_value(cam->power_gpio, 1); - gpio_set_value(cam->reset_gpio, 0); + gpiod_set_value(cam->power_gpio, 1); + gpiod_set_value(cam->reset_gpio, 1); msleep(20); /* Probably excessive */ - gpio_set_value(cam->reset_gpio, 1); + gpiod_set_value(cam->reset_gpio, 0); msleep(20); } static void via_sensor_power_down(struct via_camera *cam) { - gpio_set_value(cam->power_gpio, 0); - gpio_set_value(cam->reset_gpio, 0); + gpiod_set_value(cam->power_gpio, 0); + gpiod_set_value(cam->reset_gpio, 1); } static void via_sensor_power_release(struct via_camera *cam) { via_sensor_power_down(cam); - gpio_free(cam->power_gpio); - gpio_free(cam->reset_gpio); } /* --------------------------------------------------------------------------*/ diff --git a/drivers/media/platform/video-mux.c b/drivers/media/platform/video-mux.c index 1d9f32e5a917..6d273abfe16c 100644 --- a/drivers/media/platform/video-mux.c +++ b/drivers/media/platform/video-mux.c @@ -24,7 +24,6 @@ struct video_mux { struct v4l2_subdev subdev; struct v4l2_async_notifier notifier; struct media_pad *pads; - struct v4l2_mbus_framefmt *format_mbus; struct mux_control *mux; struct mutex lock; int active; @@ -71,6 +70,9 @@ static int video_mux_link_setup(struct media_entity *entity, mutex_lock(&vmux->lock); if (flags & MEDIA_LNK_FL_ENABLED) { + struct v4l2_subdev_state *sd_state; + struct v4l2_mbus_framefmt *source_mbusformat; + if (vmux->active == local->index) goto out; @@ -86,7 +88,12 @@ static int video_mux_link_setup(struct media_entity *entity, vmux->active = local->index; /* Propagate the active format to the source */ - vmux->format_mbus[source_pad] = vmux->format_mbus[vmux->active]; + sd_state = v4l2_subdev_lock_and_get_active_state(sd); + source_mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, + source_pad); + *source_mbusformat = *v4l2_subdev_get_pad_format(sd, sd_state, + vmux->active); + v4l2_subdev_unlock_state(sd_state); } else { if (vmux->active != local->index) goto out; @@ -138,40 +145,6 @@ static const struct v4l2_subdev_video_ops video_mux_subdev_video_ops = { .s_stream = video_mux_s_stream, }; -static struct v4l2_mbus_framefmt * -__video_mux_get_pad_format(struct v4l2_subdev *sd, - struct v4l2_subdev_state *sd_state, - unsigned int pad, u32 which) -{ - struct video_mux *vmux = v4l2_subdev_to_video_mux(sd); - - switch (which) { - case V4L2_SUBDEV_FORMAT_TRY: - return v4l2_subdev_get_try_format(sd, sd_state, pad); - case V4L2_SUBDEV_FORMAT_ACTIVE: - return &vmux->format_mbus[pad]; - default: - return NULL; - } -} - -static int video_mux_get_format(struct v4l2_subdev *sd, - struct v4l2_subdev_state *sd_state, - struct v4l2_subdev_format *sdformat) -{ - struct video_mux *vmux = v4l2_subdev_to_video_mux(sd); - - mutex_lock(&vmux->lock); - - sdformat->format = *__video_mux_get_pad_format(sd, sd_state, - sdformat->pad, - sdformat->which); - - mutex_unlock(&vmux->lock); - - return 0; -} - static int video_mux_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *sdformat) @@ -181,14 +154,11 @@ static int video_mux_set_format(struct v4l2_subdev *sd, struct media_pad *pad = &vmux->pads[sdformat->pad]; u16 source_pad = sd->entity.num_pads - 1; - mbusformat = __video_mux_get_pad_format(sd, sd_state, sdformat->pad, - sdformat->which); + mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad); if (!mbusformat) return -EINVAL; - source_mbusformat = __video_mux_get_pad_format(sd, sd_state, - source_pad, - sdformat->which); + source_mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, source_pad); if (!source_mbusformat) return -EINVAL; @@ -298,7 +268,8 @@ static int video_mux_set_format(struct v4l2_subdev *sd, /* Source pad mirrors active sink pad, no limitations on sink pads */ if ((pad->flags & MEDIA_PAD_FL_SOURCE) && vmux->active >= 0) - sdformat->format = vmux->format_mbus[vmux->active]; + sdformat->format = *v4l2_subdev_get_pad_format(sd, sd_state, + vmux->active); *mbusformat = sdformat->format; @@ -321,7 +292,7 @@ static int video_mux_init_cfg(struct v4l2_subdev *sd, mutex_lock(&vmux->lock); for (i = 0; i < sd->entity.num_pads; i++) { - mbusformat = v4l2_subdev_get_try_format(sd, sd_state, i); + mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, i); *mbusformat = video_mux_format_mbus_default; } @@ -332,7 +303,7 @@ static int video_mux_init_cfg(struct v4l2_subdev *sd, static const struct v4l2_subdev_pad_ops video_mux_pad_ops = { .init_cfg = video_mux_init_cfg, - .get_fmt = video_mux_get_format, + .get_fmt = v4l2_subdev_get_fmt, .set_fmt = video_mux_set_format, }; @@ -389,7 +360,7 @@ static int video_mux_async_register(struct video_mux *vmux, ret = PTR_ERR(asd); /* OK if asd already exists */ if (ret != -EEXIST) - return ret; + goto err_nf_cleanup; } } @@ -397,9 +368,19 @@ static int video_mux_async_register(struct video_mux *vmux, ret = v4l2_async_subdev_nf_register(&vmux->subdev, &vmux->notifier); if (ret) - return ret; + goto err_nf_cleanup; + + ret = v4l2_async_register_subdev(&vmux->subdev); + if (ret) + goto err_nf_unregister; - return v4l2_async_register_subdev(&vmux->subdev); + return 0; + +err_nf_unregister: + v4l2_async_nf_unregister(&vmux->notifier); +err_nf_cleanup: + v4l2_async_nf_cleanup(&vmux->notifier); + return ret; } static int video_mux_probe(struct platform_device *pdev) @@ -452,17 +433,9 @@ static int video_mux_probe(struct platform_device *pdev) if (!vmux->pads) return -ENOMEM; - vmux->format_mbus = devm_kcalloc(dev, num_pads, - sizeof(*vmux->format_mbus), - GFP_KERNEL); - if (!vmux->format_mbus) - return -ENOMEM; - - for (i = 0; i < num_pads; i++) { + for (i = 0; i < num_pads; i++) vmux->pads[i].flags = (i < num_pads - 1) ? MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE; - vmux->format_mbus[i] = video_mux_format_mbus_default; - } vmux->subdev.entity.function = MEDIA_ENT_F_VID_MUX; ret = media_entity_pads_init(&vmux->subdev.entity, num_pads, @@ -472,12 +445,20 @@ static int video_mux_probe(struct platform_device *pdev) vmux->subdev.entity.ops = &video_mux_ops; + ret = v4l2_subdev_init_finalize(&vmux->subdev); + if (ret < 0) + goto err_entity_cleanup; + ret = video_mux_async_register(vmux, num_pads - 1); - if (ret) { - v4l2_async_nf_unregister(&vmux->notifier); - v4l2_async_nf_cleanup(&vmux->notifier); - } + if (ret) + goto err_subdev_cleanup; + + return 0; +err_subdev_cleanup: + v4l2_subdev_cleanup(&vmux->subdev); +err_entity_cleanup: + media_entity_cleanup(&vmux->subdev.entity); return ret; } @@ -489,6 +470,7 @@ static void video_mux_remove(struct platform_device *pdev) v4l2_async_nf_unregister(&vmux->notifier); v4l2_async_nf_cleanup(&vmux->notifier); v4l2_async_unregister_subdev(sd); + v4l2_subdev_cleanup(sd); media_entity_cleanup(&sd->entity); } |