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authorMiquel Raynal <miquel.raynal@bootlin.com>2024-03-15 14:00:45 +0300
committerMiquel Raynal <miquel.raynal@bootlin.com>2024-03-15 14:00:45 +0300
commit09888e973cc9d3615dbab5d178eecb58d8a0b7ab (patch)
treef2728f4e4fd45f7ab5d9fed920f87724598e812e /drivers/mtd/nand/raw/lpc32xx_mlc.c
parent2842dc9bc1a53893eec62ec9e49beb3b501702d0 (diff)
parent4120aa0e3961f68f1f8cfe6b4c3c809ffea31fdc (diff)
downloadlinux-09888e973cc9d3615dbab5d178eecb58d8a0b7ab.tar.xz
Merge tag 'nand/for-6.9' into mtd/next
Raw NAND The main series brought is an update of the Broadcom support to support all BCMBCA SoCs and their specificity (ECC, write protection, configuration straps), plus a few misc fixes and changes in the main driver. Device tree updates are also part of this PR, initially because of a misunderstanding on my side. The STM32_FMC2 controller driver is also upgraded to properly support MP1 and MP25 SoCs. A new compatible is added for an Atmel flavor. Among all these feature changes, there is as well a load of continuous read related fixes, avoiding more corner conditions and clarifying the logic. Finally a few miscellaneous fixes are made to the core, the lpx32xx_mlc, fsl_lbc, Meson and Atmel controller driver, as well as final one in the Hynix vendor driver. SPI-NAND The ESMT support has been extended to match 5 bytes ID to avoid collisions. Winbond support on its side receives support for W25N04KV chips.
Diffstat (limited to 'drivers/mtd/nand/raw/lpc32xx_mlc.c')
-rw-r--r--drivers/mtd/nand/raw/lpc32xx_mlc.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/mtd/nand/raw/lpc32xx_mlc.c b/drivers/mtd/nand/raw/lpc32xx_mlc.c
index 488fd452611a..677fcb03f9be 100644
--- a/drivers/mtd/nand/raw/lpc32xx_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_mlc.c
@@ -303,8 +303,9 @@ static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip)
return 0;
}
-static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host)
+static irqreturn_t lpc3xxx_nand_irq(int irq, void *data)
{
+ struct lpc32xx_nand_host *host = data;
uint8_t sr;
/* Clear interrupt flag by reading status */
@@ -780,7 +781,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
goto release_dma_chan;
}
- if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq,
+ if (request_irq(host->irq, &lpc3xxx_nand_irq,
IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
res = -ENXIO;