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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2024-03-15 14:00:45 +0300 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2024-03-15 14:00:45 +0300 |
| commit | 09888e973cc9d3615dbab5d178eecb58d8a0b7ab (patch) | |
| tree | f2728f4e4fd45f7ab5d9fed920f87724598e812e /drivers/mtd/nand/spi/esmt.c | |
| parent | 2842dc9bc1a53893eec62ec9e49beb3b501702d0 (diff) | |
| parent | 4120aa0e3961f68f1f8cfe6b4c3c809ffea31fdc (diff) | |
| download | linux-09888e973cc9d3615dbab5d178eecb58d8a0b7ab.tar.xz | |
Merge tag 'nand/for-6.9' into mtd/next
Raw NAND
The main series brought is an update of the Broadcom support to support
all BCMBCA SoCs and their specificity (ECC, write protection,
configuration straps), plus a few misc fixes and changes in the main
driver. Device tree updates are also part of this PR, initially because
of a misunderstanding on my side.
The STM32_FMC2 controller driver is also upgraded to properly support
MP1 and MP25 SoCs.
A new compatible is added for an Atmel flavor.
Among all these feature changes, there is as well a load of continuous
read related fixes, avoiding more corner conditions and clarifying the
logic. Finally a few miscellaneous fixes are made to the core, the
lpx32xx_mlc, fsl_lbc, Meson and Atmel controller driver, as well as
final one in the Hynix vendor driver.
SPI-NAND
The ESMT support has been extended to match 5 bytes ID to avoid
collisions. Winbond support on its side receives support for W25N04KV
chips.
Diffstat (limited to 'drivers/mtd/nand/spi/esmt.c')
| -rw-r--r-- | drivers/mtd/nand/spi/esmt.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c index 31c439a557b1..4597a82de23a 100644 --- a/drivers/mtd/nand/spi/esmt.c +++ b/drivers/mtd/nand/spi/esmt.c @@ -104,7 +104,8 @@ static const struct mtd_ooblayout_ops f50l1g41lb_ooblayout = { static const struct spinand_info esmt_c8_spinand_table[] = { SPINAND_INFO("F50L1G41LB", - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f, + 0x7f, 0x7f), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -113,7 +114,8 @@ static const struct spinand_info esmt_c8_spinand_table[] = { 0, SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), SPINAND_INFO("F50D1G41LB", - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11), + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11, 0x7f, + 0x7f, 0x7f), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -122,7 +124,8 @@ static const struct spinand_info esmt_c8_spinand_table[] = { 0, SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), SPINAND_INFO("F50D2G41KA", - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51), + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51, 0x7f, + 0x7f, 0x7f), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |