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authorDoug Berger <opendmb@gmail.com>2020-04-29 23:02:02 +0300
committerDavid S. Miller <davem@davemloft.net>2020-04-30 02:55:22 +0300
commit1a1d5106c1e37321f3fe394b786d1aece56d0df5 (patch)
tree494789d35155849519b848b63a5bba0a12e1ccf5 /drivers/net/ethernet/broadcom/genet/bcmgenet.h
parent6f7689057a0f10a6c967b9f2759d7a3dc948b930 (diff)
downloadlinux-1a1d5106c1e37321f3fe394b786d1aece56d0df5.tar.xz
net: bcmgenet: move clk_wol management to bcmgenet_wol
The GENET_POWER_WOL_MAGIC power up and power down code configures the device for WoL when suspending and disables the WoL logic when resuming. It makes sense that this code should also manage the WoL clocking. This commit consolidates the logic and moves it earlier in the resume sequence. Since the clock is now only enabled if WoL is successfully entered the wol_active flag is introduced to track that state to keep the clock enables and disables balanced in case a suspend is aborted. The MPD_EN hardware bit can't be used because it can be cleared when the MAC is reset by a deep sleep. Signed-off-by: Doug Berger <opendmb@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/genet/bcmgenet.h')
-rw-r--r--drivers/net/ethernet/broadcom/genet/bcmgenet.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.h b/drivers/net/ethernet/broadcom/genet/bcmgenet.h
index c3bfe97f2e5c..a858b7305832 100644
--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.h
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2014-2017 Broadcom
+ * Copyright (c) 2014-2020 Broadcom
*/
#ifndef __BCMGENET_H__
@@ -678,6 +678,7 @@ struct bcmgenet_priv {
struct clk *clk_wol;
u32 wolopts;
u8 sopass[SOPASS_MAX];
+ bool wol_active;
struct bcmgenet_mib_counters mib;