diff options
| author | Hariprasad Kelam <hkelam@marvell.com> | 2022-12-05 10:05:19 +0300 |
|---|---|---|
| committer | Paolo Abeni <pabeni@redhat.com> | 2022-12-07 14:24:29 +0300 |
| commit | b9d0fedc6234011d67f6e2ba0ae1a8de6beca010 (patch) | |
| tree | 75c9f738563277709baa6040ce161c1c1aa7f947 /drivers/net/ethernet/marvell/octeontx2/af/cgx.h | |
| parent | f2e664ad503d4e5ce7c42a0862ab164331a0ef37 (diff) | |
| download | linux-b9d0fedc6234011d67f6e2ba0ae1a8de6beca010.tar.xz | |
octeontx2-af: cn10kb: Add RPM_USX MAC support
OcteonTx2's next gen platform the CN10KB has RPM_USX MAC which has a
different serdes when compared to RPM MAC. Though the underlying
HW is different, the CSR interface has been designed largely inline
with RPM MAC, with few exceptions though. So we are using the same
CGX driver for RPM_USX MAC as well and will have a different set of APIs
for RPM_USX where ever necessary.
The RPM and RPM_USX blocks support a different number of LMACS.
RPM_USX support 8 LMACS per MAC block whereas legacy RPM supports only 4
LMACS per MAC. with this RPM_USX support double the number of DMAC filters
and fifo size.
This patch adds initial support for CN10KB's RPM_USX MAC i.e registering
the driver and defining MAC operations (mac_ops). Adds the logic to
configure internal loopback and pause frames and assign FIFO length to
LMACS.
Kernel reads lmac features like lmac type, autoneg, etc from shared
firmware data this structure only supports 4 lmacs per MAC, this patch
extends this structure to accommodate 8 lmacs.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/cgx.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/af/cgx.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h index ce66c7271e3a..fb2d37676d84 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h @@ -19,7 +19,6 @@ #define PCI_CFG_REG_BAR_NUM 0 #define CGX_ID_MASK 0xF -#define MAX_DMAC_ENTRIES_PER_CGX 32 /* Registers */ #define CGXX_CMRX_CFG 0x00 @@ -53,7 +52,7 @@ #define CGXX_SCRATCH0_REG 0x1050 #define CGXX_SCRATCH1_REG 0x1058 #define CGX_CONST 0x2000 -#define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(23, 0) +#define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(55, 32) #define CGX_CONST_MAX_LMACS GENMASK_ULL(31, 24) #define CGXX_SPUX_CONTROL1 0x10000 #define CGXX_SPUX_LNX_FEC_CORR_BLOCKS 0x10700 |