diff options
| author | Sunil Goutham <sgoutham@marvell.com> | 2018-10-10 15:44:28 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-10-10 20:06:02 +0300 |
| commit | 746ea74241fa04f7a8c3146adc08b618d88681e2 (patch) | |
| tree | 0e3223980e84906fcb6112cba6ab1df3cab501b6 /drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h | |
| parent | 114a767e8b24bf5d5be5101c1713ff2eb0149657 (diff) | |
| download | linux-746ea74241fa04f7a8c3146adc08b618d88681e2.tar.xz | |
octeontx2-af: Add RVU block LF provisioning support
Added support for a RVU PF/VF to request AF via mailbox
to attach or detach NPA/NIX/SSO/SSOW/TIM/CPT block LFs.
Also supports partial detachment and modifying current
LF attached count of a certian block type.
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h index 0d69ec0c03f0..d871a394e72b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h @@ -54,20 +54,20 @@ #define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110 | (a) << 16) #define RVU_PRIV_PFX_ID_CFG(a) (0x8000120 | (a) << 16) #define RVU_PRIV_PFX_INT_CFG(a) (0x8000200 | (a) << 16) -#define RVU_PRIV_PFX_NIX_CFG (0x8000300) +#define RVU_PRIV_PFX_NIX0_CFG (0x8000300) #define RVU_PRIV_PFX_NPA_CFG (0x8000310) #define RVU_PRIV_PFX_SSO_CFG (0x8000320) #define RVU_PRIV_PFX_SSOW_CFG (0x8000330) #define RVU_PRIV_PFX_TIM_CFG (0x8000340) -#define RVU_PRIV_PFX_CPT_CFG (0x8000350) +#define RVU_PRIV_PFX_CPT0_CFG (0x8000350) #define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400 | (a) << 3) #define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280 | (a) << 16) -#define RVU_PRIV_HWVFX_NIX_CFG (0x8001300) +#define RVU_PRIV_HWVFX_NIX0_CFG (0x8001300) #define RVU_PRIV_HWVFX_NPA_CFG (0x8001310) #define RVU_PRIV_HWVFX_SSO_CFG (0x8001320) #define RVU_PRIV_HWVFX_SSOW_CFG (0x8001330) #define RVU_PRIV_HWVFX_TIM_CFG (0x8001340) -#define RVU_PRIV_HWVFX_CPT_CFG (0x8001350) +#define RVU_PRIV_HWVFX_CPT0_CFG (0x8001350) /* RVU PF registers */ #define RVU_PF_VFX_PFVF_MBOX0 (0x00000) |