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authorSunil Goutham <sgoutham@marvell.com>2021-07-30 14:49:14 +0300
committerDavid S. Miller <davem@davemloft.net>2021-08-02 12:47:12 +0300
commitc39830a4ce4df09ddef29ac388b062537c559228 (patch)
tree3f3b397fadd51f98f12b7d4afbc06027fcbec95d /drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h
parent76660df2b4a264519afef1936b5d848f62781ae5 (diff)
downloadlinux-c39830a4ce4df09ddef29ac388b062537c559228.tar.xz
octeontx2-pf: cn10k: Config DWRR weight based on MTU
Program SQ, MDQ, TL4 to TL2 transmit scheduler queues' DWRR weight based on DWRR MTU programmed at NIX_AF_DWRR_RPM_MTU. The DWRR MTU from admin function is retrieved via mbox. On OcteaonTx2 silicon, admin function driver responds with DWRR MTU as '1'. This helps to avoid silicon specific transmit scheduler DWRR quantum/weight configuration logic. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h')
-rw-r--r--drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h
index 1a1ae334477d..e07723d71a26 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h
@@ -9,6 +9,20 @@
#include "otx2_common.h"
+static inline int mtu_to_dwrr_weight(struct otx2_nic *pfvf, int mtu)
+{
+ u32 weight;
+
+ /* On OTx2, since AF returns DWRR_MTU as '1', this logic
+ * will work on those silicons as well.
+ */
+ weight = mtu / pfvf->hw.dwrr_mtu;
+ if (mtu % pfvf->hw.dwrr_mtu)
+ weight += 1;
+
+ return weight;
+}
+
void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx);
int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);