diff options
| author | Geetha sowjanya <gakula@marvell.com> | 2021-09-28 08:55:26 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-09-28 16:10:24 +0300 |
| commit | af3826db74d184bc9c2c9d3ff34548e5f317a6f3 (patch) | |
| tree | 836de45caa99a753010ba58e732f6d1969f731e5 /drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | |
| parent | 13d45964c1b4cc8cc5b3693a4b2ba4992eea4370 (diff) | |
| download | linux-af3826db74d184bc9c2c9d3ff34548e5f317a6f3.tar.xz | |
octeontx2-pf: Use hardware register for CQE count
Current driver uses software CQ head pointer to poll on CQE
header in memory to determine if CQE is valid. Software needs
to make sure, that the reads of the CQE do not get re-ordered
so much that it ends up with an inconsistent view of the CQE.
To ensure that DMB barrier after read to first CQE cacheline
and before reading of the rest of the CQE is needed.
But having barrier for every CQE read will impact the performance,
instead use hardware CQ head and tail pointers to find the
valid number of CQEs.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 78df173e6df2..4c3dbade8cfb 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -1006,6 +1006,9 @@ int otx2_config_nix_queues(struct otx2_nic *pfvf) return err; } + pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, + NIX_LF_CQ_OP_STATUS); + /* Initialize work queue for receive buffer refill */ pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, sizeof(struct refill_work), GFP_KERNEL); |