summaryrefslogtreecommitdiff
path: root/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h
diff options
context:
space:
mode:
authorIlan Tayari <ilant@mellanox.com>2017-04-18 12:54:27 +0300
committerSaeed Mahameed <saeedm@mellanox.com>2017-06-27 16:36:47 +0300
commitc43051d72a8dc4a00d49db27292a76d26e8df7af (patch)
tree6abf84e888517ba7933cc193fe09420b8f68c7a3 /drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h
parent537a50574175a2b68b0612ffb48cb044a394c7b4 (diff)
downloadlinux-c43051d72a8dc4a00d49db27292a76d26e8df7af.tar.xz
net/mlx5: FPGA, Add SBU bypass and reset flows
The Innova FPGA includes shell hardware and Sandbox-Unit (SBU) hardware. The shell hardware is handled by mlx5_core itself, while the SBU is handled by a client driver. Reset the SBU to a well-known initial state when initializing a new device, and set the FPGA to bypass mode when uninitializing a device. This allows the client driver to assume that its device has been reset when a new device is detected. During SBU reset, the FPGA is put into SBU-bypass mode. In this mode packets do not pass through the SBU, so it cannot affect the network data stream at all. A factory-image does not have an SBU, so skip these flows. Signed-off-by: Ilan Tayari <ilant@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h')
-rw-r--r--drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h b/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h
index b851580d846f..8943056163f3 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h
@@ -67,6 +67,7 @@ struct mlx5_fpga_qp_counters {
int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps);
int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
+int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
u32 *fpga_qpn);