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authorStefan Hauser <stefan@shauser.net>2016-07-01 23:35:03 +0300
committerDavid S. Miller <davem@davemloft.net>2016-07-02 21:48:58 +0300
commitb291c418172f2cfbe009d81cd9a92f7a2de7c579 (patch)
treeb879e2002b06d030368ce56df408d883b6514d4e /drivers/net/geneve.c
parent373819ec391de0d11f63b10b2fb69ef2854236ca (diff)
downloadlinux-b291c418172f2cfbe009d81cd9a92f7a2de7c579.tar.xz
net: phy: dp83867: Fix initialization of PHYCR register
When initializing the PHY control register, the FIFO depth bits are written without reading the previous register value, i.e. all other bits are overwritten with zero. This disables automatic MDI-X configuration, which is enabled by default. Fix initialization by doing a read/modify/write operation. Signed-off-by: Stefan Hauser <stefan@shauser.net> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/geneve.c')
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