diff options
| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2020-03-20 00:16:48 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-03-24 06:52:27 +0300 |
| commit | 7b005a1742be4608480d9d151aec42170a06cbee (patch) | |
| tree | ad1fc3c639ee965ba6ebc6117fc73152e5b8b5a5 /drivers/net/phy/mscc/mscc.h | |
| parent | da206d65f2b293274f8082a26da4e43a1610da54 (diff) | |
| download | linux-7b005a1742be4608480d9d151aec42170a06cbee.tar.xz | |
net: phy: mscc: configure both RX and TX internal delays for RGMII
The driver appears to be secretly enabling the RX clock skew
irrespective of PHY interface type, which is generally considered a big
no-no.
Make them configurable instead, and add TX internal delays when
necessary too.
While at it, configure a more canonical clock skew of 2.0 nanoseconds
than the current default of 1.1 ns.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/mscc/mscc.h')
| -rw-r--r-- | drivers/net/phy/mscc/mscc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index 99e2d20596ad..0f04afd81816 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -178,6 +178,8 @@ enum rgmii_clock_delay { #define MSCC_PHY_RGMII_CNTL 20 #define RGMII_RX_CLK_DELAY_MASK 0x0070 #define RGMII_RX_CLK_DELAY_POS 4 +#define RGMII_TX_CLK_DELAY_MASK 0x0007 +#define RGMII_TX_CLK_DELAY_POS 0 #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21 #define MSCC_PHY_WOL_MID_MAC_ADDR 22 |