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authorDavid S. Miller <davem@davemloft.net>2016-01-21 23:04:59 +0300
committerDavid S. Miller <davem@davemloft.net>2016-01-21 23:04:59 +0300
commit8e0c2ab262b804f87d26499695e6bfa5f366780c (patch)
tree866c619b7d870549edece4fea697835d572ab01b /drivers/net/phy
parent2c832293e09be2f998ea916650927c8ccd5b4b3b (diff)
parente308cb835c56e7a8b93664797925549a42df8e68 (diff)
downloadlinux-8e0c2ab262b804f87d26499695e6bfa5f366780c.tar.xz
Merge branch 'mvneta-multi-clk'
Jisheng Zhang says: ==================== net: mvneta: support more than one clk Some platforms may provide more than one clk for the mvneta IP, for example Marvell BG4CT provides "core" clk for the mac core, and "axi" clk for the AXI bus logic. This series tries to addess the "more than one clk" issue. Note: to support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't have mbus concept etc. Since v2: - Name the optional clock as "bus", which is a bit more flexible. Since v1: - Add Thomas Acks to patch1 and patch2. - make sure the headers are really sorted (some headers are still unsorted in v1). - disable axi clk before disabling core clk, Thank Thomas. - update dt binding as Thomas suggested. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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