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authorFelix Fietkau <nbd@openwrt.org>2010-04-26 23:04:35 +0400
committerJohn W. Linville <linville@tuxdriver.com>2010-04-28 00:09:18 +0400
commit6b42e8d03bef975085c0397806d00fbd1df67eb8 (patch)
tree42ddfa6f922ad677ee55355822c555de2a11cb10 /drivers/net/wireless/ath/ath9k/ar9002_phy.c
parent5b75d0fca5b8cd2657fb240f2112e272a115b2f9 (diff)
downloadlinux-6b42e8d03bef975085c0397806d00fbd1df67eb8.tar.xz
ath9k_hw: fix fast clock handling for 5GHz channels
Combine multiple checks that were supposed to check for the same conditions, but didn't. Always enable fast PLL clock on AR9280 2.0 Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9002_phy.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.c16
1 files changed, 6 insertions, 10 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
index 18cfe1a9781c..ed314e89bfe1 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -455,16 +455,12 @@ static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
if (chan && IS_CHAN_5GHZ(chan)) {
- pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
-
-
- if (AR_SREV_9280_20(ah)) {
- if (((chan->channel % 20) == 0)
- || ((chan->channel % 10) == 0))
- pll = 0x2850;
- else
- pll = 0x142c;
- }
+ if (IS_CHAN_A_FAST_CLOCK(ah, chan))
+ pll = 0x142c;
+ else if (AR_SREV_9280_20(ah))
+ pll = 0x2850;
+ else
+ pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
} else {
pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
}