Merge branch 'pci/ctrl/qcom'

- Add PHY clock source implementation (Dmitry Baryshkov)

- Use new clk_regmap_phy_mux_ops for gcc-sm8450 and gcc-sc7280 PCIe pipe
  clocks (Dmitry Baryshkov)

- Set up rev 2.1.0 PARF_PHY before enabling clocks (Christian Marangi)

- Power on PHY before accessing IPQ8074 DBI registers to avoid boot hangs
  (Robert Marko)

- Power on PHY before accessing DBI registers on all variants for
  consistency (Robert Marko)

- Remove unnecessary pipe_clk handling since this is done in PHY drivers
  (Dmitry Baryshkov)

- Drop manual pipe_clk_src handling (Dmitry Baryshkov)

- Move GEN3_RELATED DBI definitions to common dwc header (Baruch Siach)

- Define slot capabilities using generic PCI_EXP_SLTCAP_* macros (Baruch
  Siach)

- Add IPQ60xx support (Selvam Sathappan Periakaruppan)

- Fix DT description typo (Baruch Siach)

- Fix DT "compatibles" typo (Johan Hovold)

- Allow ASPM L1 and substates for 2.7.0 (Krishna chaitanya chundru)

* pci/ctrl/qcom:
  PCI: qcom: Allow ASPM L1 and substates for 2.7.0
  dt-bindings: PCI: qcom: Fix reset conditional
  dt-bindings: PCI: qcom: Fix description typo
  PCI: qcom: Add IPQ60xx support
  PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
  PCI: dwc: Move GEN3_RELATED DBI definitions to common header
  PCI: qcom: Drop manual pipe_clk_src handling
  PCI: qcom: Remove unnecessary pipe_clk handling
  PCI: qcom: Power on PHY before DBI register accesses
  PCI: qcom: Power on PHY before IPQ8074 DBI register accesses
  PCI: qcom: Set up rev 2.1.0 PARF_PHY before enabling clocks
  clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks
  clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks
  clk: qcom: regmap: add PHY clock source implementation

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 16489c629ac2..557e1d22dc63 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -97,6 +97,13 @@
 #define PCIE_MSI_INTR0_MASK		0x82C
 #define PCIE_MSI_INTR0_STATUS		0x830
 
+#define GEN3_RELATED_OFF			0x890
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)
+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS	BIT(13)
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)
+
 #define PCIE_PORT_MULTI_LANE_CTRL	0x8C0
 #define PORT_MLTI_UPCFG_SUPPORT		BIT(7)