Merge branch 'pci/controller/rcar'

- Add generic T_PVPERL macro for the required interval between power being
  stable and PERST# being inactive (Yoshihiro Shimoda)

- Factor out dw_pcie_link_set_max_link_width() (Yoshihiro Shimoda)

- Update PCI_EXP_LNKCAP_MLW so Link Capabilities shows the correct max link
  width (Yoshihiro Shimoda)

- Drop tegra194 PCI_EXP_LNKCAP_MLW setting since dw_pcie_setup() already
  does it (Yoshihiro Shimoda)

- Add dwc support for different dbi and dbi2 register offsets, to be used
  for R-Car Gen4 controllers (Yoshihiro Shimoda)

- Add EDMA_UNROLL capability flag for R-Car Gen4 controllers that don't
  correctly advertise unrolled mapping via their eDMA CTRL register
  (Yoshihiro Shimoda)

- Export dw_pcie_ep_exit() for use by the modular R-Car Gen4 driver
  (Yoshihiro Shimoda)

- Add .pre_init() and .deinit() hooks for use by R-Car Gen4 controllers
  (Yoshihiro Shimoda)

- Increase snps,dw-pcie DT reg and reg-names maxItems for R-Car Gen4
  controllers (Yoshihiro Shimoda)

- Add rcar-gen4-pci host and endpoint DT bindings and drivers (Yoshihiro
  Shimoda)

- Add Renesas R8A779F0 Device ID to pci_endpoint_test to allow testing on
  R-Car S4-8 (Yoshihiro Shimoda)

* pci/controller/rcar:
  misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller
  MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4
  PCI: rcar-gen4: Add endpoint mode support
  PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode
  dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint
  dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
  dt-bindings: PCI: dwc: Update maxItems of reg and reg-names
  PCI: dwc: endpoint: Introduce .pre_init() and .deinit()
  PCI: dwc: Expose dw_pcie_write_dbi2() to module
  PCI: dwc: Expose dw_pcie_ep_exit() to module
  PCI: dwc: Add EDMA_UNROLL capability flag
  PCI: dwc: endpoint: Add multiple PFs support for dbi2
  PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
  PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling
  PCI: dwc: Add dw_pcie_link_set_max_link_width()
  PCI: Add T_PVPERL macro

1 files changed, 6 insertions, 2 deletions

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index efb4d4754fc8..55ff76e3d384 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -51,8 +51,9 @@
 
 /* DWC PCIe controller capabilities */
 #define DW_PCIE_CAP_REQ_RES		0
-#define DW_PCIE_CAP_IATU_UNROLL		1
-#define DW_PCIE_CAP_CDM_CHECK		2
+#define DW_PCIE_CAP_EDMA_UNROLL		1
+#define DW_PCIE_CAP_IATU_UNROLL		2
+#define DW_PCIE_CAP_CDM_CHECK		3
 
 #define dw_pcie_cap_is(_pci, _cap) \
 	test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
@@ -330,7 +331,9 @@ struct dw_pcie_rp {
 };
 
 struct dw_pcie_ep_ops {
+	void	(*pre_init)(struct dw_pcie_ep *ep);
 	void	(*ep_init)(struct dw_pcie_ep *ep);
+	void	(*deinit)(struct dw_pcie_ep *ep);
 	int	(*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
 			     enum pci_epc_irq_type type, u16 interrupt_num);
 	const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
@@ -342,6 +345,7 @@ struct dw_pcie_ep_ops {
 	 * driver.
 	 */
 	unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
+	unsigned int (*get_dbi2_offset)(struct dw_pcie_ep *ep, u8 func_no);
 };
 
 struct dw_pcie_ep_func {