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authorAgustin Vega-Frias <agustinv@codeaurora.org>2017-03-31 21:13:43 +0300
committerWill Deacon <will.deacon@arm.com>2017-04-03 20:53:50 +0300
commit3071f13d75f627ed8648535815a0506d50cbc6ed (patch)
tree86feaf03335af1381fb80d87e956e1957d5d1e37 /drivers/perf/Makefile
parentc09adab01e4aeecfa3dfae0946409844400c5901 (diff)
downloadlinux-3071f13d75f627ed8648535815a0506d50cbc6ed.tar.xz
perf: qcom: Add L3 cache PMU driver
This adds a new dynamic PMU to the Perf Events framework to program and control the L3 cache PMUs in some Qualcomm Technologies SOCs. The driver supports a distributed cache architecture where the overall cache for a socket is comprised of multiple slices each with its own PMU. Access to each individual PMU is provided even though all CPUs share all the slices. User space needs to aggregate to individual counts to provide a global picture. The driver exports formatting and event information to sysfs so it can be used by the perf user space tools with the syntaxes: perf stat -a -e l3cache_0_0/read-miss/ perf stat -a -e l3cache_0_0/event=0x21/ Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org> [will: fixed sparse issues] Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/perf/Makefile')
-rw-r--r--drivers/perf/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
index ef24833c94a8..ef0c6b210345 100644
--- a/drivers/perf/Makefile
+++ b/drivers/perf/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_ARM_PMU) += arm_pmu.o
obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
+obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o